Search results for "EURO-DAC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Gerhard H. Büttner	Setting up a retrieval system for design reuse - experiences and acceptance.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Frank Vahid	Procedure exlining: a new system-level specification transformation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Wolfgang Ecker	A classification of design steps and their verification.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Peter Oehler, Christoph Grimm 0001, Klaus Waldschmidt	KANDIS - a tool for construction of mixed analog/digital systems.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Habib Youssef, Sadiq M. Sait, Khalid J. Al-Farra	Timing influenced force directed floorplanning.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Cristian A. Giumale, Hilary J. Kahn	A core information model of VHDL.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Hannes C. Wittmann, Manfred Henftling	Path delay ATPG for standard scan design.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Hans Achatz	Generating several solutions for the scheduling problem in high-level synthesis.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Tianxiong Xue, Ernest S. Kuh	Post routing performance optimization via tapered link insertion and wiresizing.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Gerald Musgrave (eds.)	Proceedings EURO-DAC'95, European Design Automation Conference with EURO-VHDL, Brighton, England, UK, September 18-22, 1995	EURO-DAC	1995	DBLP BibTeX RDF
1	Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli	Timing constraint specification and synthesis in behavioral VHDL.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Alexander N. Soloviev, Alexander L. Stempkovsky	Model of conceptual design of complex electronic systems.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Jürgen Schubert, Arno Kunzmann, Wolfgang Rosenstiel	Reduced design time by load distribution with CAD framework methodology information.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Rainer Schlör, Franz Korf	Verification of a production cell controller using symbolic timing diagrams.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Wolfgang Ecker	Semi-dynamic scheduling of synchronization-mechanisms.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Frank Vahid, Daniel D. Gajski	Closeness metrics for system-level functional partitioning.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Santhanam Srinivasan, Niraj K. Jha	Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Clay Gloster, Franc Brglez	Partial scan selection for user-specified fault coverage.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Flávio Rech Wagner	Design management requirements for hardware description languages.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Armin Englmaier	Mesh current method for computing the current distribution in planar conductor surfaces and possible applications in circuit simulation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Katsuhiko Shirai, Jin Hiwatashi	A design system for special purpose processors based on architectures for distributed processing.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Ansgar Bredenfeld	Cooperative concurrency control for design environments.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	E. Leroux, Flavio G. Canavero, G. Vecchi	Prediction of radiated electromagnetic emissions from PCB traces based on green dyadics.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Andrew A. Duncan, David C. Hendry	Area efficient DSP datapath synthesis.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Makarand Joshi, Hideaki Kobayashi	Quantifying design productivity: an effort distribution analysis.	EURO-DAC	1995	DBLP DOI BibTeX RDF	design productivity, effort-distribution, graphical HDL, textual HDL, human interaction, ISO 9000, design resources, design quality
1	Konstantin O. Petrosjanc, Igor A. Kharitonov, N. I. Rybov, Peter P. Maltcev	Software system for semiconductor devices, monolith and hybrid ICs thermal analysis.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Steve Hodgson, Zak Shaar, Andy Smith	A high performance VHDL simulator for large systems design.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel	Debugging of behavioral VHDL specifications by source level emulation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Maher Rahmouni, Ahmed Amine Jerraya	Formulation and evaluation of scheduling techniques for control flow graphs.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Markus Schwiegershausen, Peter Pirsch	A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Jean Michel Daga, Michel Robert, Daniel Auvergne	Delay modelling improvement for low voltage applications.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Victor V. Toporkov	Performance-complexity analysis in hardware-software codesign for real-time systems.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Thomas Gabler, Sabine März-Rössel	An approach to guided incremental specification.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Ronald B. Stewart	LibQA - library quality assurance for VHDL synthesis and simulation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Jan Andersson	A DSP ASIC design flow based on VHDL and ASIC-emulation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	M. M. Kamal Hashmi, Alistair C. Bruce	Design and use of a system-level specification and verification methodology.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Peter Conradi	Information model of a compound graph representation for system and architecture level design.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Pierre G. Paulin, Jean Fréhel, Michel Harrand, Elisabeth Berrebi, Clifford Liem, François Naçabal, Jean-Claude Herluison	High-level synthesis and codesign methods: an application to a videophone codec.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Polen Kission, Hong Ding, Ahmed Amine Jerraya	VHDL based design methodology for hierarchy and component re-use.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Sidharta Mohanty, Philip A. Wilsey	System modeling, hardware-software codesign, and mixed modeling with hardware description language.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Ludwig Schwoerer, Matthias Lück, Hartmut Schröder	Integration of VHDL into a system design environment.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Udo Jorczyk, Wilfried Daehn, Oliver Neumann	Fault modeling of differential ECL.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Markus Schütz	How to efficiently build VHDL testbenches.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	On generating compact test sequences for synchronous sequential circuits.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charles L. Saxe	Layout synthesis for datapath designs.	EURO-DAC	1995	DBLP DOI BibTeX RDF	routing, placement, layout, channel, datapath, bit-slice
1	Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De Man	Timing optimization by bit-level arithmetic transformations.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Vladimir B. Dmitriev-Zdorov, Bernhard Klaassen	An improved relaxation approach for mixed system analysis with several simulation tools.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Joris van den Hurk, Edwin Dilling	System level design, a VHDL based approach.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Thomas Benner, Rolf Ernst, Achim Österling	Scalable performance scheduling for hardware-software cosynthesis.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Alicja Pierzynska, Slawomir Pilarski	Quality considerations in delay fault testing.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng	On implementation choices for iterative improvement partitioning algorithms.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	John Willis, Zhiyuan Li 0001, Tsang-Puu Lin	Use of embedded scheduling to compile VHDL for effective parallel simulation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Vincent Moser, Hans Peter Amann, Pascal Nussbaum, Fausto Pellandini	Generating VHDL-A - like models using ABSynth.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	D. Wagenblasst, Wolfgang Thronicke	An approach for classification of integrated circuits by a knowledge conserving library concept.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Wolfgang Ecker, Manfred Huber	VHDL-based communication and synchronization synthesis.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Karlheinz Agsteiner, Dieter Monjau, Sören Schulze	Object-oriented high-level modeling of system components for the generation of VHDL code.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	J. Forrest	ODE: output direct state machine encoding.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Zohair Sahraoui, Paul Six, Ivo Bolsens, Hugo De Man	Search space reduction through clustering in test generation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Andrea Finotello, Maurizio Paolini	The VHDL based design of the MIDA MPEG1 audio decoder.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Ronald Herrmann, Thomas Reielts	Verification of a production cell using an automatic verification environment for VHDL.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Carol A. Fields	Creating hierarchy in HDL-based high density FGPA design.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Juha-Pekka Soininen, Tuomo Huttunen, Kari Tiensyrjä, Hannu Heusala	Cosimulation of real-time control systems.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Jerzy J. Dabrowski	Functional-level analog macromodeling with piecewise linear signals.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Naveen Ramineni, Malgorzata Chrzanowska-Jeske, Naveen Buddi	Tree restructuring approach to mapping problem in cellular-architecture FPGAs.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Stefan Schmerler, Yankin Tanurhan, Klaus D. Müller-Glaser	A backplane approach for cosimulation in high-level system specification environments.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Mohamed Romdhani, P. Chambert, Alain Jeffroy, Pierre de Chazelles, Ahmed Amine Jerraya	Composing ActivityCharts/StateCharts, SDL and SAO specifications for codesign in avionics.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Nguyen-Ngoc Bình, Masaharu Imai, Nobuyuki Hikichi	A hardware/software partitioning algorithm for pipelined instruction set processor.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton	Exploiting power-up delay for sequential optimization.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Zahir Moosa, Douglas Edwards	An investigation of iterative routing algorithms.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal	An adaptive distributed algorithm for sequential circuit test generation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Paul Vanoostende, Geert van Wauwe	Issues in low-power design for telecom.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Uwe Gläser, Heinrich Theodor Vierhaus	FOGBUSTER: an efficient algorithm for sequential test generation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Manfred Henftling, Hannes C. Wittmann, Kurt Antreich	A formal non-heuristic ATPG approach.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Rafael Peset Llopis	Path sensitization of combinational circuits and its impact on clocking of sequential systems.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Gerald Spiegel, Albrecht P. Stroele	A unified approach to the extraction of realistic multiple bridging and break faults.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Guido Schumacher, Wolfgang Nebel	Inheritance concept for signals in object-oriented extensions to VHDL.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Srimat T. Chakradhar, Anand Raghunathan	Bottleneck removal algorithm for dynamic compaction and test cycles reduction.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Gianpiero Cabodi, Stefano Quer, Paolo Camurati	Computing subsets of equivalence classes for large FSMs.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Peter T. Breuer, Natividad Martínez Madrid	A native process algebra for VHDL.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Mirella Mastretti	VHDL quality: synthesizability, complexity and efficiency evaluation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Viktor Preis, Renate Henftling, Markus Schütz, Sabine März-Rössel	A reuse scenario for the VHDL-based hardware design flow.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Flávio Rech Wagner, Lia Goldstein Golendziner, Miguel Rodrigues Fornari	A tightly coupled approach to design and data management.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Koen Van Nieuwenhove, Kjell Cools, D. Devisch, Ivo Bolsens, Serge Vernalde, Kim Chansik, R. B. W. Lee, Oh Younguk	ASIC synthesis of a flexible 80 Mbit/s Reed-Solomon Codec.	EURO-DAC	1994	DBLP BibTeX RDF	DFL
1	Olav Schettler	Design tool encapsulation - all problems solved?	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Loïc Vandeventer, Jean François Santucci	Speeding up test pattern generation from behavioral VHDL descriptions containing several processes.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Petru Eles, Marius Minea, Krzysztof Kuchcinski, Zebo Peng	Synthesis of VHDL concurrent processes.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Marek A. Perkowski, Philip Ho	Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Rolf Drechsler, Bernd Becker 0001, Michael Theobald	Fast OFDD based minimization of fixed polarity Reed-Muller expressions.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Jari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuominen	A VHDL-based bus model for multi-PCB system design.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
1	Jan Madsen, Jens P. Brage	Modeling shared variables in VHDL.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
1	Juan Carlos Calderón, Enric Corominas, José M. Tapia, Luis París	Implementation of a SDH STM-N IC for B-ISDN using VHDL based synthesis tools.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
1	France Mendez	VHDL and cyclic corrector codes.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
1	Christopher A. Ryan, Joseph G. Tront	VHDL switch level fault simulation.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Michael Held, Manfred Glesner	Generating compilers for generated datapaths.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Stefan Lenk 0001	Extended timing diagrams as a specification language.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Mario Stefanoni	Static analysis for VHDL model evaluation.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Sayed Mohammad Kia, Sri Parameswaran	Design automation of self checking circuits.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins	An architecture-independent approach to FPGA routing based on multi-weighted graphs.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Konstantin O. Petrosjanc, Peter P. Maltcev	Mixed electrical-thermal and electrical-mechanical simulation of electromechatronic systems using PSpice.	EURO-DAC	1994	DBLP BibTeX RDF
1	Vladimir B. Dmitriyev-Zdorov	Multilevel generalization of relaxation algorithms for circuit simulation.	EURO-DAC	1994	DBLP BibTeX RDF

Publications at "EURO-DAC"( http://dblp.L3S.de/Venues/EURO-DAC )