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Found 725 publication records. Showing 725 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Luis Alberto Cruz Salazar, Jaime H. Carvajal, Oscar A. Rojas, Edgar Chacón Ramírez |
Cyber-Physical System for Industrial Control Automation Based on the Holonic Approach and the IEC 61499 Standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2018 Forum on Specification & Design Languages, FDL 2018, Garching, Germany, September 10-12, 2018, pp. 5-16, 2018, IEEE, 978-1-5386-6418-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Rafael Stahl, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
Automated Redirection of Hardware Accesses for Host-Compiled Software Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2018 Forum on Specification & Design Languages, FDL 2018, Garching, Germany, September 10-12, 2018, pp. 5-16, 2018, IEEE, 978-1-5386-6418-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler |
Extensible and Configurable RISC-V Based Virtual Prototype. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2018 Forum on Specification & Design Languages, FDL 2018, Garching, Germany, September 10-12, 2018, pp. 5-16, 2018, IEEE, 978-1-5386-6418-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | João Bastos, Bram van der Sanden, Olaf Donk, Jeroen Voeten, Sander Stuijk, Ramon R. H. Schiffelers, Henk Corporaal |
Identifying bottlenecks in manufacturing systems using stochastic criticality analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-8, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Mona Safar |
Asil decomposition using SMT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Andrey Mokhov, Alessandro de Gennaro, Ghaith Tarawneh, Jonny Wray, Georgy Lukyanov, Sergey Mileiko, Joe Scott, Alex Yakovlev, Andrew D. Brown |
Language and hardware acceleration backend for graph processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-7, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Reinhard von Hanxleden, Timothy Bourke, Alain Girault |
Real-time ticks for synchronous programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-8, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Essayas Gebrewahid, Zain Ul-Abdin |
Actor fission transformations for executing dataflow programs on manycores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-8, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Enrico Fraccaroli, Francesco Stefanni, Franco Fummi, Mark Zwolinski |
Fault analysis in analog circuits through language manipulation and abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-7, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Stefano Centomo, Michele Lora, Antonio Portaluri, Francesco Stefanni, Franco Fummi |
Automatic generation of cycle-accurate Simulink blocks from hdl ips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-8, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Franco Fummi, Hiren D. Patel, Samarjit Chakraborty (eds.) |
2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017 ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![IEEE, 978-1-5386-4733-2 The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Joaquín Aguado, Michael Mendler, Jia Jie Wang, Bruno Bodin, Partha S. Roop |
Compositional timing-aware semantics for synchronous programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-8, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Liang Wang 0020, Xiaohang Wang 0001, Ho-fung Leung, Terrence S. T. Mak |
Runtime task mapping for lifetime budgeting in many-core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-8, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-8, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Guillaume Baudart, Timothy Bourke, Marc Pouzet |
Symbolic simulation of dataflow synchronous programs with timers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-8, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Arthur Kalsing, Laurent Fesquet, Chouki Aktouf |
Towards consistency checking between HDL and UPF descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Sarah Chabane, Rabéa Ameur-Boulifa, Mohamed Mezghiche |
Rethinking of I/O-automata composition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-7, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao |
Designing reliable cyber-physical systems overview associated to the special session at FDL'16. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-8, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Martin Ring, Jannis Stoppe, Christoph Lüth, Rolf Drechsler |
Change impact analysis for hardware designs from natural language to system level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-7, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ramakrishna Venkata Nittala, Francesco Barchi, Gianvito Urgese, Andrea Acquaviva |
Toolchain integration of runtime variability and aging awareness in multicore platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-8, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Briag Le Nabec, Belgacem Ben Hedia, Jean-Philippe Babau, Mathieu Jan, Hela Guesmi |
Modeling legacy code with BIP: how to reduce the gap between formal description and real-time implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-8, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Nima Khalilzad, Kathrin Rosvall, Ingo Sander |
A modular design space exploration framework for multiprocessor real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-7, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello |
Fault-effect analysis on system-level hardware modeling using virtual prototypes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-7, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Florenc Demrozi, Graziano Pravadelli, Francesco Stefanni |
Automatic generation of self-adaptive transactors from PSL assertions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-7, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Andreas Furtig, Sebastian Steinhorst, Lars Hedrich |
Feature based state space coverage of analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-7, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-8, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Marwan Ammar, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria |
Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-8, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Sara Vinco, Michele Lora, Enrico Macii, Massimo Poncino |
IP-XACT for smart systems design: extensions for the integration of functional and extra-functional models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-8, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Colin F. Snook, Tom J. Kazmierski |
Using event-B and Modelica to evaluate thermal management strategies in many core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-5, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Daian Yue, Vania Joloboff, Frédéric Mallet |
Flexible runtime verification based on logical clock constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-8, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Bram van der Sanden, João Bastos, Jeroen Voeten, Marc Geilen, Michel A. Reniers, Twan Basten, Johan Jacobs, Ramon R. H. Schiffelers |
Compositional specification of functionality and timing of manufacturing systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-8, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Y. Vissers, J. G. M. Mengerink, Ramon R. H. Schiffelers, Alexander Serebrenik, Michel A. Reniers |
Maintenance of specification models in industry using Edapt. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-6, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Niels Thole, Heinz Riener, Görschwin Fey |
Equivalence checking on ESL utilizing a priori knowledge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-8, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Christine Forster, Stefan Buschhorn, Monica Rafaila, Linus Maurer, Georg Pelz |
Cascading metamodels from different sources for performance analysis of a power module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-8, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ana Lucia Varbanescu, Jie Shen 0003 |
Heterogeneous computing with accelerators: an overview with examples. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-8, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ashur Rafiev, Fei Xia, Alexei Iliasov, Rem Gensh, Ali Aalsaud, Alexander B. Romanovsky, Alexandre Yakovlev |
Selective abstraction and stochastic methods for scalable power modelling of heterogeneous systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-7, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ghaith Bany Hamad, Ghaith Kazma, Otmane Aït Mohamed, Yvon Savaria |
Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-7, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Debayan Roy, Licong Zhang, Wanli Chang 0001, Samarjit Chakraborty |
Automated synthesis of cyber-physical systems from joint controller/architecture specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-8, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Yue Lu, Tom J. Kazmierski |
Error-free near-threshold adiabatic CMOS logic in presence of process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-5, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Simon Barner, Alexander Diewald, Fernando Eizaguirre, Anatoly Vasilevskiy, Franck Chauvel |
Building product-lines of mixed-criticality systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016, pp. 1-8, 2016, IEEE, 979-10-92279-17-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Rolf Drechsler, Robert Wille (eds.) |
2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016 ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![IEEE, 979-10-92279-17-7 The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
1 | Fernando Herrera, Pablo Peñil, Eugenio Villar |
Enhancing analysability and time predictability in UML/MARTE component-based application models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 122-129, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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1 | Martin Krammer, Helmut Martin, Zoran Radmilovic, Simon Erker, Michael Karner |
Standard compliant co-simulation models for verification of automotive embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 57-64, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Emad Samuel Malki Ebeid, Julio L. Medina, Davide Quaglia, Franco Fummi |
Extensions to the UML profile for MARTE for distributed embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 99-106, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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1 | David de la Fuente, Jesús Barba, Xerach Peña, Juan Carlos López 0001, Pablo Peñil, Pablo Pedro Sanchez |
Building a dynamically reconfigurable system through a high development flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 107-114, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz |
Architectural system modeling for correct-by-construction RTL design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 90-97, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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1 | Robert Lajos Bücs, Luis Gabriel Murillo, Ekaterina Korotcenko, Gaurav Dugge, Rainer Leupers, Gerd Ascheid, Andreas Ropers, Markus Wedler, Andreas Hoffmann 0002 |
Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 49-56, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Sara Vinco, Michele Lora, Mark Zwolinski |
Conservative behavioural modelling in systemc-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 65-72, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mejid Kebaili, Katell Morin-Allory, Jean-Christophe Brignone, Dominique Borrione |
Enabler-based synchronizer model for clock domain crossing static verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 11-17, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Quentin Bramas, Wilfried Dron, Mariem Ben Fadhl, Khalil Hachicha, Patrick Garda, Sébastien Tixeuil |
WiSeBat: accurate energy benchmarking of wireless sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 40-47, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Georg Gläser, Gregor Nitsche, Eckhard Hennig |
Temporal decoupling with error-bounded predictive quantum control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 18-23, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Hend Affes, Michel Auguin, François Verdier, Alain Pegatoquet |
A methodology for inserting clock-management strategies in transaction-level models of systemon- chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 24-30, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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1 | |
2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015 ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![IEEE, 978-1-4673-7735-5 The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
1 | Philipp Ittershagen, Kim Grüttner, Wolfgang Nebel |
Mixed-criticality system modelling with dynamic execution mode switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 116-121, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Asier Larrucea, Irune Agirre, Carlos Fernando Nicolás, Jon Pérez 0001, Mikel Azkarate-askasua, Ton Trapman |
Temporal independence validation of an IEC-61508 compliant mixed-criticality system based on multicore partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 130-137, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Cristiano Bacelar de Oliveira, Ricardo Menotti, João M. P. Cardoso, Eduardo Marques |
A special-purpose language for implementing pipelined FPGA-based accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 74-81, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Laurence Pierre |
Towards a toolchain for assertion-driven test sequence generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 82-89, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Xiao Pan, Javier Moreno Molina, Christoph Grimm 0001 |
Modeling power consumption at system-level for design of power integrity-aware AMS-circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015, pp. 32-39, 2015, IEEE, 978-1-4673-7735-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris, Rolf Drechsler |
Automating the translation of assertions using natural language processing techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler |
MetaSMT: a unified interface to SMT-LIB2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-6, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Yasaman Samei Syahkal, Rainer Dömer |
Powermonitor: a versatile API for automated power-aware ESL design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-4, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Julia Seiter 0002, Robert Wille, Ulrich Kühne, Rolf Drechsler |
Automatic refinement checking for formal system models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Christoph Hilken, Julia Seiter 0002, Robert Wille, Ulrich Kühne, Rolf Drechsler |
Verifying consistency between activity diagrams and their corresponding OCL contracts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-7, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Liana Musat, Markus Hubl, Andi Buzo, Georg Pelz, Susanne Kandl, Peter P. Puschner |
Semi-formal representation of requirements for automotive solutions using sysML. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Stefan Wallentowitz, Stefan Rosch, Thomas Wild, Andreas Herkersdorf, Volker Wenzel, Jörg Henkel |
Dependable task and communication migration in tiled manycore system-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Gabriel Hjort Blindell, Christian Menne, Ingo Sander |
Synthesizing code for GPGPUs from abstract formal models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Amani Khecharem, Carlos Gomez, Julien Deantoni, Frédéric Mallet, Robert de Simone |
Execution of heterogeneous models for thermal analysis with a multi-view approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Fernando Herrera, Ingo Sander |
An extensible infrastructure for modeling and time analysis of predictable embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Frank Wawrzik, Javier Moreno Molina, Christoph Grimm 0001 |
A concept for design of embedded systems at semantic level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-4, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Özlem Karaca, Jérôme Kirscher, Linus Maurer, Georg Pelz |
Towards simulation based evaluation of safety goal violations in automotive systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Mahesh Nanjundappa, Sandeep K. Shukla |
Verification of unit and dimensional consistencies in polychronous specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Bastian Haetzer, Martin Radetzki |
A comparison of parallel systemc simulation approaches at RTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | |
Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014 ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![IEEE, 978-2-9530504-9-3 The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
1 | Leandro Gil, Martin Radetzki |
SystemC AMS power electronic modeling with ideal instantaneous switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Iban Ayestaran, Carlos Fernando Nicolás, Jon Pérez 0001, Asier Larrucea, Peter P. Puschner |
A novel modeling framework for time-triggered safety-critical embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Gregor Nitsche, Kim Grüttner, Wolfgang Nebel |
Towards satisfaction checking of power contracts in Uppaal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Christian Sauer 0001, Hans-Martin Blüthgen, Hans-Peter Loeb |
Distributed, loosely-synchronized systemC/TLM simulations of many-processor platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Binghao Bao, Carlos Villarraga, Bernard Schmidt, Dominik Stoffel, Wolfgang Kunz |
A property language for the specification of hardware-dependent embedded system software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Fangyan Li, Eric Dekneuvel, Gilles Jacquemod, Davide Quaglia, Michele Lora, François Pêcheux, Remi Butaud |
Multi-level modeling of wireless embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-8, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Alper Sen 0001, Onder Kalaci |
Hybrid dynamic data race detection in systemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, pp. 1-6, 2014, IEEE, 978-2-9530504-9-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Wei Hong 0005, Jyoti Joshi, Alexander Viehl, Nico Bannow, Angela Kramer, Hendrik Post, Oliver Bringmann 0001, Wolfgang Rosenstiel |
Advanced features for industry-level logging and tracing of C-based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-6, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Tom J. Kazmierski, Torsten Maehne |
Modeling communication and circuit's behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Dominique Borrione, Ashraf M. Salem |
Application of formal methods for design space exploration and refinement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Cristian Ferent, Alex Doboli |
Modeling the analog circuit design feature variety. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-7, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Fernando Herrera, Ingo Sander |
Combining analytical and simulation-based design space exploration for time-critical systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-8, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Gjalt de Jong, Julio L. Medina |
Model driven engineering at work. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Ruomin Wang, Julien Denoulet, Sylvain Feruglio, Farouk Vallette, Patrick Garda |
Modeling of signal integrity in bus communications with timed data flow SystemC-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-6, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Liyuan Zhang 0001, Michael Glaß, Nils Ballmann, Jürgen Teich |
Bridging algorithm and ESL design: Matlab/Simulink model transformation and validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-8, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Serge Garcia Sabiro |
Event-driven (RN) modeling for AMS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-8, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Matthias Sauppe, Thomas Horn, Erik Markert, Ulrich Heinkel, Hans-Werner Sahm, Klaus-Holger Otto |
Optimal component selection for energy-efficient systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-8, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Benny Höckner, Petra Hofstedt, Sascha Kaltschmidt, Peter Sauer, Thilo Vörtler |
Design space exploration for cyber physical system design using constraint solving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-4, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Frank Oppenheimer, Martin Radetzki |
Simulation analysis and validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Dave Rich |
The unique challenges of debugging design and verification code jointly in SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-7, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Christoph Grimm 0001, Emmanuelle Encrenaz |
Verification of heterogeneous systems: Theory and industrial experiences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Marcus Eggenberger, Martin Radetzki |
Fine grained adaptive simulation with application to NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-8, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Jonathan Bromley |
If SystemVerilog is so good, why do we need the UVM? Sharing responsibilities between libraries and the core language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-7, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Dogan Ulus, Alper Sen 0001, I. Faik Baskaya |
Integrating circuit analyses for assertion-based verification of programmable AMS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-8, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Kaiming Ho |
SystemVerilog: The new standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Christian Zebelein, Christian Haubelt, Joachim Falk, Tobias Schwarzer, Jürgen Teich |
Representing mapping and scheduling decisions within dataflow graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-8, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
1 | Julio L. Medina, Gjalt de Jong |
Modeling languages extensions and best practices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
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