| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Omid Sarbishei, Yu Pang, Katarzyna Radecka |
Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks.  |
HLDVT  |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Samar Abdi |
Automatic generation of host-compiled timed TLMs for high level design. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | John Sanguinetti, Eugene Zhang |
The relationship of code coverage metrics on high-level and RTL code. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Satrajit Chatterjee, Michael Kishinevsky, Ümit Y. Ogras |
Quick formal modeling of communication fabrics to enable verification. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon |
Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicola Bombieri, Giuseppe Di Guglielmo, Luigi Di Guglielmo, Michele Ferrari, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Alessandro Venturelli |
HIFSuite: Tools for HDL code conversion and manipulation. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicholas Donataccio, Hao Zheng |
An improvement in decomposed reachability analysis for symbolic model checking. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Stefano Soffia, Marco Roveri |
Semi-formal functional verification by EFSM traversing via NuSMV. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Steininger, Michael Velten |
Model reduction techniques for the formal verification of hardware dependent software. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Alper Sen 0001, Magdy S. Abadir |
Coverage metrics for verification of concurrent SystemC designs using mutation testing. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicola Bombieri, Franco Fummi, Valerio Guarnieri |
Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Weiwei Chen 0001, Xu Han 0002, Rainer Dömer |
ESL design and multi-core validation using the System-on-Chip Environment. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Bart Vermeulen, Kees Goossens |
Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurizio Caramia, Michele Fabiano, Andrea Miele, Roberto Piazza, Paolo Prinetto |
Automated synthesis of EDACs for FLASH memories with user-selectable correction capability. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yogesh S. Mahajan, Sharad Malik |
Utility of transaction-level hardware models in refinement checking. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wolfgang Müller 0003, Marcio F. da S. Oliveira, Henning Zabel, Markus Becker 0001 |
Verification of real-time properties for Hardware-dependent Software. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming Gao, Kwang-Ting Cheng |
A case study of Time-Multiplexed Assertion Checking for post-silicon debugging. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hoang Minh Le 0001, Daniel Große, Rolf Drechsler |
Towards analyzing functional coverage in SystemC TLM property checking. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | |
IEEE International High Level Design Validation and Test Workshop, HLDVT 2010, Anaheim, CA, USA, 10-12 June 2010 |
HLDVT |
2010 |
DBLP BibTeX RDF |
|
| 1 | Nicola Nicolici, Ho Fai Ko |
Design-for-debug for post-silicon validation: Can high-level descriptions help? |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Miroslav N. Velev, Ping Gao 0002 |
Exploiting hierarchical encodings of equality to design independent strategies in parallel SMT decision procedures for a logic of equality. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Maheshwar Chandrasekar, Michael S. Hsiao |
Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ziyad Hanna, Thomas F. Melham |
A symbolic execution framework for algorithm-level modelling. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumit Ahuja, Sandeep K. Shukla |
MCBCG: Model Checking Based Sequential Clock-Gating. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sven Verdoolaege, Martin Palkovic, Maurice Bruynooghe, Gerda Janssens, Francky Catthoor |
Experience with widening based equivalence checking in realistic multimedia systems. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Debapriya Chatterjee, Valeria Bertacco |
Activity-based refinement for abstraction-guided simulation. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sung-Boem Park, Subhasish Mitra |
IFRA: Post-silicon bug localization in processors. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Huan Chen 0001, João Marques-Silva 0001 |
TG-PRO: A new model for SAT-based ATPG. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajat Subhra Chakraborty, Seetharam Narasimhan, Swarup Bhunia |
Hardware Trojan: Threats and emerging solutions. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyank Kalla, Prabhat Mishra 0001 |
Chairs' welcome message. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason G. Tong, Marc Boule, Zeljko Zilic |
Airwolf-TG: A test generator for assertion-based dynamic verification. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Lingyi Liu, Shobha Vasudevan |
STAR: Generating input vectors for design validation by static analysis of RTL. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | |
IEEE International High Level Design Validation and Test Workshop, HLDVT 2009, San Francisco, CA, USA, 4-6 November 2009 |
HLDVT |
2009 |
DBLP BibTeX RDF |
|
| 1 | Yongquan Fan, Zeljko Zilic |
A versatile scheme for the validation, testing and debugging of High Speed Serial Interfaces. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Lisherness, Kwang-Ting Cheng |
An instrumented observability coverage method for system validation. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, Sunil P. Khatri |
Fault table generation using Graphics Processing Units. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Gianpiero Cabodi, Leandro Dipietro, Marco Murciano, Sergio Nocco |
Exploiting incrementality in SAT-based search for multiple equivalence-preserving transformations in combinational circuits. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sunil R. Shenoy |
Leadership Microprocessors: Validation, debug and test. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurizio Caramia, Stefano Di Carlo, Michele Fabiano, Paolo Prinetto |
FLARE: A design environment for FLASH-based space applications. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | In-Ho Moon, Kevin Harer |
Learning from constraints for formal property checking. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Bin Xue, Sandeep K. Shukla |
Analysis of scheduled Latency insensitive systems with periodic clock calculus. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Zheng |
A coordinated reachability analysis method for modular verification of asynchronous designs. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sean Safarpour, Andreas G. Veneris |
Automated debugging with high level abstraction and refinement. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | J. Hao, Valeria Bertacco |
PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Susmit Jha, Wenchao Li 0001, Sanjit A. Seshia |
Localizing transient faults using dynamic bayesian networks. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara |
RTL DFT techniques to enhance defect coverage for functional test sequences. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Subodh Sharma 0001, Ganesh Gopalakrishnan, Eric Mercer |
Dynamic verification of Multicore Communication applications in MCAPI. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Bijan Alizadeh, Masahiro Fujita |
Modular arithmetic decision procedure with auto-correction mechanism. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Geist, Oded Vaida |
A method for hunting bugs that occur due to system conflicts. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kenneth M. Zick, John P. Hayes |
High-level vulnerability over space and time to insidious soft errors. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefano Cordibella, Franco Fummi, Giovanni Perbellini, Davide Quaglia |
A HW/SW co-simulation framework for the verification of multi-CPU systems. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Miron Abramovici |
In-system silicon validation using a reconfigurable platform. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hassan Hatefi-Ardakani, Amir Masoud Gharehbaghi, Shaahin Hessabi |
Timing verification of distributed network systems at higher levels of abstraction. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Neal Stollon |
On Chip Instrument application to SoC analysis. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Homa Alemzadeh, Zainalabedin Navabi, Stefano Di Carlo, Alberto Scionti, Paolo Prinetto |
Functional testing approaches for "BIFST-able" tlm_fifo. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang |
Temporal parallel gate-level timing simulation. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Avi Ziv, Chris Wilson, Adnan Hamid, Joerg Grosse |
Special session - What's so intelligent about testbenches? |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Shireesh Verma, Srinath Atluri, Valeria Bertacco, Mark Glasser, Badri Gopalan, Sharon Rosenberg |
Panel: Software practices for verification/testbench management. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Torsten Schober, Shimon Landa, Bodo Hoppe, Ronny Morad |
IBM system z functional and performance verification using X-Gen. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefano Di Carlo, Paolo Prinetto, Alberto Scionti, Zaid Al-Ars |
Automating defects simulation and fault modeling for SRAMs. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ankur Parikh, Michael S. Hsiao |
On dynamic switching of navigation for semi-formal design validation. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic |
Proving and disproving assertion rewrite rules with automated theorem provers. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | |
IEEE International High Level Design Validation and Test Workshop, HLDVT 2008, Incline Village, NV, USA, November 19-21, 2008 |
HLDVT |
2008 |
DBLP BibTeX RDF |
|
| 1 | Daniel Gil, Luis J. Saiz, Joaquin Gracia, Juan Carlos Baraza, Pedro J. Gil |
Injecting intermittent faults for the dependability validation of commercial microcontrollers. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kiran Ramineni, Shireesh Verma, Ian G. Harris |
Evaluation of an efficient control-oriented coverage metric. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita |
Multi-level Bounded Model Checking to detect bugs beyond the bound. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei-Lin Li, Tsung-Tang Chen, Po-Han Wu, Jiann-Chyi Rau |
Test slice difference technique for low power encoding. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Prakash Math, David Hoenig |
Janus: A novel use of Formal Verification for targeted behavioral equivalence. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kapila Udawatta, Sergey Maidanov, Mehdi Ehsanian, Surya Musunuri |
Test and validation of a non-deterministic system - True Random Number Generator. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Giuseppe Di Guglielmo, Franco Fummi, Mark Hampton, Graziano Pravadelli, Francesco Stefanni |
The role of parallel simulation in functional verification. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Bhanu Kapoor, John Goodenough 0001, Shankar Hemmady, Shireesh Verma, Manuel A. d'Abreu, Kaushik Roy 0001 |
Panel: SoC power management implications on validation and testing. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoxi Xu, Cheng-Chew Lim, Michael J. Liebelt |
Positioning test-benches and test-programs in interaction-oriented system-on-chip verification. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Farzin Karimi |
Applications of decorator and observer design patterns in functional verification. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Íñigo Ugarte, Pablo Sanchez |
Optimized coverage-directed random simulation. |
HLDVT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan |
Reliable network-on-chip based on generalized de Bruijn graph. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric Cheung, Xi Chen 0024, Fur-Shing Tsai, Yu-Chin Hsu, Harry Hsieh |
Bridging RTL and gate: correlating different levels of abstraction for design debugging. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Marco Murciano, Massimo Violante |
Validating the dependability of embedded systems through fault injection by means of loadable kernel modules. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric Cheung, Harry Hsieh, Felice Balarin |
Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Bijan Alizadeh, Masahiro Fujita |
A novel formal approach to generate high-level test vectors without ILP and SAT solvers. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Lucky L. Chi Yu Lo, Samar Abdi |
Automatic TLM generation for C-Based MPSoC design. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric Cheung, Harry Hsieh, Felice Balarin |
Framework for fast and accurate performance simulation of multiprocessor systems. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Tommy Bojan, Manuel Aguilar Arreola, Eran Shlomo, Tal Shachar |
Functional coverage measurements and results in post-Silicon validation of Core™2 duo family. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Krste Asanovic |
Transactors for parallel hardware and software co-design. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Shireesh Verma, Ian G. Harris, Kiran Ramineni |
Automatic generation of functional coverage models from CTL. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | |
IEEE International High Level Design Validation and Test Workshop, HLDVT 2007, Irvine, CA, USA, November 7-9, 2007 |
HLDVT |
2007 |
DBLP BibTeX RDF |
|
| 1 | Tommy Bojan, Igor Frumkin, Robert Mauri |
Intel's Post Silicon functional validation approach. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Noureddine Chabini, Wayne H. Wolf |
An approach for computing the initial state for retimed synchronous sequential circuits. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Lv 0001, Tong Xu, Yang Zhao, Huawei Li 0001, Xiaowei Li 0001 |
Bug analysis and corresponding error models in real designs. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kiran Ramineni, Ian G. Harris, Shireesh Verma |
Improving feasible interactions among multiple processes. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaofang Chen, Yu Yang 0013, Michael Delisi, Ganesh Gopalakrishnan, Ching-Tsun Chou |
Hierarchical cache coherence protocol verification one level at a time through assume guarantee. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Joseph Buck, Dong Wang, Yunshan Zhu |
Formal model construction using HDL simulation semantics. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Onur Guzey, Li-C. Wang |
Coverage-directed test generation through automatic constraint extraction. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Deepak Mathaikutty, Sumit Ahuja, Ajit Dingankar, Sandeep K. Shukla |
Model-driven test generation for system level validation. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jai Kumar, Catherine Ahlschlager, Peter Isberg |
Post-silicon verification methodology on Sun's UItraSPARC T2. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Alberto Bosio |
Automating the IEEE std.1500 compliance verification for embedded cores. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel |
FFT Compiler: from math to efficient hardware HLDVT invited short paper. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Gérard Berry |
Circuit design and verication with Esterel v7 and Esterel Studio. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Shakti Kapoor |
Challenges in post-silicon verification of IBM's Cell/B.E. and other game processors. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sunil Kakkar, Janick Bergeron, Brian Bailey, Harry Foster, Ian Harris |
Panel: Unified approach leading to a seamlessly evolving test bench for all phases of a multi-core design, validation and production test. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Ilya Wagner, Valeria Bertacco, Igor L. Markov |
Automatic error diagnosis and correction for RTL designs. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
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