Search results for "ISSS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Gunnar Braun, Andreas Hoffmann 0002, Achim Nohl, Heinrich Meyr	Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description.	ISSS	2001	DBLP DOI BibTeX RDF
1	Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta 0001, Preeti Ranjan Panda	New Design Paradigms: What Needs to be Standardized?.	ISSS	2001	DBLP DOI BibTeX RDF
1	Luca Benini, Giovanni De Micheli	Powering Networks on Chips: Energy-Efficient and Reliable Interconnect Design for SoCs.	ISSS	2001	DBLP DOI BibTeX RDF
1	Guang R. Gao	Bridging the gap between ISA compilers and silicon compilers a challenge for future SoC design.	ISSS	2001	DBLP DOI BibTeX RDF
1	Marco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen	Phase coupled operation assignment for VLIW processors with distributed register files.	ISSS	2001	DBLP DOI BibTeX RDF
1	Prabhat Mishra 0001, Nikil D. Dutt, Alexandru Nicolau	Functional abstraction driven design space exploration of heterogeneous programmable architectures.	ISSS	2001	DBLP DOI BibTeX RDF
1	Haris Lekatsas, Jörg Henkel, Wayne H. Wolf	Design and simulation of a pipelined decompression architecture for embedded systems.	ISSS	2001	DBLP DOI BibTeX RDF
1	Ansgar Stammermann, Lars Kruse, Wolfgang Nebel, Alexander Pratsch, Eike Schmidt, Milan Schulte, Arne Schulz	System level optimization and design space exploration for low power.	ISSS	2001	DBLP DOI BibTeX RDF
1	Ahmed Khoumsi	Synthesizing distributed real-time systems modeled by a timed version of a subset of LOTOS.	ISSS	2001	DBLP DOI BibTeX RDF
1	Kyu-won Choi, Abhijit Chatterjee	Efficient instruction-level optimization methodology for low-power embedded systems.	ISSS	2001	DBLP DOI BibTeX RDF
1	Noureddine Chabini, Yvon Savaria	Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques.	ISSS	2001	DBLP DOI BibTeX RDF
1	Radu Muresan, Catherine H. Gebotys	Current consumption dynamics at instruction and program level for a VLIW DSP processor.	ISSS	2001	DBLP DOI BibTeX RDF
1	Abhijit K. Deb, Johnny Öberg, Axel Jantsch	Control and communication performance analysis of embedded DSP systems in the MASIC methodology.	ISSS	2001	DBLP DOI BibTeX RDF
1	Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau	Conditional speculation and its effects on performance and area for high-level snthesis.	ISSS	2001	DBLP DOI BibTeX RDF
1	Román Hermida, El Mostapha Aboulhamid (eds.)	Proceedings of the 14th International Symposium on Systems Synthesis, ISSS 2001, Montrél, Québec, Canada, September 30 - October 3, 2001.	ISSS	2001	DBLP DOI BibTeX RDF
1	Peter Grun, Nikil D. Dutt, Alexandru Nicolau	APEX: Access Pattern Based Memory Architecture Exploration.	ISSS	2001	DBLP DOI BibTeX RDF
1	Lama H. Chandrasena, Priyadarshana Chandrasena, Michael J. Liebelt	An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling.	ISSS	2001	DBLP DOI BibTeX RDF
1	Frederic Doucet, Rajesh K. Gupta 0001, Masato Otsuka, Patrick Schaumont, Sandeep K. Shukla	Interoperability as a design issue in C++ based modeling environments.	ISSS	2001	DBLP DOI BibTeX RDF
1	Peter Petrov, Alex Orailoglu	Data cache energy minimizations through programmable tag size matching to the applications.	ISSS	2001	DBLP DOI BibTeX RDF
1	Per Bjuréus, Axel Jantsch	Performance analysis with confidence intervals for embedded software processes.	ISSS	2001	DBLP DOI BibTeX RDF
1	Antoine Fraboulet, Karen Kodary, Anne Mignotte	Loop fusion for memory space optimization.	ISSS	2001	DBLP DOI BibTeX RDF
1	Pontus Åström, Stefan Johansson, Peter Nilsson 0001	Application of Software design patterns to DSP library design.	ISSS	2001	DBLP DOI BibTeX RDF
1	Samy Meftali, Ferid Gharsalli, Frédéric Rousseau 0001, Ahmed Amine Jerraya	An optimal memory allocation for application-specific multiprocessor system-on-chip.	ISSS	2001	DBLP DOI BibTeX RDF
1	Mahmut T. Kandemir, Ismail Kadayif, Ugur Sezer	Exploiting scratch-pad memory using Presburger formulas.	ISSS	2001	DBLP DOI BibTeX RDF
1	Alessandro Fin, Franco Fummi, Giovanni Perbellini	Soft-cores generation by instruction set analysis.	ISSS	2001	DBLP DOI BibTeX RDF
1	Eui-Young Chung, Luca Benini, Giovanni De Micheli	Source code transformation based on software cost analysis.	ISSS	2001	DBLP DOI BibTeX RDF
1	Marcus T. Schmitz, Bashir M. Al-Hashimi	Considering power variations of DVS processing elements for energy minimisation in distributed systems.	ISSS	2001	DBLP DOI BibTeX RDF
1	JoAnn M. Paul, Arne J. Suppé, Donald E. Thomas	Modeling and simulation of steady state and transient behaviors for emergent SoCs.	ISSS	2001	DBLP DOI BibTeX RDF
1	Preeti Ranjan Panda	SystemC: A Modeling Platform Supporting Multiple Design Abstractions.	ISSS	2001	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto	On-line fault detection in a hardware/software co-design environment.	ISSS	2001	DBLP DOI BibTeX RDF
1	Maria-Cristina V. Marinescu, Martin C. Rinard	High-level automatic pipelining for sequential circuits.	ISSS	2001	DBLP DOI BibTeX RDF
1	Pierre G. Paulin	Embedded systems technologies for application-specific architecture platforms.	ISSS	2001	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Hiroshi Nakamura	The standard SpecC language.	ISSS	2001	DBLP DOI BibTeX RDF
1	Tycho van Meeuwen, Arnout Vandecappelle, Allert van Zelst, Francky Catthoor, Diederik Verkest	System-level interconnect architecture exploration for custom memory organizations.	ISSS	2001	DBLP DOI BibTeX RDF
1	Preeti Ranjan Panda, Luc Séméria, Giovanni De Micheli	Cache-efficient memory layout of aggregate data structures.	ISSS	2001	DBLP DOI BibTeX RDF
1	Feliks J. Welfeld	Network processing in content inspection applications.	ISSS	2001	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen	Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults.	ISSS	2001	DBLP DOI BibTeX RDF
1	Richard Norman	System design of a telecommunication router.	ISSS	2001	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya, Pierre G. Paulin, Richard Norman, Feliks J. Welfeld	Programming models for network processors (Panel).	ISSS	2001	DBLP DOI BibTeX RDF
1	Kaiyu Chen, Sharad Malik, David I. August	Retargetable static timing analysis for embedded software.	ISSS	2001	DBLP DOI BibTeX RDF
1	Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh	A data scheduler for multi-context reconfigurable architectures.	ISSS	2001	DBLP DOI BibTeX RDF
1	Ying Zhao, Sharad Malik, Matthew W. Moskewicz, Conor F. Madigan	Accelerating boolean satisfiability through application specific processing.	ISSS	2001	DBLP DOI BibTeX RDF
1	Om Prakash Gangwal, André Nieuwland, Paul E. R. Lippens	A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems.	ISSS	2001	DBLP DOI BibTeX RDF
1	Miguel Miranda, C. Ghez, Chidamber Kulkarni, Francky Catthoor, Diederik Verkest	Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications.	ISSS	2001	DBLP DOI BibTeX RDF
1	Matthias Meerwein, C. Baumgartner, T. Wieja, W. Glauert	Embedded Systems Verification with FPGA-Enhanced In-Circuit Emulator.	ISSS	2000	DBLP DOI BibTeX RDF
1	Mateo Valero	Architectures for One Billion of Transistors.	ISSS	2000	DBLP DOI BibTeX RDF
1	Cagdas Akturan, Margarida F. Jacome	FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors.	ISSS	2000	DBLP DOI BibTeX RDF
1	Tanja Van Achteren, Rudy Lauwereins, Francky Catthoor	Systematic Data Reuse Exploration Methodology for Irregular Access Patterns.	ISSS	2000	DBLP DOI BibTeX RDF
1	Neal K. Bambha, Shuvra S. Bhattacharyya	A Joint Power/Performance Optimization Algorithm for Multiprocessor Systems using a Period Graph Construct.	ISSS	2000	DBLP DOI BibTeX RDF
1	Warren Savage, John Chilton, Raul Camposano	IP Reuse in the System on a Chip Era.	ISSS	2000	DBLP DOI BibTeX RDF
1	Chanik Park, Soonhoi Ha	Hardware Synthesis from SPDF Representation for Multimedia Applications.	ISSS	2000	DBLP DOI BibTeX RDF
1	Yung-Hsiang Lu, Giovanni De Micheli, Luca Benini	Requester-Aware Power Reduction.	ISSS	2000	DBLP DOI BibTeX RDF
1	Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Nader Bagherzadeh, Hartej Singh	Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization.	ISSS	2000	DBLP DOI BibTeX RDF
1	Martin Grajcar	Conditional Scheduling for Embedded Systems using Genetic List Scheduling.	ISSS	2000	DBLP DOI BibTeX RDF
1	Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Riccardo Scarsi	Battery-Driven Dynamic Power Management of Portable Systems.	ISSS	2000	DBLP DOI BibTeX RDF
1	Juanjo Noguera, Rosa M. Badia	Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures.	ISSS	2000	DBLP DOI BibTeX RDF
1	Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai	Compiler Optimization on Instruction Scheduling for Low Power.	ISSS	2000	DBLP DOI BibTeX RDF
1	Carlo Brandolese, William Fornaciari, Luigi Pomante, Fabio Salice, Donatella Sciuto	A Multi-Level Strategy for Software Power Estimation.	ISSS	2000	DBLP DOI BibTeX RDF
1	Olga Peñalba, José M. Mendías, María C. Molina	Execution Condition Analysis in High Level Synthesis: A Unified Approach.	ISSS	2000	DBLP DOI BibTeX RDF
1	Annette Muth, Georg Färber	SDL as a System Level Specification Language for Application-Specific Hardware in a Rapid Prototyping Environment.	ISSS	2000	DBLP DOI BibTeX RDF
1	Fadi J. Kurdahi, Román Hermida (eds.)	Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000.	ISSS	2000	DBLP BibTeX RDF
1	Tajana Simunic, Giovanni De Micheli, Luca Benini, Mat Hans	Source Code Optimization and Profiling of Energy Consumption in Embedded Systems.	ISSS	2000	DBLP DOI BibTeX RDF
1	Apostolos A. Kountouris, Christophe Wolinski	Hierarchical Conditional Dependency Graphs as a Unifying Design Representation in the CODESIS High-Level Synthesis System.	ISSS	2000	DBLP DOI BibTeX RDF
1	Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Wolfgang Nebel	Lower Bound Estimation for Low Power High-Level Synthesis.	ISSS	2000	DBLP DOI BibTeX RDF
1	Tony Givargis, Frank Vahid, Jörg Henkel	Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores.	ISSS	2000	DBLP DOI BibTeX RDF	silicon platforms, caches, low-power design, estimation, System-on-a-chip, intellectual property, cores, system parameters
1	Luis Alejandro Cortés, Petru Eles, Zebo Peng	Verification of Embedded Systems using a Petri Net based Representation.	ISSS	2000	DBLP DOI BibTeX RDF
1	Rainer Leupers	Code Generation for Embedded Processors.	ISSS	2000	DBLP DOI BibTeX RDF
1	Wander O. Cesário, Zoltan Sugar, Imed Moussa, Ahmed Amine Jerraya	Efficient Integration of Behavioral Synthesis with Existing Design Flows.	ISSS	2000	DBLP DOI BibTeX RDF
1	Marek Jersak, Ying Cai, Dirk Ziegenbein, Rolf Ernst	A Transformational Approach to Constraint Relaxation of a Time-driven Simulation Model.	ISSS	2000	DBLP DOI BibTeX RDF
1	Erik Brockmeyer, Arnout Vandecappelle, Sven Wuytack, Francky Catthoor	Low Power Storage Cycle Budget Distribution Tool Support for Hierarchical Graphs.	ISSS	2000	DBLP DOI BibTeX RDF
1	Vivek Sinha, Frederic Doucet, Chuck Siska, Rajesh K. Gupta 0001, Stan Y. Liao, Abhijit Ghosh	YAML: A Tool for Hardware Design Visualization and Capture.	ISSS	2000	DBLP DOI BibTeX RDF
1	Wolfgang Rosenstiel	Embedded Java.	ISSS	2000	DBLP DOI BibTeX RDF
1	Natalino G. Busá, Albert van der Werf, Marco Bekooij	Scheduling Coarse-Grain Operations for VLIW Processors.	ISSS	2000	DBLP DOI BibTeX RDF
1	Fabian Wolf, Rolf Ernst	Intervals in Software Execution Cost Analysis.	ISSS	2000	DBLP DOI BibTeX RDF
1	Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha	Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design.	ISSS	2000	DBLP DOI BibTeX RDF
1	Jeffrey Kang, Albert van der Werf, Paul E. R. Lippens	Mapping Array Communication onto FIFO Communication - Towards an Implementation.	ISSS	2000	DBLP DOI BibTeX RDF
1	F. Jesús Sánchez, Antonio González 0001	Instruction Scheduling for Clustered VLIW Architectures.	ISSS	2000	DBLP DOI BibTeX RDF
1	Roman L. Lysecky, Frank Vahid, Tony Givargis	Experiments with the Peripheral Virtual Component Interface.	ISSS	2000	DBLP DOI BibTeX RDF	VCI, bus wrappers, interfacing, system-on-a-chip, intellectual property, Cores, on-chip bus
1	Rafael Gadea Gironés, Joaquín Cerdá, Francisco José Ballester-Merelo, Antonio Mocholí Salcedo	Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation.	ISSS	2000	DBLP DOI BibTeX RDF
1	Brian Kelley	On the Rapid Prototyping and Design of a Wireless Communication System on a Chip.	ISSS	1999	DBLP DOI BibTeX RDF
1	Bart Mesman, Carlos A. Alba Pinto, Koen van Eijk	Efficient Scheduling of DSP Code on Processors with Distributed Register Files.	ISSS	1999	DBLP DOI BibTeX RDF
1	Werner De Rammelaere, K. Eckert, T. Lawell, Ralph McGarity, F. Steininger, Patricia Le Moenner, E. Hilkens	Catalyst: A DSIP Design Flow Development in Industry.	ISSS	1999	DBLP DOI BibTeX RDF
1	Takanori Okuma, Tohru Ishihara, Hiroto Yasuura	Real-Time Task Scheduling for a Variable Voltage Processor.	ISSS	1999	DBLP DOI BibTeX RDF
1	Antoine Fraboulet, Guillaume Huard, Anne Mignotte	Loop Alignment for Memory Accesses Optimization.	ISSS	1999	DBLP DOI BibTeX RDF
1	Vincent John Mooney III	Path-based Edge Activation for Dynamic Run-Time Scheduling.	ISSS	1999	DBLP DOI BibTeX RDF
1	Douglas C. Schmidt	Middleware Techniques and Optimizations for Real-Time, Embedded Systems.	ISSS	1999	DBLP DOI BibTeX RDF
1	Rafael Maestre, Milagros Fernández, Román Hermida, Nader Bagherzadeh	A Framework for Scheduling and Context Allocation in Reconfigurable Computing.	ISSS	1999	DBLP DOI BibTeX RDF
1	Jens Horstmannshoff, Heinrich Meyr	Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs.	ISSS	1999	DBLP DOI BibTeX RDF
1	Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau	RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions.	ISSS	1999	DBLP DOI BibTeX RDF
1	Fei Chen, Edwin Hsing-Mean Sha	Loop Scheduling and Partitions for Hiding Memory Latencies.	ISSS	1999	DBLP DOI BibTeX RDF
1	Praveen K. Murthy, Shuvra S. Bhattacharyya	A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications.	ISSS	1999	DBLP DOI BibTeX RDF
1	Brian M. Barry, John Duimovich	Embedded Java: Techniques and Applications.	ISSS	1999	DBLP DOI BibTeX RDF
1	Roman L. Lysecky, Frank Vahid, Rilesh Patel, Tony Givargis	Pre-Fetching for Improved Core Interfacing.	ISSS	1999	DBLP DOI BibTeX RDF	interfacing, system-on-a-chip, intellectual property, Cores, on-chip bus
1	Khurram Muhammad, Kaushik Roy 0001	A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters.	ISSS	1999	DBLP DOI BibTeX RDF
1	Paulo Centoducatte, Ricardo Pannain, Guido Araujo	Compressed Code Execution on DSP Architectures.	ISSS	1999	DBLP DOI BibTeX RDF
1	Chantal Ykman-Couvreur, Jurgen Lambrecht, Diederik Verkest, Francky Catthoor, Hugo De Man	Exploration and Synthesis of Dynamic Data Sets in Telecom Network Applications.	ISSS	1999	DBLP DOI BibTeX RDF
1	Eric M. Foster	Design of a Set-Top Box System on a Chip.	ISSS	1999	DBLP DOI BibTeX RDF
1	Daniel Gajski, Reinaldo A. Bergamaschi	Panel Statement: System-Level Design: Designers' Wish List vs. Reality.	ISSS	1999	DBLP DOI BibTeX RDF
1	Carlos Carreras, Juan A. López, Octavio Nieto-Taladriz	Bit-Width Selection for Data-Path Implementations.	ISSS	1999	DBLP DOI BibTeX RDF
1		Proceedings of the 12th International Symposium on System Synthesis, ISSS '99, Boca Raton, Florida, USA, November 1-4, 1999.	ISSS	1999	DBLP BibTeX RDF

Publications at "ISSS"( http://dblp.L3S.de/Venues/ISSS )