Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Raphael Segabinazzi Ferreira, Jörg Nolte |
Low latency reconfiguration mechanism for fine-grained processor internal functional units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone |
On the evaluation of SEU effects in GPGPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Pablo A. Ferreyra, Juan A. Fraire, Fabian Gomez, Raoul Velazco, Daniel Sánchez 0013, Dardo Vinas Viscardi |
Delay-Tolerant Wireless Networks on Chip: Preliminary Analysis and Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | |
IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019 ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![IEEE, 978-1-7281-1756-0 The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
1 | Cezar Antônio Rigo, Lucas M. Luza, Elder Dominghini Tramontin, Victor M. Goncalves Martins, Sara Vega Martínez, Leonardo Kessler Slongo, Laio Oriel Seman, Luigi Dilillo, Fabian Luis Vargas 0001, Eduardo A. Bezerra |
A Fault-Tolerant Reconfigurable Platform for Communication Modules of Satellites. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Thiago Santos Copetti, Tiago R. Balen, E. Brum, C. Aquistapace, Leticia Bolzani Poehls |
A Comparative Study Between FinFET and CMOS-Based SRAMs under Resistive Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Luiz G. S. Dias, Carlos J. González, Fernando J. Boeira, Tiago R. Balen |
Electromagnetic Immunity Test of Analog-to-Digital Interfaces of a Mixed-Signal Programmable SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Lorena Anghel, Anna Bernasconi 0001, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Elena I. Vatajelu |
Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Vladimir Hahanov, Wajeb Gharibi, Eugenia Litvinova, Svetlana Chumachenko |
Qubit-driven Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-7, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik |
Mixed-level identification of fault redundancy in microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Ivan D. Meza-Ibarra, Víctor H. Champac, Roberto Gómez-Fuentes, Jose R. Noriega-Luna, A. Vera-Marquina |
Identification of Logic Paths Influenced by Severe Coupling Capacitances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco |
NoCFI: A Hybrid Fault Injection Method for Networks-On-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Daniel H. P. Kraak, Cemil Cem Gürsoy, Innocent O. Agbo, Mottaqiallah Taouil, Maksim Jenihhin, Jaan Raik, Said Hamdioui |
Software-Based Mitigation for Memory Address Decoder Aging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Marwan Ammar, Ghaith Bany Hamad, Otmane Aït Mohamed |
Probabilistic High-Level Estimation of Vulnerability and Fault Mitigation of Critical Systems Using Fault-Mitigation Trees (FMTs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Estevan Lara, Guilherme Debon, Roger C. Goerl, Paulo Ricardo Cechelero Villa, Dorian Schramm, Leticia B. Poehls, Fabian Vargas 0001 |
A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of Multicore Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac |
A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek |
Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Matheus Monteiro Mariano, Érica Ferreira de Souza, André Takeshi Endo, Nandamudi L. Vijaykumar |
Analyzing graph-based algorithms employed to generate test cases from finite state machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Frank Plasencia-Balabarca, Edward Mitacc-Meza, Mario Raffo-Jara, Carlos Silva Cárdenas |
A Flexible UVM-Based Verification Framework Reusable with Avalon, AHB, AXI and Wishbone Bus Interfaces for an AES Encryption Module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Alexander Aponte-Moreno, Cesar Augusto Pedraza, Felipe Restrepo-Calle |
Reducing Overheads in Software-based Fault Tolerant Systems using Approximate Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Alberto Bosio, Paolo Bernardi, Annachiara Ruospo, Ernesto Sánchez 0001 |
A Reliability Analysis of a Deep Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Hassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Francois Lefevre |
Use of ensemble methods for indirect test of RF circuits: can it bring benefits? ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Alexander Aponte-Moreno, Felipe Restrepo-Calle, Cesar Augusto Pedraza |
MiFIT: A Fault Injection Tool to Validate the Reliability of Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Martin Krcma, Zdenek Kotásek, Jakub Lojda |
Detecting hard synapses faults in artificial neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek |
Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Rodrigo Zeli, Reinaldo Silveira, Qadeer Qureshi |
SoC Memory Test Optimization using NXP MTR Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Karel Szurman, Zdenek Kotásek |
Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Juan M. Alvarez Q., John A. Sanabria-Ordoñez, José Isidro García Melo |
Microservices-based architecture for fault diagnosis in tele-rehabilitation equipment operated via Internet. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Fabio Benevenuti, Fernanda Lima Kastensmidt |
Comparing Exhaustive and Random Fault Injection Methods for Configuration Memory on SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Douglas Rossi de Melo, César Albenes Zeferino, Luigi Dilillo, Eduardo Augusto Bezerra |
Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Salem Abdennadher, Arani Sinha, Yonghyun Kim |
Analog/Mixed Signal IP DFx from a Foundry perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Daniel Sánchez 0013, Pablo A. Ferreyra, Juan A. Fraire, Fabian Gomez, Raoul Velazco, Dardo Vinas Viscardi |
A Wireless Embedded System for Measuring the Effects of Ionizing Radiations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Abhishek Das, Nur A. Touba |
Online Correction of Hard Errors and Soft Errors via One-Step Decodable OLS Codes for Emerging Last Level Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Ghazanfar Ali, Jerrin Pathrose, Hans G. Kerkhoff |
IJTAG Compatible Delay-line based Voltage Embedded Instrument with One Clock-cycle Conversion Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler |
Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Alejandro Serrano-Cases, Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez |
Softerror mitigation for multi-core processors based on thread replication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Zhan Gao, Santosh Malagi, Erik Jan Marinissen, Joe Swenton, Jos Huisken, Kees Goossens |
Defect-Location Identification for Cell-Aware Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Walter J. Lancioni, Pablo A. Petrashin, Luis E. Toledo, Carlos Vazquez, Juan Luis Castagnola, Fortunato Carlos Dualibe |
OBT applied to a 2nd order continuous time Feedforward Sigma Delta modulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Ayman A. Atallah, Ghaith Bany Hamad, Otmane Aït Mohamed |
Reliability Analysis of TSN Networks Under SEU Induced Soft Error Using Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1756-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Reinaldo Silveira, Qadeer Qureshi, Rodrigo Zeli |
Flexible architecture of memory BISTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Fábio B. Armelin, Lirida A. B. Naviner, Roberto d'Amore |
Probability aware fault-injection approach for SER estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-3, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Rodrigo Travessini, Paulo Ricardo Cechelero Villa, Fabian Luis Vargas 0001, Eduardo Augusto Bezerra |
Processor core profiling for SEU effect analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Dionisio de Carvalho, Bruno Sanches, M. De Carvalho, Wilhelmus A. M. Van Noije |
A flexible stand-alone FPGA-based ATE for ASIC manufacturing tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Augusto Einsfeldt, Renato C. Giacomini |
Fault-tolerant architecture with full recovery under presence of SEU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | G. Cardoso Medeiros, E. Brum, Leticia Bolzani Poehls, Thiago Copetti, Tiago R. Balen |
Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Hassen Aziza, Karine Coulié, Wenceslas Rahajandraibe, Remy Vauche |
Using short-term fourier transform for particle detection and recognition in a CMOS oscillator-based chain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-5, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Andres F. Gomez, Roberto Gómez 0001, Víctor H. Champac |
A metric-guided gate-sizing methodology for aging guardband reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell |
Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-5, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Israel C. Lopes, Fabio Benevenuti, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Paolo Rech |
Reliability analysis on case-study traffic sign convolutional neural network on APSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Fabio Benevenuti, Fernanda Lima Kastensmidt |
Reliability evaluation on interfacing with AXI and AXI-S on Xilinx Zynq-7000 AP-SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Salem Abdennadher, Michael Altmann, Bin Xue |
Challenges and emerging solutions in testing HBM IO & systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Jerrin Pathrose, Ghazanfar Ali, Hans G. Kerkhoff |
IJTAG compatible analogue embedded instruments for MPSoC life-time prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Riccardo Cantoro, Andrea Firrincieli, Davide Piumatti, Marco Restifo, Ernesto Sánchez 0001, Matteo Sonza Reorda |
About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Carlos L. G. Batista, Eliane Martins, Maria de Fátima Mattiello-Francisco |
On the use of a failure emulator mechanism at nanosatellite subsystems integration tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Renato Severo, Celso Maciel da Costa, Adriane Parraga, Debora Motta, Ivan Müller, Fabian Vargas 0001 |
Design and test of the RT-NKE task scheduling algorithm for multicore architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Pablo A. Petrashin, Luis E. Toledo, Walter J. Lancioni, Carlos Vazquez, Tinus Stander, Fortunato C. Dualibe |
Influence of passive oscillator component variation on OBT sensitivity in OTAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Moritz Fieback, Mottaqiallah Taouil, Said Hamdioui, Marco Rovatti |
Ionizing radiation modeling in DRAM transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Stefano Esposito, Jacopo Sini, Massimo Violante |
Real-time validation of mixed-criticality applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Gabriel Natan P. Silva, Ricardo O. Duarte |
Towards evolvable hardware and genetic algorithm operators to fail safe systems achievement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Rafael Melo Macieira, Edna Barros |
TDevCGen: A synthesis toolset of HW/SW communication protocol monitors from high-level specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Luiz Carlos Kretly, Ricardo Maltione, Marcelo Gradella Villalva |
A novel method of impact and failure mechanism analysis of RF-based fault injection: A frequency response analyzer, FRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Felix Mühlbauer, Lukas Schröder, Mario Schölzel |
A fault tolerant dynamically scheduled processor with partial permanent fault handling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Marcello Traiola, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi, Alberto Bosio |
Testing approximate digital circuits: Challenges and opportunities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | |
19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018 ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![IEEE, 978-1-5386-1472-3 The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
1 | Lucas M. V. Pereira, Douglas R. Melo, Cesar A. Zeferino, Eduardo A. Bezerra |
Analysis of LEON3 systems integration for a Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-3, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Alexandra Kourfali, Dirk Stroobandt |
Superimposed in-circuit debugging for self-healing FPGA overlays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Luis Alberto Contreras Benites, Fernanda Lima Kastensmidt |
Automated design flow for applying Triple Modular Redundancy (TMR) in complex digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Alexander Aponte-Moreno, Alejandro Moncada, Felipe Restrepo-Calle, Cesar Augusto Pedraza |
A review of approximate computing techniques towards fault mitigation in HW/SW systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Eduardo Garcia-Espinosa, Omar Longoria-Gandara, Enrique Gonzalez-Garcia, Arturo Veloz-Guerrero |
Post-silicon validation based on synthetic test patterns for early detection of timing anomalies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-5, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Ingrid F. V. Oliveira, Rafael B. Schvittz, Paulo F. Butzen |
Fault masking ratio analysis of majority voters topologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Fábio B. Armelin, Lírida A. B. Naviner, Roberto d'Amore |
Using FPGA self-produced transients to emulate SETs for SER estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-3, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio |
Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Marcos Silveira Santos, Roberto d'Amore |
Error detection method for the ARINC429 communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Paulo Ricardo Cechelero Villa, Rodrigo Travessini, Fabian Luis Vargas 0001, Eduardo Augusto Bezerra |
Processor checkpoint recovery for transient faults in critical applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Wendong Wang, Adit D. Singh, Ujjwal Guin, Abhijit Chatterjee |
Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Frank Plasencia-Balabarca, Edward Mitacc-Meza, Mario Raffo-Jara, Carlos Silva Cárdenas |
Alternative functional verification methodology for low and medium level designs (Applied to an AES encryption module). ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Stefano Esposito, Serhiy Avramenko, Massimo Violante |
RTOS for mixed criticality applications deployed on NoC-based COTS MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Joao de Moraes, Taisy Silva Weber, Guilherme Muller, Tiago Dall'Agnol, Rafael Macedo, Elaine P. L. Scartezzini, Roque Eduardo Dapper, Sérgio Luis Cechin, Joao Netto |
Architecture of an industrial analog input designed to meet safety requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Paulo Vinicius Cardoso, Patrícia Pitthan Barcelos |
Validation of a dynamic checkpoint mechanism for Apache Hadoop with failure scenarios. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Iuri Albandes Cunha Gomes, Alejandro Serrano-Cases, Antonio J. Sanchez-Clemente, Mayler G. A. Martins, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Fernanda Lima Kastensmidt |
Improving approximate-TMR using multi-objective optimization genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | George Redivo Pinto, Guilherme Cardoso Medeiros, Fabian Vargas 0001, Leticia Bolzani Poehls |
A hardware-based approach for SEU monitoring in SRAMs with weak resistive defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Andrea Marcelli, Ernesto Sánchez 0001, Giovanni Squillero, Muhammad Usman Jamal, Afnan Imtiaz, Simone Machetti, Filippo Mangani, Paolo Monti 0003, Davide Pola, Alessandro Salvato, Michele Simili |
Defeating hardware Trojan in microprocessor cores through software obfuscation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Thales E. Becker, Fábio Fedrizzi Vidor, Gilson I. Wirth, Thorsten Meyers, Julia Reker, Ulrich Hilleringmann |
Time domain electrical characterization in zinc oxide nanoparticle thin-film transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Edgar-Andrei Vega-Ochoa, Nagib Hakim |
Direct optimization of a PCI express link equalization in industrial post-silicon validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Juliano Oliveira, Marcilei Aparecida Guazzelli, Marco Antonio Assis, Renato C. Giacomini |
Single event effect: Simulations and analysis on 3N163 PMOS transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018, pp. 1-3, 2018, IEEE, 978-1-5386-1472-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Israel C. Lopes, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin |
SEU susceptibility analysis of a feedforward neural network implemented in a SRAM-based FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | André Lucas Chinazzo, Paulo César Comassetto de Aguirre, Tiago R. Balen |
Low cost automatic test vector generation for structural analog testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-4, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Felix Mühlbauer, Lukas Schröder, Patryk Skoncej, Mario Schölzel |
Handling manufacturing and aging faults with software-based techniques in tiny embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Toral Shah, Anzhela Yu. Matrosova, Binod Kumar 0001, Masahiro Fujita, Virendra Singh |
Testing multiple stuck-at faults of ROBDD based combinational circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Jan Burchard, Felix Neubauer, Pascal Raiola, Dominik Erb, Bernd Becker 0001 |
Evaluating the effectiveness of D-chains in SAT-based ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja |
Identifying high variability speed-limiting paths under aging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Paolo Bernardi, Riccardo Cantoro, L. Gianotto, Marco Restifo, Ernesto Sánchez 0001, Federico Venini, Davide Appello |
A DMA and CACHE-based stress schema for burn-in of automotive microcontroller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Satoshi Ohtake, Daichi Shimazu |
An approach to LFSR-based X-masking for built-in self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-4, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt |
Evaluating the behavior of successive approximation algorithms under soft errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Nandeesha Veeranna, Benjamin Carrión Schäfer |
Efficient behavioral intellectual properties source code obfuscation for high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Vinicius Martins, Jiang Chau Wang, Jerson Paulo Guex |
Mixed signal verification to avoid integration mismatch in complex SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez |
An effective strategy for selective hardening of software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Ronaldo Milfont, Paulo Cortez 0002, Alan Cadore Pinheiro, Joao Marcelo Ferreira, Jarbas Silveira, Rafael Mota, César A. M. Marcon |
Analysis of routing algorithms generation for irregular NoC topologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-5, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Jose Isaza-Gonzalez, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Hipólito Guzmán-Miranda, Miguel A. Aguirre |
Contrast of a HDL model and COTS version of a microprocessor for soft-error testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Binod Kumar 0001, Ankit Jindal, Masahiro Fujita, Virendra Singh |
Post-silicon observability enhancement with topology based trace signal selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|