Search results for "MTV"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Maneesh Kumar Pandey, Shwetank Shekhar, Nitin Saxena 0003, Gaurav Kumar Agarwal, Amersh Kumar	An Approach for In-House USB2.0 Electrical Compliance Testing on Nanoscale SoC.	MTV	2013	DBLP DOI BibTeX RDF
1	Emad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia	Communication Alternatives Exploration in Model-Driven Design of Networked Embedded Systems.	MTV	2013	DBLP DOI BibTeX RDF
1	Christian Miller, Christoph Scholl 0001, Bernd Becker 0001	Proving QBF-hardness in Bounded Model Checking for Incomplete Designs.	MTV	2013	DBLP DOI BibTeX RDF
1	Emad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia, Francesco Stefanni	Automatic Network Protocol Synthesis from UML Sequence Diagrams.	MTV	2013	DBLP DOI BibTeX RDF
1	Narendra Kamat	IP Testing for Heterogeneous SOCs.	MTV	2013	DBLP DOI BibTeX RDF
1	Mohamed A. Salem, Kerstin I. Eder	Modified Condition Decision Coverage: A Hardware Verification Perspective.	MTV	2013	DBLP DOI BibTeX RDF
1	Kanad Basu, Prabhat Mishra 0001, Priyadarsan Patra, Amir Nahir, Allon Adir	Dynamic Selection of Trace Signals for Post-Silicon Debug.	MTV	2013	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Riccardo Cantoro, Lyl M. Ciganda Brasca, Boyang Du, Ernesto Sánchez 0001, Matteo Sonza Reorda, Michelangelo Grosso, Oscar Ballan	On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors.	MTV	2013	DBLP DOI BibTeX RDF
1	Maneesh Kumar Pandey, Atul Gupta, Shwetank Shekhar	USB Validation Challenges on C45SOI & C28NM Technology Products.	MTV	2013	DBLP DOI BibTeX RDF
1	Jack L. Mason, Gregory E. Simco	Target Environment Simulation and its Impact on Architecture Validation: A Case Study of Thread-Level Speculative Execution.	MTV	2013	DBLP DOI BibTeX RDF
1	Vinayak Kamath, Farhan Rahman, Li-C. Wang	Analyzing Efficacy of Constrained Test Program Generators - A Case Study.	MTV	2013	DBLP DOI BibTeX RDF
1	Matthew L. King	Practical Security Validation.	MTV	2013	DBLP DOI BibTeX RDF
1	Brian Kahne, Jim Holt	Functional Validation of a New Network Switch Architecture Using Rapid Prototyping Techniques.	MTV	2013	DBLP DOI BibTeX RDF
1	Daniel Hansson, Heli Uronen-Hansson	Measuring the Gain of Automatic Debug.	MTV	2013	DBLP DOI BibTeX RDF
1	Rama Venkatasubramanian, Oluleye Olorode, Abhishek Arun	State Retention Validation of C66X DSP Core.	MTV	2013	DBLP DOI BibTeX RDF
1	David Brier, Rama Venkatasubramanian, Sowmya Rangarajan, Abhishek Arun, David Thompson, Neelima Muralidharan	Verification Methodology of Heterogeneous DSP+ARM Multicore Processors for Multi-core System on Chip.	MTV	2013	DBLP DOI BibTeX RDF
1	Hoyoung Kim, Seonghun Jeong, Sunmin Kwon, Soojung Ryu	Hierarchical Verification Framework for Samsung Reconfigurable Processor Video System.	MTV	2013	DBLP DOI BibTeX RDF
1	Abhishek Basak, Sanchita Mal-Sarkar, Swarup Bhunia	Secure and Trusted SoC: Challenges and Emerging Solutions.	MTV	2013	DBLP DOI BibTeX RDF
1	Ujjwal Guin, Domenic Forte, Mohammad Tehranipoor	Anti-counterfeit Techniques: From Design to Resign.	MTV	2013	DBLP DOI BibTeX RDF
1		14th International Workshop on Microprocessor Test and Verification, MTV 2013, Austin, TX, USA, December 11-13, 2013	MTV	2013	DBLP BibTeX RDF
1	Tariq Bashir Ahmad, Maciej J. Ciesielski	An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads.	MTV	2013	DBLP DOI BibTeX RDF
1	Mona Safar, Magdy A. El-Moursy, Ashraf Salem	Ultra-Fast DMAC TLM Model for High Speed Virtual Platform Simulation.	MTV	2013	DBLP DOI BibTeX RDF
1	Lung-Jen Lee, Wang-Dauh Tseng, Wei-Shun Chen	Two-Way Multicasting for Test Data Compression.	MTV	2012	DBLP DOI BibTeX RDF
1	Georges Morbé, Christoph Scholl 0001	Guaranteeing Termination of Fully Symbolic Timed Forward Model Checking.	MTV	2012	DBLP DOI BibTeX RDF
1	Biruk Mammo, Jim Larimer, Matthew Morgan, Dave Fan, Eric Hennenhoefer, Valeria Bertacco	Architectural Trace-Based Functional Coverage for Multiprocessor Verification.	MTV	2012	DBLP DOI BibTeX RDF
1	Lung-Jen Lee, Chia-Cheng He, Wang-Dauh Tseng	Deterministic ATPG for Low Capture Power Testing.	MTV	2012	DBLP DOI BibTeX RDF
1	Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli, Sara Vinco	Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis.	MTV	2012	DBLP DOI BibTeX RDF
1	Lyl M. Ciganda, Marco Gaudesi, Evelyne Lutton, Ernesto Sánchez 0001, Giovanni Squillero, Alberto Paolo Tonda	Automatic Generation of On-Line Test Programs through a Cooperation Scheme.	MTV	2012	DBLP DOI BibTeX RDF
1	Johnny J. W. Kuan, Tor M. Aamodt	Progressive-BackSpace: Efficient Predecessor Computation for Post-Silicon Debug.	MTV	2012	DBLP DOI BibTeX RDF
1	Heejun Shim, Minwook Ahn, JinSae Jung, Yenjo Han, Soojung Ryu	Verification of CGRA Executable Code and Debugging of Memory Dependence Violation.	MTV	2012	DBLP DOI BibTeX RDF
1	Lukás Charvát, Ales Smrcka, Tomás Vojnar	Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description.	MTV	2012	DBLP DOI BibTeX RDF
1	Youngchul Cho, Seonghun Jeong, J. Jeong, Heejun Shim, Yenjo Han, Soojung Ryu, Jay Kim	Case Study: Verification Framework of Samsung Reconfigurable Processor.	MTV	2012	DBLP DOI BibTeX RDF
1	Markus Mattwandel	New Process to Simultaneously Measure, Quantify, and Model Energy Efficient Performance.	MTV	2012	DBLP DOI BibTeX RDF
1	Anton Tsepurov, Valentin Tihhomirov, Maksim Jenihhin, Jaan Raik, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke	Localization of Bugs in Processor Designs Using zamiaCAD Framework.	MTV	2012	DBLP DOI BibTeX RDF
1	Nicola Bombieri, Emad Samuel Malki Ebeid, Franco Fummi, Michele Lora	On the Reuse of RTL IPs for SysML Model Generation.	MTV	2012	DBLP DOI BibTeX RDF
1	Lung-Jen Lee, Wang-Dauh Tseng, Wen-Ting Yang	Dual-LFSR Reseeding for Low Power Testing.	MTV	2012	DBLP DOI BibTeX RDF
1		13th International Workshop on Microprocessor Test and Verification, MTV 2012, Austin, TX, USA, December 10-13, 2012	MTV	2012	DBLP BibTeX RDF
1	Christoph Wolf, Steffen Zeidler 0001, Milos Krstic, Rolf Kraemer	Overview on ATE Test and Debugging Methods for Asynchronous Circuits.	MTV	2011	DBLP DOI BibTeX RDF
1	Magdy S. Abadir, Jay Bhadra, Li-C. Wang (eds.)	12th International Workshop on Microprocessor Test and Verification, MTV 2011, Austin, TX, USA, December 5-7, 2011	MTV	2011	DBLP BibTeX RDF
1	Daecheol You, Young-Si Hwang, Youngho Ahn, Ki-Seok Chung	A Test Method for Power Management of SoC-based Microprocessors.	MTV	2011	DBLP DOI BibTeX RDF
1	Robert de B. Johnston, Ouiza Dahmoune	Overview of Applying Reachability Analysis to Verifying a Physical Microprocessor.	MTV	2011	DBLP DOI BibTeX RDF
1	Alper Sen 0001, Etem Deniz	Verification Tests for MCAPI.	MTV	2011	DBLP DOI BibTeX RDF
1	Devraj Kallappa Bakchowde, Nanda Kishore AS	An Efficient Overlapping Event Generation Method for Symmetric System Testing.	MTV	2011	DBLP DOI BibTeX RDF
1	Ernesto Sánchez 0001, Giovanni Squillero, Alberto Paolo Tonda	Automatic Generation of Software-based Functional Failing Test for Speed Debug and On-silicon Timing Verification.	MTV	2011	DBLP DOI BibTeX RDF
1	Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli	Reusing of Properties after Discretization of Hybrid Automata.	MTV	2011	DBLP DOI BibTeX RDF
1	Mona Safar, Magdy A. El-Moursy, Ashraf Salem, Mohamed Abdelsalam	TLM Based Approach for Architecture Exploration of Multicore Systems-on-Chip.	MTV	2011	DBLP DOI BibTeX RDF
1	Christian Miller, Karina Gitina, Bernd Becker 0001	Bounded Model Checking of Incomplete Real-time Systems Using Quantified SMT Formulas.	MTV	2011	DBLP DOI BibTeX RDF
1	Sergey Sofer, Asher Berkovitz, Valery Neiman	High Coverage Power Integrity Verification in PSO Domains Employing Distributed PSO Switches.	MTV	2011	DBLP DOI BibTeX RDF
1	Kesava R. Talupuru, Sanjai Athi	Achieving Glitch-Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking.	MTV	2011	DBLP DOI BibTeX RDF
1	Oswaldo Olivo, Sandip Ray, Jayanta Bhadra, Vivekananda M. Vedula	A Unified Formal Framework for Analyzing Functional and Speed-path Properties.	MTV	2011	DBLP DOI BibTeX RDF
1	Ouiza Dahmoune, Robert de B. Johnston	Model Checker to FPGA Prototype Commmunication Bottleneck Issue.	MTV	2011	DBLP DOI BibTeX RDF
1	Ouiza Dahmoune, Robert de B. Johnston	An Embedded Reachability Analyzer and Invariant Checker (ERAIC).	MTV	2010	DBLP DOI BibTeX RDF
1	Christian Miller, Karina Gitina, Christoph Scholl 0001, Bernd Becker 0001	Bounded Model Checking of Incomplete Networks of Timed Automata.	MTV	2010	DBLP DOI BibTeX RDF
1	Brian Keng, Andreas G. Veneris, Sean Safarpour	An Automated Framework for Correction and Debug of PSL Assertions.	MTV	2010	DBLP DOI BibTeX RDF
1	Oscar Ballan, Paolo Bernardi, Giovanni Fontana, Michelangelo Grosso, Ernesto Sánchez 0001	A Fault Grading Methodology for Software-Based Self-Test Programs in Systems-on-Chip.	MTV	2010	DBLP DOI BibTeX RDF
1	Devraj Kallappa Bakchowde, Nanda Kishore A. S.	An Efficient Event Generation Method for Testing a SOC with Multiple Processing Elements and Associated Peripherals.	MTV	2010	DBLP DOI BibTeX RDF
1	Mauricio de Carvalho, Paolo Bernardi, Ernesto Sánchez 0001, Matteo Sonza Reorda	An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization.	MTV	2010	DBLP DOI BibTeX RDF
1	Padmaraj Singh, David L. Landis	Test Generation for CMP Designs.	MTV	2010	DBLP DOI BibTeX RDF
1	Nathan Buchanan, Hiren D. Patel	Towards a Multi-MoC Hardware/Software Co-design Framework Using Abstract State Machines.	MTV	2010	DBLP DOI BibTeX RDF
1	Wei Sheng, Yanyan Gao 0001, Li Xi, Xuehai Zhou	Schedulability Analysis for MultiCore Global Scheduling with Model Checking.	MTV	2010	DBLP DOI BibTeX RDF
1	Hoang Minh Le 0001, Daniel Große, Rolf Drechsler	Automatic Fault Localization for SystemC TLM Designs.	MTV	2010	DBLP DOI BibTeX RDF
1	Alper Sen 0001, Baris Aksanli, Murat Bozkurt	Using Graphics Processing Units for Logic Simulation of Electronic Designs.	MTV	2010	DBLP DOI BibTeX RDF
1	Magdy S. Abadir, Jay Bhadra, Li-C. Wang (eds.)	11th International Workshop on Microprocessor Test and Verification, MTV 2010, Austin, TX, USA, December 13-15, 2010	MTV	2010	DBLP BibTeX RDF
1	Görschwin Fey, André Sülflow, Rolf Drechsler	Towards Unifying Localization and Explanation for Automated Debugging.	MTV	2010	DBLP DOI BibTeX RDF
1	Padmaraj Singh, David L. Landis, Vijaykrishnan Narayanan	Test Generation for Precise Interrupts on Out-of-Order Microprocessors.	MTV	2009	DBLP DOI BibTeX RDF
1	Franco Fummi, Davide Quaglia, Sara Vinco, Giovanni Perbellini, Saul Saggin	Mixing Simulated and Actual Hardware Devices to Validate Device Drivers in a Complex Embedded Platform.	MTV	2009	DBLP DOI BibTeX RDF
1	Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, Sudeep Pasricha	A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations.	MTV	2009	DBLP DOI BibTeX RDF
1	Robert C. Page, Sakar Jain	Verification of the CoreNet Fabric with SystemVerilog.	MTV	2009	DBLP DOI BibTeX RDF
1	Jim Holt, Jaideep Dastidar, David Lindberg, John Pape, Peng Yang	System-level Performance Verification of Multicore Systems-on-Chip.	MTV	2009	DBLP DOI BibTeX RDF
1	Daniel Große, Hoang Minh Le 0001, Rolf Drechsler	Induction-Based Formal Verification of SystemC TLM Designs.	MTV	2009	DBLP DOI BibTeX RDF
1	Chen-Yuan Kao, Chien-Hui Liao, Charles H.-P. Wen	An ILP-Based Diagnosis Framework for Multiple Open-Segment Defects.	MTV	2009	DBLP DOI BibTeX RDF
1	József Sziray	Switch-Level Test Calculation for CMOS Circuits.	MTV	2009	DBLP DOI BibTeX RDF
1		10th International Workshop on Microprocessor Test and Verification, MTV 2009, Austin, Texas, USA, 7-9 December 2009	MTV	2009	DBLP BibTeX RDF
1	James A. Lear	Digital and Mixed-Signal Verification Differences.	MTV	2009	DBLP DOI BibTeX RDF
1	Jing Zeng, Jing Wang, Michael Mateja	A Path-Oriented Timing-Aware Diagnosis Methodology of At-Speed Transition Tests.	MTV	2009	DBLP DOI BibTeX RDF
1	Alper Sen 0001	Mutation Operators for Concurrent SystemC Designs.	MTV	2009	DBLP DOI BibTeX RDF
1	Richard Bartolotti, Tom Burd, Brian McMinn, Arun Chandra	Constraint Management and Checking in Template-Based Circuit Designs.	MTV	2009	DBLP DOI BibTeX RDF
1	Mona Safar, M. Watheq El-Kharashi, Mohamed Shalan, Ashraf Salem	A Reconfigurable Five-Stage Pipelined SAT Solver.	MTV	2009	DBLP DOI BibTeX RDF
1	Vyas Venkataraman, Di Wang, Wei Qin, Mrinal Bose, Jayanta Bhadra	Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling.	MTV	2009	DBLP DOI BibTeX RDF
1	Shadi Moazzeni, Saadat Poormozaffari, Amin Emami	An Optimized Simulation-Based Fault Injection and Test Vector Generation Using VHDL to Calculate Fault Coverage.	MTV	2009	DBLP DOI BibTeX RDF
1	Jack L. Mason	The importance of full target environment simulation tests for architecture validation.	MTV	2009	DBLP DOI BibTeX RDF
1	Zdenek Prikryl, Karel Masarík, Tomás Hruska, Adam Husár	Fast Cycle-Accurate Interpreted Simulation.	MTV	2009	DBLP DOI BibTeX RDF
1	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	On the Mutation Analysis of SystemC TLM-2.0 Standard.	MTV	2009	DBLP DOI BibTeX RDF
1	Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla	Applying Verification Collaterals for Accurate Power Estimation.	MTV	2008	DBLP DOI BibTeX RDF
1	Ulrich Kühne, Daniel Große, Rolf Drechsler	Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow.	MTV	2008	DBLP DOI BibTeX RDF
1	Alexander Weiss, Christian Hochberger	A New Methodology for the Test of SoCs and for Analyzing Elusive Failures.	MTV	2008	DBLP DOI BibTeX RDF
1	Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton	BackSpace: Moving Towards Reality.	MTV	2008	DBLP DOI BibTeX RDF
1	William W. Collier	Testing Memory Models.	MTV	2008	DBLP DOI BibTeX RDF
1	Thinh Ngo	Enhancing Verification Efficiency via Dynamically Focused, Selective and Intrusive Transactions.	MTV	2008	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda	A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores.	MTV	2008	DBLP DOI BibTeX RDF
1	Bhanu Kapoor, J. Marc Edwards, Shankar Hemmady, Shireesh Verma, Kaushik Roy 0001	Tutorial: SoC Power Management Verification and Testing Issues.	MTV	2008	DBLP DOI BibTeX RDF
1	Sandip Ray	Abstraction as a Practical Debugging Tool.	MTV	2008	DBLP DOI BibTeX RDF
1		Ninth International Workshop on Microprocessor Test and Verification, MTV 2008, Austin, Texas, USA, 8-10 December 2008	MTV	2008	DBLP BibTeX RDF
1	Joseph W. Lyles Jr.	Vertical Reuse Strategy for Testbench Components Supporting Memory Consistency Checking of an SMP-Capable AMD64 Processor.	MTV	2008	DBLP DOI BibTeX RDF
1	Y. B. Liao, P. Li, A. W. Ruan, Y. W. Wang, W. C. Li, W. Li	Hierarchy Communication Channel in Transaction-Level Hardware/Software Co-emulation System.	MTV	2008	DBLP DOI BibTeX RDF
1	Nathan Sheeley, Nicolas Pena, Irfan Waheed, Mark H. Nodine	Enhancing Sequential LEC Using a Cumulative Verification Methodology.	MTV	2008	DBLP DOI BibTeX RDF
1	Mark H. Nodine	Preparing Rearchitected Designs for Sequential Equivalence Checking.	MTV	2008	DBLP DOI BibTeX RDF
1	Ryan Ritesh M. Pinto	Power Management Verification - An Evolving Discipline.	MTV	2008	DBLP DOI BibTeX RDF
1	Kana Murale, Scot Hildebrandt, Per Bojsen, Alfonso Urzua	AMD64 Processor Front-End Verification (at Unit-Level Testbench) with Instruction Set Simulator.	MTV	2008	DBLP DOI BibTeX RDF
1	Alan Hunter 0002, Andrew Piziali, Avi Ziv, Kelly Larson, Shankar Hemmady	Ensuring Functional Closure of a Multi-core SoC through Verification Planning, Implementation and Execution.	MTV	2008	DBLP DOI BibTeX RDF

Publications at "MTV"( http://dblp.L3S.de/Venues/MTV )