Search results for "NORCHIP"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis	KL-cut based digital circuit remapping.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Mark Ruvald Pedersen, Jan Madsen	Optimal register allocation by augmented left-edge algorithm on arbitrary control-flow structures.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Imad ud Din, Johan Wernehag, Stefan Back Andersson, Sven Mattisson	Wideband Reconfigurable Capacitive shunt-feedback LNA in 65nm CMOS.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Peteris Misans, Uldis Derums, Vents Kanders	FPGA implementation of elementary generalized unitary rotation with CORDIC based architecture.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Joakim Alvbrant, J. Jacob Wikner	Study and simulation of an example redundant FIR filter.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Tuan Vu Cao, Snorre Aunet, Trond Ytterdal	A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Nowshad Painda Mand, Francesco Robino, Johnny Öberg	Artificial neural network emulation on NOC based multi-core FPGA platform.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Kristian Gjertsen Kjelgård, Tor Sverre Lande	A 26 GHz UWB CMOS IR-UWB transmitter with on-chip balun.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	S. Balasubramanian, Waleed Khalil	Architectural trends in GHz speed DACs.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Sima Payami, Amin Ojani	An operational amplifier for high performance pipelined ADCs in 65nm CMOS.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Rasmus Bo Sørensen, Martin Schoeberl, Jens Sparsø	A light-weight statically scheduled network-on-chip.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Fatemeh Khalili, Hamid R. Zarandi	A fault-aware low-energy spare core allocation in networks-on-chip.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Vahid Saljooghi, Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors	Configurable RTL model for level-1 caches.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Wolfgang Gut, Gerald Hilber, Dominik Gruber, Manuel Kaufmann, Andreas Rauchenecker, Timm Ostermann	Low power Real Time Clock with high accuracy over large supply voltage range.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Deena M. Zamzam, Mohamed A. Abd El-Ghany, Klaus Hofmann	Performability of error control schemes for NOC interconnects.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Ping Lu 0002, Pietro Andreani, Antonio Liscidini	A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Stefan Hauser, Nico Moser, Ben H. H. Juurlink	SynZEN: A hybrid TTA/VLIW architecture with a distributed register file.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Ivan H. H. Jørgensen	Challenges in IC design for hearing aids.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Jia Sun, Timo Rahkonen, Marko Neitola	Behavioral modeling of nonlinear settling for multiple cascaded SC stages.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Francesca Cucchi, Stefano Di Pascoli, Giuseppe Iannaccone	Variability-aware design of 55 nA current reference with 1.4% standard deviation and 290 nW power consumption.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Mitesh Yogesh, Puneet Sareen, Markus Dietl, Ketan Dewan	A 2.5 GHz self-compensated, bandwidth tracking PLL with 0.8 ps jitter.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Lauri Matilainen, Sakari Lahti, Otto Esko, Erno Salminen, Timo D. Hämäläinen	Integration of TTA processor tools to Kactus2 IP-XACT design flow.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Ahmed Shalaby 0001, Mohamed El-Sayed Ragab, Victor Goulart	Intermediate nodes selection schemes for Network Coding in Network-on-Chips.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Oliver Schrape, Frank Vater	Embedded low power clock generator for sensor nodes.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Iracu O. Santos, Alba Sandyra Bezerra Lopes, Bruno M. Carvalho 0001, Edgard de Faria Corrêa, Márcio Eduardo Kreutz	H.264/AVC motion estimation on FPGAs and GPUs: A comparative study.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Raimund Ubar, Viljar Indus, Oliver Kalmend, Teet Evartson, Elmet Orasson	Functional Built-In Self-Test for processor cores in SoC.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Quoc-Tai Duong, Jerzy J. Dabrowski	Wideband RF detector design for high performance on-chip test.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Chenxin Zhang, Hemanth Prabhu, Liang Liu 0002, Ove Edfors, Viktor Öwall	Energy efficient MIMO channel pre-processor using a low complexity on-line update scheme.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas	Lithography analysis of via-configurable transistor-array fabrics.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Jing Zhou, Zengrong Liu, Lei Chen 0010, Shuo Wang, Zhiping Wen 0001, Xun Chen, Chang Qi	An accurate fault location method based on configuration bitstream analysis.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Jonas Stenbaek Hegner, Joakim Sindholt, Alberto Nannarelli	Design of power efficient FPGA based hardware accelerators for financial applications.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Nadeem Afzal, J. Jacob Wikner	Power efficient arrangement of oversampling sigma-delta DAC.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Ali Fazli Yeknami, Atila Alvandpour	A 2.1 µW 76 dB SNDR DT-ΔΣ modulator for medical implant devices.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Elias Bakken, Tor Sverre Lande, Sverre Holm	Effect of process variations in CMOS chips for radar beamforming.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Iason Filippopoulos, Francky Catthoor, Per Gunnar Kjeldsberg, Elena Hammari, Jos Huisken	Memory-aware system scenario approach energy impact.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Behrad Niazmand, Midia Reshadi, Akram Reza	PathAware: A contention-aware selection function for application-specific Network-On-Chips.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Vladimir M. Milovanovic, Horst Zimmermann	Analyses of single-stage complementary self-biased CMOS differential amplifiers.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Mehran Baboli, Olga Boric-Lubecke, Victor Lubecke	Heart and respiratory detection and simulations for tracking humans based on respiration by using pulse-based radar.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Haoyuan Ying, Kris Heid, Thomas Hollstein, Klaus Hofmann	A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Felice Francesco Tafuri, Cataldo Guaragnella, Marco Fiore, Torben Larsen	Linearization of RF power amplifiers using an enhanced memory polynomial predistorter.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Shailesh Singh Chouhan, Kari Halonen	A Novel on-chip ultra-low power temperature sensing scheme.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Prakash Harikumar, Muhammad Irfan Kazim, J. Jacob Wikner	An analog receiver front-end for capacitive body-coupled communication.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Mateo Valero	Novel SRAM bias control circuits for a low power L1 data cache.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Wei Wei, Jan H. Mikkelsen, Ole Kiel Jensen	Deembedding static nonlinearities of power amplifiers using least square error algorithm.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Saif Uddin, Johnny Öberg	Testing of an off-chip NoC protocol using a BIST/Synthesizable Testbench approach.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Shanthi Sudalaiyandi, Tor Sverre Lande	A continuous-time IR-UWB RAKE receiver for coherent symbol detection.	NORCHIP	2012	DBLP DOI BibTeX RDF
1		NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012	NORCHIP	2012	DBLP BibTeX RDF
1	Dag T. Wisland	Nanoscale CMOS impulse radar - from research to product.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Andrea Simonetti	A measurement technique for the vibrating wire sensors.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Daniel Svard, Christer Jansson, Atila Alvandpour	A readout circuit for an uncooled IR camera with mismatch and self-heating compensation.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Maris Terauds	Implementation of FPGA based DSP module for CW Doppler radar: Preliminary results.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Eirik Steen-Hansen, Trond Ytterdal	Modeling and design of a dual-residue pipelined ADC in 130nm CMOS.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Hanspeter Schmid	Electrical and human feedback.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Jan Madsen	Biochips: The integrated circuit of biology.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Jia Mao, Zhuo Zou, David Sarmiento M., Fredrik Jonsson, Li-Rong Zheng 0001	A power scalable and high pulse swing UWB transmitter for wirelessly-powered RFID applications.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Srinivasa Reddy Kuppireddi, Sayanu Pamidighantam, V. Janardhana, Oddvar Søråsen, J. S. Roy, R. G. Kulkarn	Evaluation of SU8 photo polymer for microwave packaging applications.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Dipak S. Marathe	A survey on mixed operating mode/self synchronization.	NORCHIP	2012	DBLP DOI BibTeX RDF
1	Mohammed Hassan, Horst Zimmermann	An 85dB dynamic range transimpedance amplifier in 40nm CMOS technology.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Nicolas Borup, Jonas Dindorp, Alberto Nannarelli	FPGA implementation of decimal processors for hardware acceleration.	NORCHIP	2011	DBLP DOI BibTeX RDF
1		2011 NORCHIP, Lund, Sweden, November 14-15, 2011	NORCHIP	2011	DBLP BibTeX RDF
1	Deena M. Zamzam, Mohamed A. Abd El-Ghany, Klaus Hofmann, Mohammad Ismail 0001	Highly reliable and power efficient NOC interconnects.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Ronald Spilka, Dominik Gruber, Timm Ostermann	Use of a calibrated voltage reference to enhance the performance of switched capacitor sigma-delta ADCs over process corner.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Ying Wu 0003, Ping Lu 0002, Pietro Andreani	A digital PLL with a multi-delay coarse-fine TDC.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Kin Keung Lee, Håkon A. Hjortland, Tor Sverre Lande	IR-UWB technology on next generation RFID systems.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Brad R. Jackson, Carlos E. Saavedra	A divide-by-three regenerative frequency divider using a subharmonic mixer.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Xiaodong Liu, Vijay Viswam, Stefan Back Andersson, Johan Wernehag, Imad ud Din, Pietro Andreani	Highly linear direct conversion receiver using customized on-chip balun.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Petter Kallstrom, Oscar Gustafsson	Magnitude scaling for increased SFDR in DDFS.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Shahzad Ahmad Butt, Luciano Lavagno	Model-based rapid prototyping of multirate digital signal processing algorithms.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Andreas Thor Winther, Wei Liu 0016, Alberto Nannarelli, Sarma B. K. Vrudhula	Temperature dependent wire delay estimation in floorplanning.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Mojtaba Valinataj, Pasi Liljeberg, Juha Plosila	A fault-tolerant and hierarchical routing algorithm for NoC architectures.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Yelin Wang, Daniel Sira, Troels Studsgaard Nielsen, Ole K. Jensen, Torben Larsen	On wafer X-parameter based modeling of a switching cascode power amplifier.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Syed Iftekhar Ali, Md. Shafiqul Islam	A novel low-energy match line sensing scheme for ternary content addressable memory using charge sharing.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Johannes Uhlig, René Schüffny	An empirical study of the stability of 4th-order Incremental-ΣΔ-ADCs.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Yevgen Borokhovych, Christoph Scheytt	10 GS/s 8-bit bipolar THA in SiGe technology.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Johanna Anteroinen, Wonjae Kim, Kari Stadius, Juha Riikonen, Harri Lipsanen, Jussi Ryynänen	Electrical properties of CVD-graphene FETs.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Tero Koivisto, Esa Tiiliharju, Peter Virta	Injection-locked superharmonic self-oscillating mixer.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Muhammad Shakir, Mohammed Abdulaziz, Ping Lu 0002, Pietro Andreani	A mixed mode design flow for multi GHz ADPLLs.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Reza Meraji, John B. Anderson, Henrik Sjöland, Viktor Öwall	Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Anders Nejdel, Markus Törmänen, Henrik Sjöland	A linearized 1.6-5 GHz low noise amplifier using positive feedback in 65 nm CMOS.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Denys I. Martynenko, Gunter Fischer, Oleksiy Klymenko	Low power programmable frequency divider for IEEE 802.15.4a standard.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Lin Zhu, Martin Liliebladh	Comparison and IIP2 analysis of two wideband Balun-LNAs designed in 65nm CMOS.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Vivek Elangovan, Markus Dietl, Puneet Sareen	Very high bandwidth semi-digital PLL with large operating frequency range.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Felice Francesco Tafuri, Daniel Sira, Troels Studsgaard Nielsen, Ole Kiel Jensen, Torben Larsen	Wideband limit study of a GaN power amplifier using two-tone measurements.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Tobias Tired, Pietro Andreani	Single-ended low noise multiband LNA with programmable integrated matching and high isolation switches.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Khalid Latif 0002, Amir-Mohammad Rahmani, Tiberiu Seceleanu, Hannu Tenhunen	A low-cost processing element recovery mechanism for fault tolerant Networks-on-Chip.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Daniel Sira, Torben Larsen	Modeling of cascode modulated power amplifiers.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Christian Schuss, Timo Rahkonen	Adaptive photovoltaic cell simulation with maximum power point tracking simulation for accurate energy predictions.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Oskar Andersson, S. M. Yasser Sherazi, Joachim Neves Rodrigues	Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Amir H. Miremadi, Ahmad Ayatollahi, Adib Abrishamifar	A low voltage low power CMOS analog multiplier.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Michael Opoku Agyeman, Ali Ahmadinia	An adaptive router architecture for heterogeneous 3D Networks-on-Chip.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Seyyed Hassan Khalilinezhad, Akram Reza, Midia Reshadi	Yield modeling and yield-aware mapping for application specific networks-on-chip.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Johan Löfgren, Peter Nilsson 0001	On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Syed Asad Alam, Oscar Gustafsson	Implementation of narrow-band frequency-response masking for efficient narrow transition band FIR filters on FPGAs.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Muhammad Abbas, Oscar Gustafsson	Computational and implementation complexity of polynomial evaluation schemes.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Jiajia Jiao, Yuzhuo Fu, Jiang Jiang	Architecture-level analysis and evaluation of transient errors on NoC.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Andrea Bevilacqua, Pietro Andreani	A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Olli Kursu, Timo Rahkonen	Charge scaling 10-bit successive approximation A/D converter with reduced input capacitance.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Matthew J. Turnquist, Erkka Laulainen, Jani Mäkipää, Lauri Koskinen	Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Ying Wu 0003, Xiaodong Liu, Dawei Ye, Vijay Viswam, Lin Zhu, Ping Lu 0002, Dejan Radjen, Henrik Sjöland	A 0.13µm CMOS ΔΣ PLL FM transmitter.	NORCHIP	2011	DBLP DOI BibTeX RDF
1	Luca Fanori, Pietro Andreani	Dynamic bias schemes for class-C VCOs.	NORCHIP	2011	DBLP DOI BibTeX RDF

Publications at "NORCHIP"( http://dblp.L3S.de/Venues/NORCHIP )