Search results for "NUMA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
29	Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa	A Sub-1-µs Start-Up Time, Fully-Integrated 32-MHz Relaxation Oscillator for Low-Power Intermittent Systems.	IEICE Trans. Electron.	2018	DBLP DOI BibTeX RDF
29	Marco Proverbio, Numa Joy Bertola, Ian F. C. Smith	Outlier-Detection Methodology for Structural Identification Using Sparse Static Measurements.	Sensors	2018	DBLP DOI BibTeX RDF
29	Numa Joy Bertola, Ian F. C. Smith	Adaptive Approach for Sensor Placement Combining a Quantitative Strategy with Engineering Practice.	EG-ICE	2018	DBLP DOI BibTeX RDF
29	Kaori Matsumoto, Tetsuya Hirose, Hiroki Asano, Yuto Tsuji, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa	An ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
29	Shuto Kanzaki, Tetsuya Hirose, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa	Switched-Capacitor Voltage Buck Converter with Step-Down-Ratio and Clock-Frequency Controllers for Ultra-Low-Power IoT Devices.	ICECS	2018	DBLP DOI BibTeX RDF
29	Yuichiro Nakazawa, Tetsuya Hirose, Toshihiro Ozaki, Yuto Tsuji, Shuto Kanzaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa	Analytical Study of Multi-stage Switched-Capacitor Voltage Boost Converter for Ultra-low Voltage Energy Harvesting.	ISCAS	2018	DBLP DOI BibTeX RDF
29	Shinya Ohtani, Yu Kato, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa	Multi-Channel Convolutional Neural Networks for Image Super-Resolution.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF
29	Numa Joy Bertola, Maria Papadopoulou 0003, Didier G. Vernay, Ian F. C. Smith	Optimal Multi-Type Sensor Placement for Structural Identification by Static-Load Testing.	Sensors	2017	DBLP DOI BibTeX RDF
29	Ryo Matsuzuka, Tetsuya Hirose, Yuzuru Shizuku, Kyohei Shinonaga, Nobutaka Kuroki, Masahiro Numa	An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
29	Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa	Sub-1-μs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systems.	ASP-DAC	2017	DBLP DOI BibTeX RDF
29	Takanori Sato, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa	An ultra-low-power supercapacitor voltage monitoring system for low-voltage energy harvesting.	ICECS	2017	DBLP DOI BibTeX RDF
29	Yuto Tsuji, Tetsuya Hirose, Toshihiro Ozaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa	A 0.1-0.6 V input range voltage boost converter with low-leakage driver for low-voltage energy harvesting.	ICECS	2017	DBLP DOI BibTeX RDF
29	Hiroki Asano, Tetsuya Hirose, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa	An area-efficient, 0.022-mm2, fully integrated resistor-less relaxation oscillator for ultra-low power real-time clock applications.	ISCAS	2017	DBLP DOI BibTeX RDF
29	Numa Gueissaz, Konstantina Christakou, Jean-Yves Le Boudec, Mario Paolone	Fair control of distributed PV plants in low voltage grids.	ISGT Europe	2017	DBLP DOI BibTeX RDF
29	Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa	Fully-Integrated High-Conversion-Ratio Dual-Output Voltage Boost Converter With MPPT for Low-Voltage Energy Harvesting.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
29	Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa	A Highly Efficient Switched-Capacitor Voltage Boost Converter with Nano-Watt MPPT Controller for Low-Voltage Energy Harvesting.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2016	DBLP DOI BibTeX RDF
29	Numa Couniot, Laurent A. Francis, Denis Flandre	A 16×16 CMOS Capacitive Biosensor Array Towards Detection of Single Bacterial Cell.	IEEE Trans. Biomed. Circuits Syst.	2016	DBLP DOI BibTeX RDF
29	Hiroki Asano, Tetsuya Hirose, Keishi Tsubaki, Taro Miyoshi, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa	A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/°C fully integrated current-mode RC oscillator for real-time clock applications with PVT stability.	ESSCIRC	2016	DBLP DOI BibTeX RDF
29	Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa	A fully integrated, 1-µs start-up time, 32-MHz relaxation oscillator for low-power intermittent systems.	NEWCAS	2016	DBLP DOI BibTeX RDF
29	Yu Kato, Shinya Ohtani, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa	Image super-resolution with multi-channel convolutional neural networks.	NEWCAS	2016	DBLP DOI BibTeX RDF
29	Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa	A 0.38-μW stand-by power, 50-nA-to-1-mA load current range DC-DC converter with self-biased linear regulator for ultra-low power battery management.	A-SSCC	2016	DBLP DOI BibTeX RDF
29	Numa Couniot, Guerric de Streel, François Botman, Angelo Kuti Lusala, Denis Flandre, David Bol	A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
29	Keishi Tsubaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	A 32-kHz Real-Time Clock Oscillator with On-Chip PVT Variation Compensation Circuit for Ultra-Low Power MCUs.	IEICE Trans. Electron.	2015	DBLP DOI BibTeX RDF
29	Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada	An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2015	DBLP DOI BibTeX RDF
29	Numa Basilio, Antoine H. P. Morice, Geoffrey Marti, Gilles Montagne	High- and Low-Order Overtaking-Ability Affordances: Drivers Rely on the Maximum Velocity and Acceleration of Their Cars to Perform Overtaking Maneuvers.	Hum. Factors	2015	DBLP DOI BibTeX RDF
29	Numa Couniot, David Bol, Olivier Poncelet, Laurent A. Francis, Denis Flandre	A Capacitance-to-Frequency Converter With On-Chip Passivated Microelectrodes for Bacteria Detection in Saline Buffers Up to 575 MHz.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
29	Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada	Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
29	Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa	A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvesters.	ASP-DAC	2015	DBLP DOI BibTeX RDF
29	Meghan Watson, Numa Dancause, Mohamad Sawan	Efficient microstimulation of the brain: A parametric approach.	EMBC	2015	DBLP DOI BibTeX RDF
29	Ryo Matsuzuka, Tetsuya Hirose, Yuzuru Shizuku, Nobutaka Kuroki, Masahiro Numa	A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs.	ISCAS	2015	DBLP DOI BibTeX RDF
29	Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa	A fully-integrated, high-conversion-ratio and dual-output voltage boost converter with MPPT for low-voltage energy harvesting.	A-SSCC	2015	DBLP DOI BibTeX RDF
29	Numa Basilio	Prise de Décision et Possibilités d'action: La théorie des affordances à l'épreuve du dépassement automobile. (Decision-Making and Possibilities for Action: New insights into Affordane theory through the car overtaking).		2015	RDF
29	Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa	A Fully On-Chip, 6.66-kHz, 320-nA, 56ppm/°C, CMOS Relaxation Oscillator with PVT Variation Compensation Circuit.	IEICE Trans. Electron.	2014	DBLP DOI BibTeX RDF
29	Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa	A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvesters.	ESSCIRC	2014	DBLP DOI BibTeX RDF
29	Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada	A 24-transistor static flip-flop consisting of nors and inverters for low-power digital vlsis.	NEWCAS	2014	DBLP DOI BibTeX RDF
29	David Bol, Guerric de Streel, François Botman, Angelo Kuti Lusala, Numa Couniot	A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range.	VLSIC	2014	DBLP DOI BibTeX RDF
29	Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
29	Keishi Tsubaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	A 32.55-kHz, 472-nW, 120ppm/°C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application.	ESSCIRC	2013	DBLP DOI BibTeX RDF
29	Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
29	Masahiro Numa	FOREWORD.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
29	Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa	A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator.	ICECS	2012	DBLP DOI BibTeX RDF
29	Yuji Osaki, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa	A low-power single-slope analog-to-digital converter with digital PVT calibration.	ICECS	2012	DBLP DOI BibTeX RDF
29	Yumiko Tsuruya, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa, Osamu Kobayashi	A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs.	ESSCIRC	2012	DBLP DOI BibTeX RDF
29	Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa	Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique.	IEICE Trans. Electron.	2011	DBLP DOI BibTeX RDF
29	Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa	Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit.	IEICE Trans. Electron.	2011	DBLP DOI BibTeX RDF
29	Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	A wide input voltage range level shifter circuit for extremely low-voltage digital LSIs.	IEICE Electron. Express	2011	DBLP DOI BibTeX RDF
29	Xuguang Wang, Romain Pannetier, Nagananda Krishna Burra, Julien Numa	A Biomechanical Approach for Evaluating Motion Related Discomfort : Illustration by an Application to Pedal Clutching Movement.	HCI (17)	2011	DBLP DOI BibTeX RDF
29	Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder.	ASP-DAC	2011	DBLP DOI BibTeX RDF
29	Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs.	ESSCIRC	2011	DBLP DOI BibTeX RDF
29	Kosuke Isono, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa	A 18.9-nA standby current comparator with adaptive bias current generator.	A-SSCC	2011	DBLP DOI BibTeX RDF
29	Kosuke Shioki, Narumi Okada, Kosuke Watanabe, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	An Error Diagnosis Technique Based on Clustering of Elements.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2010	DBLP DOI BibTeX RDF
29	Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa	A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities.	ESSCIRC	2010	DBLP DOI BibTeX RDF
29	Shingo Chikamatsu, Tomohiro Nakaya, Masakazu Kouda, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa	Super-resolution technique for thermography with dual-camera system.	ISCAS	2010	DBLP DOI BibTeX RDF
29	Kosuke Shioki, Narumi Okada, Toshiro Ishihara, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
29	Kayoko Seto, Masaaki Iijima, Tetsuya Hirose, Masahiro Numa, Akira Tada, Takashi Ipposhi	A Look-ahead Active Body-biasing scheme for SOI-SRAM with dynamic VDDM control.	IEICE Electron. Express	2009	DBLP DOI BibTeX RDF
29	Kosuke Numa, Hironori Tomobe, Tatsuo Sugimoto, Masako Miyata, Kiyoko Toriumi, Jun Abe, Koichi Hori	Public Large Screen Enabled Content Collection and Connection.	KES (2)	2009	DBLP DOI BibTeX RDF
29	Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi	Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation.	J. Comput.	2008	DBLP BibTeX RDF
29	Akira Tada, Hiromi Notani, Genichi Tanaka, Toshiaki Iwamatsu, Takashi Ipposhi, Masayuki Terai, Masaaki Iijima, Masahiro Numa	Delayed-ABC SOI for crosstalk noise repair.	IEICE Electron. Express	2008	DBLP DOI BibTeX RDF
29	Kosuke Numa, Kiyoko Toriumi, Katsuaki Tanaka, Mina Akaishi, Koichi Hori	Participatory Workshop as a Creativity Support System.	KES (2)	2008	DBLP DOI BibTeX RDF
29	Toru Takahashi 0003, Norihito Numa, Takafumi Aoki, Satoshi Kondo	A geometric correction method for projected images using SIFT feature points.	PROCAMS	2008	DBLP DOI BibTeX RDF
29	Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi, Shigeto Maegawa	Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
29	Yoichi Aoyama, Hisa Numa, Ryo Fujita	Analysis of the Behavior of Cuprous Oxide by Acceleration Test for Evaluation of Heat and Fire Phenomena of Imperfectly Connected Electrical Terminal.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
29	Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi	Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
29	Akira Tada, Hiromi Notani, Genichi Tanaka, Takashi Ipposhi, Masaaki Iijima, Masahiro Numa	Charge recycling in MTCMOS circuits with block dividing.	IEICE Electron. Express	2007	DBLP DOI BibTeX RDF
29	Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi	Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM.	VLSI Design	2007	DBLP DOI BibTeX RDF
29	Nobutaka Kuroki, Nobuhiro Oka, Masahiro Numa, Keisuke Yamamoto	An Evaluation of Triple Density Error Diffusion for Medical Monochrome LCDs.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2006	DBLP DOI BibTeX RDF
29	Akira Tada, Hiromi Notani, Masahiro Numa	A novel power gating scheme with charge recycling.	IEICE Electron. Express	2006	DBLP DOI BibTeX RDF
29	Masaaki Iijima, Kenji Hamada, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi	Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI.	IEICE Electron. Express	2006	DBLP DOI BibTeX RDF
29	Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa	High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI.	PATMOS	2006	DBLP DOI BibTeX RDF
29	Kosuke Numa, Hideaki Takeda 0001, Hiroki Uematsu, Takuichi Nishimura, Yutaka Matsuo, Masahiro Hamasaki, Noriyuki Fujimura, Keisuke Ishida, Tom Hope, Yoshiyuki Nakamura, Satoshi Fujiyoshi, Kazuya Sakamoto, Hiroshi Nagata, Osamu Nakagawa, Eiji Shinbori	A Weblog Grounded to the Real World.	AAAI Spring Symposium: Computational Approaches to Analyzing Weblogs	2006	DBLP BibTeX RDF
29	Kosuke Numa, Hideaki Takeda 0001, Takuichi Nishimura, Yutaka Matsuo, Masahiro Hamasaki, Noriyuki Fujimura, Keisuke Ishida, Tom Hope, Yoshiyuki Nakamura, Satoshi Fujiyoshi, Kazuya Sakamoto, Hiroshi Nagata, Osamu Nakagawa, Eiji Shinbori	Context-Aware Weblog to Enhance Communication among Participants in a Conference.	WEBIST (1)	2006	DBLP BibTeX RDF
29	Hiroki Uematsu, Kosuke Numa, Masahiro Hamasaki, Ikki Ohmukai, Hideaki Takeda 0001	Communication support with location-based information.	AMT	2005	DBLP DOI BibTeX RDF
29	Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada	A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.	PATMOS	2004	DBLP DOI BibTeX RDF
29	Ikki Ohmukai, Hideaki Takeda 0001, Masahiro Hamasaki, Kosuke Numa, Shin Adachi	Metadata-Driven Personal Knowledge Publishing.	ISWC	2004	DBLP DOI BibTeX RDF
29	Nobutaka Kuroki, Takahiro Manabe, Masahiro Numa	Adaptive arithmetic coding for image prediction errors.	ISCAS (3)	2004	DBLP BibTeX RDF
29	Masaaki Iijima, Katsuya Fujita, Kazuki Fukuoka, Masahiro Numa, Keisuke Yamamoto, Kengo Takata	A technique for high-speed circuits on SOI using look-ahead type active body bias control.	ISCAS (2)	2004	DBLP BibTeX RDF
29	Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada	Leakage power reduction for clock gating scheme on PD-SOI.	ISCAS (2)	2004	DBLP BibTeX RDF
29	Hiroshi Inoue, Takahiro Iwasaki, Toshifumi Sugane, Masahiro Numa, Keisuke Yamamoto	Application of Error Diagnosis Technique to Incremental Synthesis.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2003	DBLP BibTeX RDF
29	Yoshikazu Kaneta, M. Numa, Takenao Ohkawa	Automatic Extraction of Protein Active Site Information from Literature Using Template Matching and Anaphora Analysis.	METMBS	2003	DBLP BibTeX RDF
29	Katsumi Sakata, Yoshiaki Nagamura, Hisataka Numa, Baltazar A. Antonio, Hideki Nagasaki, Atsuko Idonuma, Wakako Watanabe, Yuji Shimizu, Ikuo Horiuchi, Takashi Matsumoto, Takuji Sasaki, Kenichi Higo	RiceGAAS: an automated annotation system and database for rice genome sequence.	Nucleic Acids Res.	2002	DBLP DOI BibTeX RDF
29	Hirokazu Masuda, Nobutaka Kuroki, Masahiro Numa, Kotaro Hirano	Layered blind deconvolution with interband prediction.	Syst. Comput. Jpn.	2000	DBLP DOI BibTeX RDF
29	Masazumi Matsubara, Hisataka Numa, Taisuke Boku	Commodity Network Based Parallel I/O System for Massively Parallel Processors.	PDPTA	1999	DBLP BibTeX RDF
29	Atsushi Yoshikawa 0003, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita	A diagnosis method for single logic design errors in gate-level combinational circuits.	Syst. Comput. Jpn.	1997	DBLP DOI BibTeX RDF
29	Changzheng Wang, Masahiro Numa, Kotaro Hirano	ATM data transmission systems based on N-ISDN.	IEEE Trans. Commun.	1995	DBLP DOI BibTeX RDF
28	Paul Slavin, Len Freeman	Integrating Dynamic Memory Placement with Adaptive Load-Balancing for Parallel Codes on NUMA Multiprocessors.	Euro-Par	2008	DBLP DOI BibTeX RDF
28	Marc Pérache, Hervé Jourdren, Raymond Namyst	MPC: A Unified Parallel Runtime for Clusters of NUMA Machines.	Euro-Par	2008	DBLP DOI BibTeX RDF
28	Liqun Cheng, John B. Carter	Extending CC-NUMA systems to support write update optimizations.	SC	2008	DBLP DOI BibTeX RDF
28	Joseph Antony, Pete P. Janes, Alistair P. Rendell	Exploring Thread and Memory Placement on NUMA Architectures: Solaris and Linux, UltraSPARC/FirePlane and Opteron/HyperTransport.	HiPC	2006	DBLP DOI BibTeX RDF
28	François Cantonnet, Yiyi Yao, Smita Annareddy, Ahmed S. Mohamed, Tarek A. El-Ghazawi	Performance Monitoring and Evaluation of a UPC Implementation on a NUMA Architecture.	IPDPS	2003	DBLP DOI BibTeX RDF
28	Akira Nishida, Yoshio Oyanagi	Performance Evaluation of Low Level Multithreaded BLAS Kernels on Intel Processor Based cc-NUMA Systems.	ISHPC	2003	DBLP DOI BibTeX RDF
28	Guan-Joe Lai, Jywe-Fei Fang, Pei-Shan Sung, Der-Lin Pean	Scheduling Parallel Tasks onto NUMA Multiprocessors with Inter-processor Communication Overhead.	ISPA	2003	DBLP DOI BibTeX RDF
28	Manuel Arenaz, Juan Touriño, Ramon Doallo	Irregular Assignment Computations on cc-NUMA Multiprocessors.	ISHPC	2002	DBLP DOI BibTeX RDF
28	Rajarshi Mukherjee, Yozo Nakayama, Toshiya Mima	Verification of an Industrial CC-NUMA Server.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
28	Jie Tao 0001, Wolfgang Karl, Martin Schulz 0001	Visualizing the Memory Access Behavior of Shared Memory Applications on NUMA Architectures.	International Conference on Computational Science (2)	2001	DBLP DOI BibTeX RDF
28	Felix Heine, Adrian Slowik	Volume Driven Data Distribution for NUMA-Machines.	Euro-Par	2000	DBLP DOI BibTeX RDF
28	Ravi R. Iyer 0001, Laxmi N. Bhuyan, Ashwini K. Nanda	Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors.	IPDPS	2000	DBLP DOI BibTeX RDF
28	María J. Martín, Inmaculada Pardines, Francisco F. Rivera	Scheduling of Algorithms Based on Elimination Trees on NUMA Systems.	Euro-Par	1999	DBLP DOI BibTeX RDF
28	Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim, Michael L. Scott	Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors.	ISCA	1997	DBLP DOI BibTeX RDF
28	Jayashree Ramanathan, Lionel M. Ni	Critical factors in NUMA memory management.	ICDCS	1991	DBLP DOI BibTeX RDF
24	Edmund B. Nightingale, Orion Hodson, Ross McIlroy, Chris Hawblitzel, Galen C. Hunt	Helios: heterogeneous multiprocessing with satellite kernels.	SOSP	2009	DBLP DOI BibTeX RDF	operating systems, heterogeneous computing