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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1003 occurrences of 375 keywords
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Results
Found 2678 publication records. Showing 2674 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
43 | Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha |
Quality-of-service and error control techniques for network-on-chip architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 45-50, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
quality-of-service, performance, networks, networks-on-chip, interconnection, power, error detection, correction |
43 | Tang Lei, Shashi Kumar |
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey, pp. 180-189, 2003, IEEE Computer Society, 0-7695-2003-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Rickard Holsmark, Magnus Högberg, Shashi Kumar |
Modelling and Evaluation of a Network on Chip Architecture Using SDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SDL Forum ![In: SDL 2003: System Design, 11th International SDL Forum, Stuttgart, Germany, July 1-4, 2003. Proceedings, pp. 166-182, 2003, Springer. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan |
Compiler directed network-on-chip reliability enhancement for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems, LCTES 2010, Stockholm, Sweden, April 13-15, 2010, pp. 85-94, 2010, ACM, 978-1-60558-953-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
reliability, compiler, noc, chip multiprocessors |
43 | Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol |
An efficient dynamically reconfigurable on-chip network architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 166-169, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance, reconfigurable, topology, power, NoC |
43 | Tobias Bjerregaard, Shankar Mahadevan |
A survey of research and practices of Network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Comput. Surv. ![In: ACM Comput. Surv. 38(1), pp. 1, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Chip-area networks, GSI design, OCP, ULSI design, communication-centric design, SoC, system-on-chip, network-on-chip, interconnects, NoC, GALS, sockets, on-chip communication, communication abstractions |
42 | Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, Nader Bagherzadeh |
A Generic Network Interface Architecture for a Networked Processor Array (NePA). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2008, 21st International Conference, Dresden, Germany, February 25-28, 2008, Proceedings, pp. 247-260, 2008, Springer, 978-3-540-78152-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Networked Processor Array (NePA), Multiprocessor System-on-Chip (MPSoC), Interconnection Network, Network Interface, Network-on-Chip (NoC) |
42 | Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie 0001, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das |
A novel dimensionally-decomposed router for on-chip communication in 3D architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 138-149, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
3D architecture, 3D integration, network-on-chip (NoC) |
41 | Grant Martin |
Book Reviews: NoC, NoC ... Who's there? ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(6), pp. 500-501, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
technology and tools, networks, NoC |
40 | Alberto Giordano, Tim Cole, Maël Le Noc |
Spatial social networks for the humanities: A visualization and analytical model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. GIS ![In: Trans. GIS 26(4), pp. 1683-1702, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
40 | Denis Dufour, Loïc Le Noc, Bruno Tremblay, Mathieu N. Tremblay, Francis Généreux, Marc Terroux, Carl Vachon, Melanie J. Wheatley, Joshua M. Johnston, Mike Wotton, Patrice Topart |
A Bi-Spectral Microbolometer Sensor for Wildfire Measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 21(11), pp. 3690, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
40 | Yihong Yuan, Maël Le Noc |
Exploring Urban Mobility from Taxi Trajectories: A Case Study of Nanjing, China. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATA ![In: Proceedings of the 7th International Conference on Data Science, Technology and Applications, DATA 2018, Porto, Portugal, July 26-28, 2018., pp. 302-307, 2018, SciTePress, 978-989-758-318-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
40 | Manca Noc, Maja Zumer |
Eliciting mental models of music resources: a research agenda. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Res. ![In: Inf. Res. 19(4), 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
40 | Manca Noc, Maja Zumer |
The completeness of articles and citation in the Slovene Wikipedia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Program ![In: Program 48(1), pp. 53-75, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
40 | Martin Rauber, Dusan Stajer, Marko Noc, Todd T. Schlegel, Vito Starc |
High Resolution ECG Differences between Hospital Survivors and Non-survivors of Out-of-Hospital Cardiac Arrest during Mild Therapeutic Hypothermia. (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
CinC ![In: Computing in Cardiology, CinC 2014, Cambridge, Massachusetts, USA, September 7-10, 2014, pp. 1093-1096, 2014, www.cinc.org, 978-1-4799-4346-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
40 | Martin Rauber, Dusan Stajer, Marko Noc, Todd T. Schlegel, Vito Starc |
High resolution ECG Changes in Survivors of Out-of-Hospital Cardiac Arrest during and after Mild Therapeutic Hypothermia. (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
CinC ![In: Computing in Cardiology, CinC 2013, Zaragoza, Spain, September 22-25, 2013, pp. 595-598, 2013, www.cinc.org, 978-1-4799-0884-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
40 | Timothy D. Pope, Christine Alain, Loïc Le Noc, Hubert Jerominek, L. Ngo Phong, W. Zheng |
Performance of a 512x3 Pixel Microbolometer Detector for Space Imaging Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMENS ![In: 2005 International Conference on MEMS, NANO, and Smart Systems (ICMENS 2005), 24-27 July 2005, Banff, Alberta, Canada, pp. 275-276, 2005, IEEE Computer Society, 0-7695-2398-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Samir Ilias, Patrice Topart, Sébastien Leclair, Jean-Sébastien Côté, Loïc Le Noc, Francis Picard, Hubert Jerominek |
Novel Electroplating-Based Technology for the Fabrication of Giant Micromirrors for Space and Terrestrial Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMENS ![In: 2004 International Conference on MEMS, NANO, and Smart Systems (ICMENS 2004), 25-27 August 2004, Banff, Alberta, Canada, pp. 257-261, 2004, IEEE Computer Society, 0-7695-2189-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | L. Ngo Phong, J. Lee, I. Ressejac, M. Maszkiewicz, W. Zheng, S. Crisan, Loïc Le Noc, Francis Picard, Hubert Jerominek |
Closed Loop Micromanipulators for Optical Metrology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMENS ![In: 2004 International Conference on MEMS, NANO, and Smart Systems (ICMENS 2004), 25-27 August 2004, Banff, Alberta, Canada, pp. 414-420, 2004, IEEE Computer Society, 0-7695-2189-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Bruce Mathewson |
The evolution of SOC interconnect and how NOC fits within it. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 312-313, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
AMBA AXI, network on chip |
38 | Radu Marculescu, Ümit Y. Ogras, Li-Shiuan Peh, Natalie D. Enright Jerger, Yatin Vasant Hoskote |
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1), pp. 3-21, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | Simone Medardoni, Marcello Lajolo, Davide Bertozzi |
Variation tolerant NoC design by means of self-calibrating links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1402-1407, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Hung-Chih Lai, Radu Marculescu, Marios Savvides, Tsuhan Chen |
Communication-Aware Face Detection Using Noc Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICVS ![In: Computer Vision Systems, 6th International Conference, ICVS 2008, Santorini, Greece, May 12-15, 2008, Proceedings, pp. 181-189, 2008, Springer, 978-3-540-79546-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Network-on-Chip, Face detection, Hardware Architecture |
38 | Ruchika Verma, Ali Akoglu |
A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Mahmoud Moadeli, Wim Vanderbauwhede, Ali Shahrabi |
A Performance Model of Communication in the Quarc NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 14th International Conference on Parallel and Distributed Systems, ICPADS 2008, Melbourne, Victoria, Australia, December 8-10, 2008, pp. 908-913, 2008, IEEE Computer Society, 978-0-7695-3434-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Song Chai, Chang Wu, Yubai Li, Zhongming Yang |
A NoC Simulation and Verification Platform Based on SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (3) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 3: Grid Computing / Distributed and Parallel Computing / Information Security, December 12-14, 2008, Wuhan, China, pp. 423-426, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Jean-Philippe Diguet, Samuel Evain, Romain Vaslin, Guy Gogniat, Emmanuel Juin |
NOC-centric Security of Reconfigurable SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 223-232, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet |
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 295-306, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon W. Moore |
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 283-294, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini |
NoC Design and Implementation in 65nm Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 273-282, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Luciano Bononi, Nicola Concer, Miltos D. Grammatikakis, Marcello Coppola, Riccardo Locatelli |
NoC Topologies Exploration based on Mapping and Simulation Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 543-546, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara |
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 12th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007, pp. 35-42, 2007, IEEE Computer Society, 978-0-7695-2827-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Mahdiar Hosein Ghadiry, Mahdieh Nadi Senjani, M. T. Manzuri-Shalmani, Dara Rahmati |
Effect of number of faults on NoC power and performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 13th International Conference on Parallel and Distributed Systems, ICPADS 2007, Hsinchu, Taiwan, December 5-7, 2007, pp. 1-9, 2007, IEEE Computer Society, 978-1-4244-1889-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Ben A. Abderazek, Mushfiquzzaman Akanda, Tsutomu Yoshinaga, Masahiro Sowa |
Mathematical Model for Multiobjective Synthesis of NoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 2007 International Conference on Parallel Processing Workshops (ICPP Workshops 2007), 10-14 September 2007, Xi-An, China, pp. 36, 2007, IEEE Computer Society, 978-0-7695-2934-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Sumit D. Mediratta, Jeffrey T. Draper |
Characterization of a Fault-tolerant NoC Router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 381-384, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Huy Nam Nguyen, Vu-Duc Ngo, Younghwan Bae, Hanjin Cho, Hae-Wook Choi |
An QoS Aware Mapping of Cores Onto NoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, 5th International Symposium, ISPA 2007, Niagara Falls, Canada, August 29-31, 2007, Proceedings, pp. 278-288, 2007, Springer, 978-3-540-74741-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Luca Benini |
Application specific NoC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 491-495, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
application-specific integrated systems, systems on chip, networks on chip, design methodologies |
38 | Balasubramanian Sethuraman, Ranga Vemuri |
optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 947-952, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Frédéric Pétrot, Alain Greiner, Pascal Gomez |
On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 53-60, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Guangyu Chen, Feihui Li, Mahmut T. Kandemir, Mary Jane Irwin |
Reducing NoC energy consumption through compiler-directed channel voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2006 Conference on Programming Language Design and Implementation, Ottawa, Ontario, Canada, June 11-14, 2006, pp. 193-203, 2006, ACM, 1-59593-320-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
compiler, network-on-chip, energy |
38 | Cristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande |
On-line Fault Detection and Location for NoC Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, pp. 145-150, 2006, IEEE Computer Society, 0-7695-2620-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Yuanfang Hu, Yi Zhu 0002, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng |
Communication latency aware low power NoC synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 574-579, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
network-on-chip, topology, power, latency |
38 | Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin |
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 54-63, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Ümit Y. Ogras, Jingcao Hu, Radu Marculescu |
Key research problems in NoC design: a holistic perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 69-74, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Networks-on-Chip motivation, problem formulation, proposed solutions and open research problems, systems-on-chip, multi-processor systems |
38 | Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh |
Methodologies and Algorithms for Testing Switch-Based NoC Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 238-246, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Srinivasan Murali, Giovanni De Micheli |
Bandwidth-Constrained Mapping of Cores onto NoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 896-903, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
routing, Systems on Chips, mapping, Networks on Chips, bandwidth, cores |
38 | Sílvio R. F. de Fernandes, Bruno Cruz de Oliveira, Ivan Saraiva Silva |
Using NoC routers as processing elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SoC, system-on-chip, network-on-chip, routing algorithm, NoC, MP-SoC |
38 | Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli |
NoC topology synthesis for supporting shutdown of voltage islands in SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 822-825, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
shutdown, topology, NoC, leakage power, voltage islands |
38 | Shankar Neelkrishnan, Mei Yang, Yingtao Jiang, Lei Zhang 0014, Yulu Yang, Enyue Lu, Xiao-chun Yun |
Design and Implementation of a Parameterized NoC Router and its Application to Build PRDT-Based NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fifth International Conference on Information Technology: New Generations (ITNG 2008), 7-8 April 2008, Las Vegas, Nevada, USA, pp. 259-264, 2008, IEEE Computer Society, 978-0-7695-3099-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
PRDT, router, NoC |
38 | Oreste Villa, Gianluca Palermo, Cristina Silvano |
Efficiency and scalability of barrier synchronization on NoC based many-core architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 81-90, 2008, ACM. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
scalability, synchronization, efficiency, Multicore, NoC, barrier, Manycore |
37 | Guangyu Chen, Feihui Li, Mahmut T. Kandemir |
Compiler-directed application mapping for NoC based chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 155-157, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
compilers, power optimization, Network-on-Chip (NoC), application mapping |
37 | Seung Eun Lee, Nader Bagherzadeh |
Increasing the throughput of an adaptive router in network-on-chip (NoC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 82-87, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
adaptive router, interconnection network, chip-multiprocessor, wormhole routing, network-on-chip (NoC) |
36 | Riad Ben Mouhoub, Omar Hammami |
NoC Monitoring Hardware Support for Fast NoC Design Space Exploration and Potential NoC Partial Dynamic Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IES ![In: International Symposium on Industrial Embedded Systems, IES 2006, Antibes Juan-Les-Pins, France, October 18-20, 2006, pp. 1-10, 2006, IEEE, 1-4244-0777-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Jason Lee, Lesley Shannon |
Predicting the performance of application-specific NoCs implemented on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 23-32, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance, FPGAs, topologies, heterogeneous, NoCs, homogeneous, application-specific, routability |
35 | Jason Cong, Chunyue Liu, Glenn Reinman |
ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 443-448, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
application-specific Network-on-Chip, deadlock-free routing |
35 | Xiang Zhang, Ahmed Louri |
A multilayer nanophotonic interconnection network for on-chip many-core communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 156-161, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
interconnection networks, CMP, 3D, silicon photonics |
35 | Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania |
Application Specific Routing Algorithms for Networks on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 20(3), pp. 316-330, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Luciano Ost, Guilherme Montez Guindani, Leandro Soares Indrusiak, Cezar Reinbrecht, Thiago Raupp da Rosa, Fernando Moraes 0001 |
A high abstraction, high accuracy power estimation model for networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
high abstraction modeling, networks-on-chip, power modeling |
35 | Sai Prashanth Muralidhara, Mahmut T. Kandemir |
Communication Based Proactive Link Power Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, pp. 198-215, 2009, Springer, 978-3-540-92989-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Cristian Grecu |
Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 67-81, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Crosstalk avoidance, Multiple error correction, Joint codes, Low power, Network on Chip, Transient errors |
35 | Ümit Y. Ogras, Radu Marculescu |
Analysis and optimization of prediction-based flow control in networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(1), pp. 11:1-11:28, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
congestion control, networks-on-chip, flow control, Multi-processor systems |
35 | Suboh A. Suboh, Mohamed Bakhouya, Jaafar Gaber, Tarek A. El-Ghazawi |
An interconnection architecture for network-on-chip systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Telecommun. Syst. ![In: Telecommun. Syst. 37(1-3), pp. 137-144, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Switching and routing, Network on chip, Network analysis, Modeling and simulation, On-chip interconnects |
35 | Bart Vermeulen, Kees Goossens, Siddharth Umrani |
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 3-12, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
communication-centric debug, debug, network-on-chip, design for debug |
35 | Xiao-Jing Zhu, Hongbo Zeng, Kun Huang, Ge Zhang |
Round-robin based scheduling algorithms for FIFO IQ switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNSC ![In: Proceedings of the IEEE International Conference on Networking, Sensing and Control, ICNSC 2008, Hainan, China, 6-8 April 2008, pp. 46-51, 2008, IEEE, 978-1-4244-1685-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Hsin-Chou Chi, Chia-Ming Wu, Jun-Hui Lee |
Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 415-420, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
network-on-chip architectures, scheduling, mapping, circuit-switched networks |
35 | Arun Janarthanan, Karen A. Tomko |
MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA Based On-Chip Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 397-402, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Cristian Grecu, André Ivanov, Resve A. Saleh, Partha Pratim Pande |
Testing Network-on-Chip Communication Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12), pp. 2201-2214, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach |
Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 216, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Andreas Hansson 0001, Kees Goossens |
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 233-242, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Cristian Grecu |
Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 317-324, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Nikolaos Zompakis, Lazaros Papadopoulos, Georgios Ch. Sirakoulis, Dimitrios Soudris |
Implementing cellular automata modeled applications on network-on-chip platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 288-291, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su |
An architectural co-synthesis algorithm for energy-aware network-on-chip design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), Seoul, Korea, March 11-15, 2007, pp. 680-684, 2007, ACM, 1-59593-480-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Andreas Hansson 0001, Martijn Coenen, Kees Goossens |
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 954-959, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Jan Willem van den Brand, Calin Ciordas, Kees Goossens, Twan Basten |
Congestion-controlled best-effort communication for networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 948-953, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Akash Kumar 0001, Andreas Hansson 0001, Jos Huisken, Henk Corporaal |
Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 117-122, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Andreas Ehliar, Dake Liu |
An fpga based open source network-on-chip architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 800-803, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Stephan Kubisch, Claas Cornelius, Ronald Hecht, Dirk Timmermann |
Mapping a Pipelined Data Path onto a Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIES ![In: IEEE Second International Symposium on Industrial Embedded Systems, SIES 2007, Hotel Costa da Caparica, Lisbon, Portugal, July 4-6, 2007, pp. 178-185, 2007, IEEE, 1-4244-0840-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Henrique C. Freitas, Dalton M. Colombo, Fernanda Lima Kastensmidt, Philippe Olivier Alexandre Navaux |
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3776-3779, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri |
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2007, Orlando, Florida, USA, December 3-4, 2007, pp. 47-56, 2007, ACM, 978-1-59593-945-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
network-on-chip, low-power design |
35 | Vassos Soteriou, Hangsheng Wang, Li-Shiuan Peh |
A Statistical Traffic Model for On-Chip Interconnection Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 14th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2006), 11-14 September 2006, Monterey, California, USA, pp. 104-116, 2006, IEEE Computer Society, 0-7695-2573-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu |
Exploiting Software Pipelining for Network-on-Chip architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 295-302, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Luciano Bononi, Nicola Concer |
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 154-159, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli |
A methodology for mapping multiple use-cases onto networks on chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 118-123, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
dynamic re-configuration, systems on chips, networks on chips, use-cases, modes |
35 | Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen |
A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 641-648, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach |
A DFT Architecture for Asynchronous Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 219-224, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Mário P. Véstias, Horácio C. Neto |
A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Balasubramanian Sethuraman, Ranga Vemuri |
Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Balasubramanian Sethuraman |
Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-2, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Leonel Tedesco, Aline Mello 0001, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes |
Application driven traffic modeling for NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 62-67, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
QoS, applications, networks on chip, traffic modeling |
35 | Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli |
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 130-135, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
systems-on-chip, networks-on-chip, buffers, area |
35 | Antoine Scherrer, Antoine Fraboulet, Tanguy Risset |
Automatic phase detection for stochastic on-chip traffic generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 88-93, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
phase behavior, stochastic traffic modeling, performance evaluation, network-on-chip, traffic generation |
35 | Vu-Duc Ngo, Huy Nam Nguyen, Younghwan Bae, Hanjin Cho, Hae-Wook Choi |
Throughput Aware Mapping for Network on Chip Design of H.264 Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA Workshops ![In: Frontiers of High Performance Computing and Networking - ISPA 2006 Workshops, ISPA 2006 International Workshops, FHPCN, XHPC, S-GRACE, GridGIS, HPC-GTP, PDCE, ParDMCom, WOMP, ISDF, and UPWN, Sorrento, Italy, December 4-7, 2006, Proceedings, pp. 791-802, 2006, Springer, 3-540-49860-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya |
QOS Driven Network-on-Chip Design for Real Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1291-1295, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie 0001, Chita R. Das, Vijay Degalahal |
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 657-664, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago González Pestana, Andrei Radulescu, Edwin Rijpkema |
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1182-1187, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Flávio Rech Wagner, Altamiro Amadeu Susin |
Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 190-195, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
mapping and optimization algorithms, systems-on-chip, networks-on-chip |
35 | Krishnan Srinivasan, Karam S. Chatha |
A technique for low energy mapping and routing in network-on-chip architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 387-392, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
core mapping, routing, network-on-chip, automated design, mesh topology |
35 | Krishnan Srinivasan, Karam S. Chatha |
ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 623-628, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne P. Burleson |
NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 69-75, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
on-chip, spice-based, network-on-chip, interconnects, signaling |
35 | Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod |
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 422-429, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
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