Search results for "NoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
43	Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha	Quality-of-service and error control techniques for network-on-chip architectures.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	quality-of-service, performance, networks, networks-on-chip, interconnection, power, error detection, correction
43	Tang Lei, Shashi Kumar	A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture.	DSD	2003	DBLP DOI BibTeX RDF
43	Rickard Holsmark, Magnus Högberg, Shashi Kumar	Modelling and Evaluation of a Network on Chip Architecture Using SDL.	SDL Forum	2003	DBLP DOI BibTeX RDF
43	Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan	Compiler directed network-on-chip reliability enhancement for chip multiprocessors.	LCTES	2010	DBLP DOI BibTeX RDF	reliability, compiler, noc, chip multiprocessors
43	Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol	An efficient dynamically reconfigurable on-chip network architecture.	DAC	2010	DBLP DOI BibTeX RDF	performance, reconfigurable, topology, power, NoC
43	Tobias Bjerregaard, Shankar Mahadevan	A survey of research and practices of Network-on-chip.	ACM Comput. Surv.	2006	DBLP DOI BibTeX RDF	Chip-area networks, GSI design, OCP, ULSI design, communication-centric design, SoC, system-on-chip, network-on-chip, interconnects, NoC, GALS, sockets, on-chip communication, communication abstractions
42	Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, Nader Bagherzadeh	A Generic Network Interface Architecture for a Networked Processor Array (NePA).	ARCS	2008	DBLP DOI BibTeX RDF	Networked Processor Array (NePA), Multiprocessor System-on-Chip (MPSoC), Interconnection Network, Network Interface, Network-on-Chip (NoC)
42	Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie 0001, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das	A novel dimensionally-decomposed router for on-chip communication in 3D architectures.	ISCA	2007	DBLP DOI BibTeX RDF	3D architecture, 3D integration, network-on-chip (NoC)
41	Grant Martin	Book Reviews: NoC, NoC ... Who's there?	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	technology and tools, networks, NoC
40	Alberto Giordano, Tim Cole, Maël Le Noc	Spatial social networks for the humanities: A visualization and analytical model.	Trans. GIS	2022	DBLP DOI BibTeX RDF
40	Denis Dufour, Loïc Le Noc, Bruno Tremblay, Mathieu N. Tremblay, Francis Généreux, Marc Terroux, Carl Vachon, Melanie J. Wheatley, Joshua M. Johnston, Mike Wotton, Patrice Topart	A Bi-Spectral Microbolometer Sensor for Wildfire Measurement.	Sensors	2021	DBLP DOI BibTeX RDF
40	Yihong Yuan, Maël Le Noc	Exploring Urban Mobility from Taxi Trajectories: A Case Study of Nanjing, China.	DATA	2018	DBLP DOI BibTeX RDF
40	Manca Noc, Maja Zumer	Eliciting mental models of music resources: a research agenda.	Inf. Res.	2014	DBLP BibTeX RDF
40	Manca Noc, Maja Zumer	The completeness of articles and citation in the Slovene Wikipedia.	Program	2014	DBLP DOI BibTeX RDF
40	Martin Rauber, Dusan Stajer, Marko Noc, Todd T. Schlegel, Vito Starc	High Resolution ECG Differences between Hospital Survivors and Non-survivors of Out-of-Hospital Cardiac Arrest during Mild Therapeutic Hypothermia. (PDF / PS)	CinC	2014	DBLP BibTeX RDF
40	Martin Rauber, Dusan Stajer, Marko Noc, Todd T. Schlegel, Vito Starc	High resolution ECG Changes in Survivors of Out-of-Hospital Cardiac Arrest during and after Mild Therapeutic Hypothermia. (PDF / PS)	CinC	2013	DBLP BibTeX RDF
40	Timothy D. Pope, Christine Alain, Loïc Le Noc, Hubert Jerominek, L. Ngo Phong, W. Zheng	Performance of a 512x3 Pixel Microbolometer Detector for Space Imaging Applications.	ICMENS	2005	DBLP DOI BibTeX RDF
40	Samir Ilias, Patrice Topart, Sébastien Leclair, Jean-Sébastien Côté, Loïc Le Noc, Francis Picard, Hubert Jerominek	Novel Electroplating-Based Technology for the Fabrication of Giant Micromirrors for Space and Terrestrial Applications.	ICMENS	2004	DBLP DOI BibTeX RDF
40	L. Ngo Phong, J. Lee, I. Ressejac, M. Maszkiewicz, W. Zheng, S. Crisan, Loïc Le Noc, Francis Picard, Hubert Jerominek	Closed Loop Micromanipulators for Optical Metrology.	ICMENS	2004	DBLP DOI BibTeX RDF
38	Bruce Mathewson	The evolution of SOC interconnect and how NOC fits within it.	DAC	2010	DBLP DOI BibTeX RDF	AMBA AXI, network on chip
38	Radu Marculescu, Ümit Y. Ogras, Li-Shiuan Peh, Natalie D. Enright Jerger, Yatin Vasant Hoskote	Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
38	Simone Medardoni, Marcello Lajolo, Davide Bertozzi	Variation tolerant NoC design by means of self-calibrating links.	DATE	2008	DBLP DOI BibTeX RDF
38	Hung-Chih Lai, Radu Marculescu, Marios Savvides, Tsuhan Chen	Communication-Aware Face Detection Using Noc Architecture.	ICVS	2008	DBLP DOI BibTeX RDF	Network-on-Chip, Face detection, Hardware Architecture
38	Ruchika Verma, Ali Akoglu	A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation.	IPDPS	2008	DBLP DOI BibTeX RDF
38	Mahmoud Moadeli, Wim Vanderbauwhede, Ali Shahrabi	A Performance Model of Communication in the Quarc NoC.	ICPADS	2008	DBLP DOI BibTeX RDF
38	Song Chai, Chang Wu, Yubai Li, Zhongming Yang	A NoC Simulation and Verification Platform Based on SystemC.	CSSE (3)	2008	DBLP DOI BibTeX RDF
38	Jean-Philippe Diguet, Samuel Evain, Romain Vaslin, Guy Gogniat, Emmanuel Juin	NOC-centric Security of Reconfigurable SoC.	NOCS	2007	DBLP DOI BibTeX RDF
38	Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet	ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC.	NOCS	2007	DBLP DOI BibTeX RDF
38	Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon W. Moore	Implications of Rent's Rule for NoC Design and Its Fault-Tolerance.	NOCS	2007	DBLP DOI BibTeX RDF
38	Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini	NoC Design and Implementation in 65nm Technology.	NOCS	2007	DBLP DOI BibTeX RDF
38	Luciano Bononi, Nicola Concer, Miltos D. Grammatikakis, Marcello Coppola, Riccardo Locatelli	NoC Topologies Exploration based on Mapping and Simulation Models.	DSD	2007	DBLP DOI BibTeX RDF
38	Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara	Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints.	ETS	2007	DBLP DOI BibTeX RDF
38	Mahdiar Hosein Ghadiry, Mahdieh Nadi Senjani, M. T. Manzuri-Shalmani, Dara Rahmati	Effect of number of faults on NoC power and performance.	ICPADS	2007	DBLP DOI BibTeX RDF
38	Ben A. Abderazek, Mushfiquzzaman Akanda, Tsutomu Yoshinaga, Masahiro Sowa	Mathematical Model for Multiobjective Synthesis of NoC Architectures.	ICPP Workshops	2007	DBLP DOI BibTeX RDF
38	Sumit D. Mediratta, Jeffrey T. Draper	Characterization of a Fault-tolerant NoC Router.	ISCAS	2007	DBLP DOI BibTeX RDF
38	Huy Nam Nguyen, Vu-Duc Ngo, Younghwan Bae, Hanjin Cho, Hae-Wook Choi	An QoS Aware Mapping of Cores Onto NoC Architectures.	ISPA	2007	DBLP DOI BibTeX RDF
38	Luca Benini	Application specific NoC design.	DATE	2006	DBLP DOI BibTeX RDF	application-specific integrated systems, systems on chip, networks on chip, design methodologies
38	Balasubramanian Sethuraman, Ranga Vemuri	optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs.	DATE	2006	DBLP DOI BibTeX RDF
38	Frédéric Pétrot, Alain Greiner, Pascal Gomez	On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures.	DSD	2006	DBLP DOI BibTeX RDF
38	Guangyu Chen, Feihui Li, Mahmut T. Kandemir, Mary Jane Irwin	Reducing NoC energy consumption through compiler-directed channel voltage scaling.	PLDI	2006	DBLP DOI BibTeX RDF	compiler, network-on-chip, energy
38	Cristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande	On-line Fault Detection and Location for NoC Interconnects.	IOLTS	2006	DBLP DOI BibTeX RDF
38	Yuanfang Hu, Yi Zhu 0002, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng	Communication latency aware low power NoC synthesis.	DAC	2006	DBLP DOI BibTeX RDF	network-on-chip, topology, power, latency
38	Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin	An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework.	ASYNC	2005	DBLP DOI BibTeX RDF
38	Ümit Y. Ogras, Jingcao Hu, Radu Marculescu	Key research problems in NoC design: a holistic perspective.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	Networks-on-Chip motivation, problem formulation, proposed solutions and open research problems, systems-on-chip, multi-processor systems
38	Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh	Methodologies and Algorithms for Testing Switch-Based NoC Interconnects.	DFT	2005	DBLP DOI BibTeX RDF
38	Srinivasan Murali, Giovanni De Micheli	Bandwidth-Constrained Mapping of Cores onto NoC Architectures.	DATE	2004	DBLP DOI BibTeX RDF	routing, Systems on Chips, mapping, Networks on Chips, bandwidth, cores
38	Sílvio R. F. de Fernandes, Bruno Cruz de Oliveira, Ivan Saraiva Silva	Using NoC routers as processing elements.	SBCCI	2009	DBLP DOI BibTeX RDF	SoC, system-on-chip, network-on-chip, routing algorithm, NoC, MP-SoC
38	Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli	NoC topology synthesis for supporting shutdown of voltage islands in SoCs.	DAC	2009	DBLP DOI BibTeX RDF	shutdown, topology, NoC, leakage power, voltage islands
38	Shankar Neelkrishnan, Mei Yang, Yingtao Jiang, Lei Zhang 0014, Yulu Yang, Enyue Lu, Xiao-chun Yun	Design and Implementation of a Parameterized NoC Router and its Application to Build PRDT-Based NoCs.	ITNG	2008	DBLP DOI BibTeX RDF	PRDT, router, NoC
38	Oreste Villa, Gianluca Palermo, Cristina Silvano	Efficiency and scalability of barrier synchronization on NoC based many-core architectures.	CASES	2008	DBLP DOI BibTeX RDF	scalability, synchronization, efficiency, Multicore, NoC, barrier, Manycore
37	Guangyu Chen, Feihui Li, Mahmut T. Kandemir	Compiler-directed application mapping for NoC based chip multiprocessors.	LCTES	2007	DBLP DOI BibTeX RDF	compilers, power optimization, Network-on-Chip (NoC), application mapping
37	Seung Eun Lee, Nader Bagherzadeh	Increasing the throughput of an adaptive router in network-on-chip (NoC).	CODES+ISSS	2006	DBLP DOI BibTeX RDF	adaptive router, interconnection network, chip-multiprocessor, wormhole routing, network-on-chip (NoC)
36	Riad Ben Mouhoub, Omar Hammami	NoC Monitoring Hardware Support for Fast NoC Design Space Exploration and Potential NoC Partial Dynamic Reconfiguration.	IES	2006	DBLP DOI BibTeX RDF
35	Jason Lee, Lesley Shannon	Predicting the performance of application-specific NoCs implemented on FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	performance, FPGAs, topologies, heterogeneous, NoCs, homogeneous, application-specific, routability
35	Jason Cong, Chunyue Liu, Glenn Reinman	ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip.	DAC	2010	DBLP DOI BibTeX RDF	application-specific Network-on-Chip, deadlock-free routing
35	Xiang Zhang, Ahmed Louri	A multilayer nanophotonic interconnection network for on-chip many-core communications.	DAC	2010	DBLP DOI BibTeX RDF	interconnection networks, CMP, 3D, silicon photonics
35	Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania	Application Specific Routing Algorithms for Networks on Chip.	IEEE Trans. Parallel Distributed Syst.	2009	DBLP DOI BibTeX RDF
35	Luciano Ost, Guilherme Montez Guindani, Leandro Soares Indrusiak, Cezar Reinbrecht, Thiago Raupp da Rosa, Fernando Moraes 0001	A high abstraction, high accuracy power estimation model for networks-on-chip.	SBCCI	2009	DBLP DOI BibTeX RDF	high abstraction modeling, networks-on-chip, power modeling
35	Sai Prashanth Muralidhara, Mahmut T. Kandemir	Communication Based Proactive Link Power Management.	HiPEAC	2009	DBLP DOI BibTeX RDF
35	Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Cristian Grecu	Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Crosstalk avoidance, Multiple error correction, Joint codes, Low power, Network on Chip, Transient errors
35	Ümit Y. Ogras, Radu Marculescu	Analysis and optimization of prediction-based flow control in networks-on-chip.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	congestion control, networks-on-chip, flow control, Multi-processor systems
35	Suboh A. Suboh, Mohamed Bakhouya, Jaafar Gaber, Tarek A. El-Ghazawi	An interconnection architecture for network-on-chip systems.	Telecommun. Syst.	2008	DBLP DOI BibTeX RDF	Switching and routing, Network on chip, Network analysis, Modeling and simulation, On-chip interconnects
35	Bart Vermeulen, Kees Goossens, Siddharth Umrani	Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip.	NOCS	2008	DBLP DOI BibTeX RDF	communication-centric debug, debug, network-on-chip, design for debug
35	Xiao-Jing Zhu, Hongbo Zeng, Kun Huang, Ge Zhang	Round-robin based scheduling algorithms for FIFO IQ switch.	ICNSC	2008	DBLP DOI BibTeX RDF
35	Hsin-Chou Chi, Chia-Ming Wu, Jun-Hui Lee	Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures.	DELTA	2008	DBLP DOI BibTeX RDF	network-on-chip architectures, scheduling, mapping, circuit-switched networks
35	Arun Janarthanan, Karen A. Tomko	MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA Based On-Chip Networks.	VLSI Design	2008	DBLP DOI BibTeX RDF
35	Cristian Grecu, André Ivanov, Resve A. Saleh, Partha Pratim Pande	Testing Network-on-Chip Communication Fabrics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
35	Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach	Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip.	NOCS	2007	DBLP DOI BibTeX RDF
35	Andreas Hansson 0001, Kees Goossens	Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases.	NOCS	2007	DBLP DOI BibTeX RDF
35	Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Cristian Grecu	Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding.	ISVLSI	2007	DBLP DOI BibTeX RDF
35	Nikolaos Zompakis, Lazaros Papadopoulos, Georgios Ch. Sirakoulis, Dimitrios Soudris	Implementing cellular automata modeled applications on network-on-chip platforms.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
35	Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su	An architectural co-synthesis algorithm for energy-aware network-on-chip design.	SAC	2007	DBLP DOI BibTeX RDF
35	Andreas Hansson 0001, Martijn Coenen, Kees Goossens	Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip.	DATE	2007	DBLP DOI BibTeX RDF
35	Jan Willem van den Brand, Calin Ciordas, Kees Goossens, Twan Basten	Congestion-controlled best-effort communication for networks-on-chip.	DATE	2007	DBLP DOI BibTeX RDF
35	Akash Kumar 0001, Andreas Hansson 0001, Jos Huisken, Henk Corporaal	Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip.	DATE	2007	DBLP DOI BibTeX RDF
35	Andreas Ehliar, Dake Liu	An fpga based open source network-on-chip architecture.	FPL	2007	DBLP DOI BibTeX RDF
35	Stephan Kubisch, Claas Cornelius, Ronald Hecht, Dirk Timmermann	Mapping a Pipelined Data Path onto a Network-on-Chip.	SIES	2007	DBLP DOI BibTeX RDF
35	Henrique C. Freitas, Dalton M. Colombo, Fernanda Lima Kastensmidt, Philippe Olivier Alexandre Navaux	Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
35	Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri	Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture.	ANCS	2007	DBLP DOI BibTeX RDF	network-on-chip, low-power design
35	Vassos Soteriou, Hangsheng Wang, Li-Shiuan Peh	A Statistical Traffic Model for On-Chip Interconnection Networks.	MASCOTS	2006	DBLP DOI BibTeX RDF
35	Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu	Exploiting Software Pipelining for Network-on-Chip architectures.	ISVLSI	2006	DBLP DOI BibTeX RDF
35	Luciano Bononi, Nicola Concer	Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
35	Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli	A methodology for mapping multiple use-cases onto networks on chips.	DATE	2006	DBLP DOI BibTeX RDF	dynamic re-configuration, systems on chips, networks on chips, use-cases, modes
35	Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen	A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip.	DSD	2006	DBLP DOI BibTeX RDF
35	Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach	A DFT Architecture for Asynchronous Networks-on-Chip.	ETS	2006	DBLP DOI BibTeX RDF
35	Mário P. Véstias, Horácio C. Neto	A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation.	FPL	2006	DBLP DOI BibTeX RDF
35	Balasubramanian Sethuraman, Ranga Vemuri	Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip.	FPL	2006	DBLP DOI BibTeX RDF
35	Balasubramanian Sethuraman	Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip.	FPL	2006	DBLP DOI BibTeX RDF
35	Leonel Tedesco, Aline Mello 0001, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes	Application driven traffic modeling for NoCs.	SBCCI	2006	DBLP DOI BibTeX RDF	QoS, applications, networks on chip, traffic modeling
35	Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli	A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	systems-on-chip, networks-on-chip, buffers, area
35	Antoine Scherrer, Antoine Fraboulet, Tanguy Risset	Automatic phase detection for stochastic on-chip traffic generation.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	phase behavior, stochastic traffic modeling, performance evaluation, network-on-chip, traffic generation
35	Vu-Duc Ngo, Huy Nam Nguyen, Younghwan Bae, Hanjin Cho, Hae-Wook Choi	Throughput Aware Mapping for Network on Chip Design of H.264 Decoder.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
35	Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya	QOS Driven Network-on-Chip Design for Real Time Systems.	CCECE	2006	DBLP DOI BibTeX RDF
35	Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie 0001, Chita R. Das, Vijay Degalahal	A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.	VLSI Design	2006	DBLP DOI BibTeX RDF
35	Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago González Pestana, Andrei Radulescu, Edwin Rijpkema	A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification.	DATE	2005	DBLP DOI BibTeX RDF
35	Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Flávio Rech Wagner, Altamiro Amadeu Susin	Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures.	SBCCI	2005	DBLP DOI BibTeX RDF	mapping and optimization algorithms, systems-on-chip, networks-on-chip
35	Krishnan Srinivasan, Karam S. Chatha	A technique for low energy mapping and routing in network-on-chip architectures.	ISLPED	2005	DBLP DOI BibTeX RDF	core mapping, routing, network-on-chip, automated design, mesh topology
35	Krishnan Srinivasan, Karam S. Chatha	ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis.	VLSI Design	2005	DBLP DOI BibTeX RDF
35	Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne P. Burleson	NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods.	SLIP	2004	DBLP DOI BibTeX RDF	on-chip, spice-based, network-on-chip, interconnects, signaling
35	Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod	Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures.	ICCD	2004	DBLP DOI BibTeX RDF