Search results for "PLL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Xiaohua Huang, Bowen Wang, Woogeun Rhee, Zhihua Wang 0001	A 5.4GHz ΔΣ Bang-Bang PLL with 19dB In-Band Noise Reduction by Using a Nested PLL Filter.	VLSI-DAT	2020	DBLP DOI BibTeX RDF
26	Elie Noumon Allini, Oto Petura, Viktor Fischer, Florent Bernard	Optimization of the PLL configuration in a PLL-based TRNG design.	DATE	2018	DBLP DOI BibTeX RDF
26	Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Robert Bogdan Staszewski	A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
26	Dhon-Gue Lee, Patrick P. Mercier	AMASS PLL: An Active-Mixer-Adopted Sub-Sampling PLL Achieving an FOM of -255.5DB and a Reference Spur of -66.6DBC.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
26	B. C. Sarkar, S. Chakraborty 0002	Self-oscillations of a third order PLL in periodic and chaotic mode and its tracking in a slave PLL.	Commun. Nonlinear Sci. Numer. Simul.	2014	DBLP DOI BibTeX RDF
26	Muhammad Kalimuddin Khan, Kenneth Mulvaney	A novel PLL lock and out-of-lock detect scheme based on a feedback sampling of PLL.	CSNDSP	2014	DBLP DOI BibTeX RDF
26	Gerardo Escobar, Carl Ngai Man Ho, Sami Pettersson, Manuel J. Lopez-Sanchez, Andres A. Valdez-Fernandez	Cascade three-phase PLL for unbalance and harmonic distortion operation (CSRF-PLL).	IECON	2014	DBLP DOI BibTeX RDF
26	Liming Xiu, Chen-Wei Huang, Ping Gui	A comparative study between Fractional-N PLL and Flying-Adder PLL.	ISCAS	2010	DBLP DOI BibTeX RDF
26	Yang Han 0002, Lin Xu, Muhammad Mansoor Khan, Gang Yao, Lidan Zhou, Chen Chen 0020	A novel synchronization scheme for grid-connected converters by using adaptive linear optimal filter based PLL (ALOF-PLL).	Simul. Model. Pract. Theory	2009	DBLP DOI BibTeX RDF
26	Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera	A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL.	IEICE Trans. Electron.	2005	DBLP DOI BibTeX RDF
24	Sinisa Milicevic, Leonard MacEachern	A phase-frequency detector and a charge pump design for PLL applications.	ISCAS	2008	DBLP DOI BibTeX RDF
24	Xu Yi, Hongbing Qiu	Modeling and Simulation of the Locking Process of a 4th Order Microwave Frequency-Hopping PLL Synthesizer.	CSSE (2)	2008	DBLP DOI BibTeX RDF
24	Stephen K. Sunter, Aubin Roy	Purely Digital BIST for Any PLL or DLL.	ETS	2007	DBLP DOI BibTeX RDF
24	Chin-Cheng Kuo, Chien-Nan Jimmy Liu	On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
24	Kazuhiko Miki, David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill, Yuichi Goto	A new test and characterization scheme for 10+ GHz low jitter wide band PLL.	ASP-DAC	2006	DBLP DOI BibTeX RDF
24	Ting Mei, Jaijeet S. Roychowdhury	PPV-HB: harmonic balance for oscillator/PLL phase macromodels.	ICCAD	2006	DBLP DOI BibTeX RDF
24	Gordon Allan, John Knight	A compact 190µW PLL for clock control and distribution in ultra-large scale ICs.	ISCAS	2006	DBLP DOI BibTeX RDF
24	Mohsen Saffari, Seyed Mojtaba Atarodi, Armin Tajalli	A 1/4 rate linear phase detector for PLL-based CDR circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
24	Alexis W. Krieger, John C. Salmon	Three-Phase PLL Synchronization with Gated Error Control.	CCECE	2006	DBLP DOI BibTeX RDF
24	Farhad Zarkeshvari, Peter Noel, Tad A. Kwasniewski	PLL-Based Fractional-N Frequency Synthesizers.	IWSOC	2005	DBLP DOI BibTeX RDF
24	Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber	FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T.	FPL	2004	DBLP DOI BibTeX RDF
24	Chin-Cheng Tsai, Chung-Len Lee	An On-Chip Jitter Measurement Circuit for the PLL.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
24	Jayasanker Jayabalan, Kiang Goh Chee, Ban-Leong Ooi, Mook Seng Leong, Mahadevan K. Iyer, Andrew A. O. Tay	PLL Based High Speed Functional Testing.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
24	Rola A. Baki, Mourad N. El-Gamal	A new CMOS charge pump for low-voltage (1V) high-speed PLL applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
24	Mathieu Renaud, Yvon Savaria	A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
24	Michael H. Perrott	Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
24	Wataru Ohno, Tetsuro Endo	Property of the double heteroclinic tangency crisis in a forced PLL equation.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
24	Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung	A low-power high driving ability voltage control oscillator used in PLL.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
24	Hyuk-Jun Sung, Kwang Sub Yoon	A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
24	Amr N. Hafez, Mohamed I. Elmasry	A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
22	Cui-Xia Li, Wei-Ming Liu 0003, Yi Tang	A New 12-channel Hand-Held GPS Accelerator Design.	NCM	2009	DBLP DOI BibTeX RDF	GPS accelerator, DCO, Correlator, PLL, LUT
22	Calvin Plett, Robson Nunes de Lima	Low-power CMOS transceivers with on-chip antennas for short-range radio-frequency communication.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS transceiver, injection locked, integrated antenna, medical sensor readout, PLL
22	Jose Marcelo Lima Duarte, Francisco das Chagas Mota, Manoel J. M. Carvalho	Digital PM demodulator for brazilian data collecting system.	SBCCI	2007	DBLP DOI BibTeX RDF	BDCS, control system theory, FPGA, PLL, phase locked loop
22	Xiaolue Lai, Jaijeet S. Roychowdhury	A multilevel technique for robust and efficient extraction of phase macromodels of digitally controlled oscillators.	DAC	2006	DBLP DOI BibTeX RDF	DCO, PPV, simulation, PLL, macromodel, VCO, DPLL
22	Domine Leenaerts	Low power RF IC design for wireless communication.	ISLPED	2003	DBLP DOI BibTeX RDF	low power, wireless communication, technology, PLL, RF, VCO, transceivers, LNA
22	Rahul Bhattacharya, Santosh Biswas, Siddhartha Mukhopadhyay	FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	ams testing, concurrent test development, behavioral modeling
22	Taisuke Sato	Logic-Based Probabilistic Modeling.	WoLLIC	2009	DBLP DOI BibTeX RDF
22	Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi	An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
22	Chin-Sean Sum, Ryuhei Funada, Junyi Wang, Tuncer Baykas, Ming Lei, Yoshinori Nishiguchi, Ryota Kimura, Yozo Shoji, Hiroshi Harada, Shuzo Kato	Adjacent channel interference resistance of a multi-Gbps millimeter-wave WPAN system.	PIMRC	2008	DBLP DOI BibTeX RDF
22	Yin Wang, Ke Gong, Zhaowu Chen	Theoretical Analysis of Performance Degradation Due to Phase Noise and I/Q Imbalance in MQAM-OFDM Systems.	ICC	2008	DBLP DOI BibTeX RDF
22	Martin Kumm, M. Shahab Sanjari	Digital hilbert transformers for FPGA-based phase-locked loops.	FPL	2008	DBLP DOI BibTeX RDF
22	Daisuke Atuti, Kazuki Nakada, Takashi Morie	CMOS pulse-modulation circuit implementation of phase-locked loop neural networks.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick D. Wolf	Phase-Noise Driven System Design of Fractional-N Frequency Synthesizers and Validation With Measured Results.	ISVLSI	2007	DBLP DOI BibTeX RDF
22	Sayed Hafizur Rahman, Asif Iqbal Ahmed, Otmane Aït Mohamed	Analysis and Performance Evaluation of a Digital Carrier Synchronizer for Modem Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Christian Wicpalek, Thomas Mayer 0003, Linus Maurer, U. Vollenbruch, Tindaro Pittorino, Andreas Springer	Analysis of Spurious Emission and In-Band Phase Noise of an All Digital Phase Locked Loop for RF Synthesis using a Frequency Discriminator.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Dominic DiClemente, Fei Yuan 0005	Current-Mode Phase-Locked Loops with Low Supply Voltage Sensitivity.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Maneesha Yellepeddi, Kartikeya Mayaram	Issues in the Design and Simulation of a MEMS VCO based Phase-Locked Loop.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Himanshu Arora, Nikolaus Klemmer, Patrick D. Wolf	A 900 MHz ISM band mash-12 fractional-n frequency synthesizer for 5-Mbps data transmission.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	RMS phase error, delta-sigma, fractional-N, gain mismatch, phase frequency detector, spurs, thermal noise, VCO, phase noise, frequency synthesizer, charge pump
22	Henry H. Y. Chan, Zeljko Zilic	Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops.	DAC	2007	DBLP DOI BibTeX RDF
22	Régis Roubadia, Sami Ajram, Guy Cathébras	Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs.	PATMOS	2006	DBLP DOI BibTeX RDF
22	Benjamin Nicolle, William Tatinian, Jean Oudinot, Gilles Jacquemod	Hierarchical Modeling of a Fractional Phase Locked Loop.	PATMOS	2006	DBLP DOI BibTeX RDF
22	Shalabh Goyal, Abhijit Chatterjee, Mike Atia	Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production Test.	ETS	2006	DBLP DOI BibTeX RDF
22	Wei-Tsen Lin, Dah-Chung Chang	The extended Kalman filtering algorithm for carrier synchronization and the implementation.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Haiyong Wang, Guoliang Shou, Nanjian Wu	An adaptive frequency synthesizer architecture reducing reference sidebands.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Vincent Lagareste, Franck Badets, Pierre Melchior, Jean-Baptiste Bégueret, Yann Deval, Alain Oustaloup, Didier Belot	Phase locked loop robustness improvement using non integer order loop filter.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Alexey Teplinsky, Raymond Flynn, Orla Feely	Limit cycles in bang-bang phase-locked loops.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Sangho Shin, Kwyro Lee, Sung-Mo Kang	Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Cornelis Jan Kikkert	Two Novel Phase-Frequency Detectors.	APCCAS	2006	DBLP DOI BibTeX RDF
22	Min Chu, David J. Allstot	Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimization.	ASP-DAC	2005	DBLP DOI BibTeX RDF
22	Wei-Ta Chen, Jen-Chien Hsu, Hong-Wen Lune, Chauchin Su	A spread spectrum clock generator for SATA-II.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
22	Aditya Sankar Medury, Ingvar Carlson, Atila Alvandpour, John Stensby	Structural Fault Diagnosis in Charge-Pump Based Phase-Locked Loops.	VLSI Design	2005	DBLP DOI BibTeX RDF
22	Viktor Fischer, Milos Drutarovský, Martin Simka, Nathalie Bochard	High Performance True Random Number Generator in Altera Stratix FPLDs.	FPL	2004	DBLP DOI BibTeX RDF
22	José Manuel Cazeaux, Martin Omaña 0001, Cecilia Metra	Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop.	IOLTS	2004	DBLP DOI BibTeX RDF
22	José Pineda de Gyvez, Guido Gronthoud, Cristiano Cenci, Martin Posch, Thomas Burger, Manfred Koller	Power Supply Ramping for Quasi-static Testing of PLLs.	ITC	2004	DBLP DOI BibTeX RDF
22	Hüseyin Aniktar, Yalçin Tanik	New Receiver Structures for Subcarrier Synchronization in OFDM Systems over Frequency-Selective Channels.	ISCC	2003	DBLP DOI BibTeX RDF
22	N. Christoffers, Rainer Kokozinski, Stephan Kolnsberg, Bedrich J. Hosticka	High loop-filter-order ΣΔ-fractional-n frequency synthesizers for use in frequency-hopping-spread-spectrum communication-systems.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
22	Sara Escalera, Carlos M. Domínguez-Matas, José M. García-González, Oscar Guerra, Ángel Rodríguez-Vázquez	On the development of a MODEM for data transmission and control of electrical household appliances using the low-voltage power-line.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
22	Marco Balsi, Francesco Centurelli, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti	An accurate behavioral model of phase detectors for clock recovery circuits.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
22	Mieczyslaw Jessa, Marcin Walentynowicz	Discrete-time phase-locked loop as a source of random sequences with different distributions.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
22	Youcef Fouzar, Yvon Savaria, Mohamad Sawan	A CMOS phase-locked loop with an auto-calibrated VCO.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
22	Ranjit Yashwante, Bhalchandra Jahagirdar	IEEE 1394a_2000 Physical Layer ASIC.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
22	Viktor Fischer, Milos Drutarovský	True Random Number Generator Embedded in Reconfigurable Hardware.	CHES	2002	DBLP DOI BibTeX RDF
22	Fulvio Spagna	Phase Locked Loop Using Delay Compensation Techniques.	ISCC	2000	DBLP DOI BibTeX RDF	timing recovery, stability analysis, Phase Locked Loop
22	Dirk Niggemeyer, M. Rüffer	Parametric Built-In Self-Test of VLSI Systems.	DATE	1999	DBLP DOI BibTeX RDF
22	Won Hyo Lee, Jun Dong Cho, Sung Dae Lee	A High Speed and Low Power Phase-Frequency Detector and Charge - pump.	ASP-DAC	1999	DBLP DOI BibTeX RDF
22	Amr N. Hafez, Mohamed I. Elmasry	A low power monolithic subsampled phase-locked loop architecture for wireless transceivers.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
22	Thomas Toifl, Paulo Moreira	A radiation-hard 80 MHz phase locked loop for clock and data recovery.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
22	Abdelohahab Djemouai, Mohamad Sawan, Mustapha Slamani	A 200 MHz frequency-locked loop based on new frequency-to-voltage converters approach.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
22	Amr M. Fahim, Mohamed I. Elmasry	A low-power CMOS frequency synthesizer design methodology for wireless applications.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
22	Sang-Soo Lee, Carlos A. Laber	A 3.5 in 230 Mbytes read-channel chip set for magneto-optical disk drives.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
21	Youhui Xie, Wenjin Dai, Yongtao Dai	A Method of Phase Tracking Based on Neural Network.	JCAI	2009	DBLP DOI BibTeX RDF	Phase tracking, Artificial neural network(ANN), RBF network, Phase Locked Loop(PLL), BP network
21	Akhil Garg 0001, Prashant Dubey	On Chip Jitter Measurement through a High Accuracy TDC.	ISQED	2008	DBLP DOI BibTeX RDF	Jitter Measurement, PLL Test
21	JinKyung Kim, Sung-Kyu Jung, Ji-Hoon Jung, Sang-Kyung Sung, Kang-Yoon Lee, Chul Nam, Bong Hyuk Park, Sang-Sung Choi	A Design of the Frequency Synthesizer for UWB Application in 0.13 µm RF CMOS Process.	DELTA	2008	DBLP DOI BibTeX RDF	single-sideband (SSB) mixer, UWB, phase-locked loop (PLL), Frequency Synthesizer
13	Suvom Roy, Souvik Das, Bhim Singh 0001, Bijaya Ketan Panigrahi	HT-PLL-Based Seamless Transition Strategy for DFIG With Power Quality Enhancement Through Fractional-Order Adaptive Filter.	IEEE Trans. Ind. Electron.	2024	DBLP DOI BibTeX RDF
13	Bin Guo 0003, Xin Zhang 0034, Hao Ma 0002, Yongheng Yang, Xiaoqiang Wang 0004, Qingxin Tian, Sicong Jin	A Series Impedance Reshaping Control Method Considering PLL Dynamics for Grid-Connected Inverters Under Weak Grid Conditions.	IEEE Trans. Ind. Electron.	2024	DBLP DOI BibTeX RDF
13	Juyeop Kim, Yongwoo Jo, Hangi Park, Taeho Seong, Younghyun Lim, Jaehyouk Choi	A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
13	Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua	Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
13	Saurabh Kumar, Yatendra Kumar Singh	A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique.	Integr.	2024	DBLP DOI BibTeX RDF
13	Mohamed Mellouli, Mahmoud Hamouda, Hafiz Ahmed, Jaleleddine Ben Hadj Slama, Kamal Al-Haddad	A Grid Synchronization PLL With Accurate Extraction Technique of Positive/Negative Sequences and DC-Offset Under Frequency Drift.	IEEE Trans. Instrum. Meas.	2024	DBLP DOI BibTeX RDF
13	Zeeshan Ali, Mostafa Elsayed, Girish Tiwari, Meraj Ahmad, Julien Le Kernec, Hadi Heidari, Shalabh Gupta	Impact of Receiver Thermal Noise and PLL RMS Jitter in Radar Measurements.	IEEE Trans. Instrum. Meas.	2024	DBLP DOI BibTeX RDF
13	Suvom Roy, Souvik Das, Bhim Singh 0001, Bijaya Ketan Panigrahi	AALMS Current Control and FC Type-2 PLL Aided Synchronization of DFIG-BES Microgrid.	IEEE Trans. Ind. Informatics	2024	DBLP DOI BibTeX RDF
13	Bowen Wang, Cong Ding 0004, Yunzhao Nie, Woogeun Rhee, Zhihua Wang 0001	A 0.14-nJ/b 200-Mb/s 2.7-3.5-GHz Quasi-Balanced FSK Transceiver With PLL-Based Modulation and Sideband Energy Detection.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
13	Dipan Kar, Soumen Mohapatra, Md. Aminul Hoque, Deukhyoun Heo	A 14 GHz Integer-N Sub-Sampling PLL With RMS-Jitter of 85.4 fs Occupying an Ultra Low Area of 0.0918 mm2.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
13	A. Ghaemnia, M. B. Ghaznavi-Ghoushchi	QD-PFD: Quasi Dynamic Dead-Zone/Blind-Zone Free PFD With 23 nW-38 μW for 2 MHz-5 GHz Range and 150-ns Settling Time PLL Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
13	Depeng Sun, Linguo Huang, Rong Zhou, Feng Bu, Lisheng Chen, Xiaoteng Zhao, Ruixue Ding, Shubin Liu, Zhangming Zhu	A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fsrms Integrated Jitter and -250.8-dB FOMPLL.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
13	Ke Jia, Xinying Jiang, Yang Zhang, Haoyuan Wang, Qian Liu, Tianshu Bi	Fault Dynamic Response Difference-Based PLL Controller Parameter Identification of IIRESs.	IEEE Trans. Smart Grid	2024	DBLP DOI BibTeX RDF
13	Jianguo Hu, Renfei Zou, Yao Yao, Jiajun He, Deming Wang	A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
13	Yi Zhou, Zhouchen Deng, Shi Chen, Yiwei Qiu, Tianlei Zang, Buxiang Zhou	A Pure Integral-Type PLL with a Damping Branch to Enhance the Stability of Grid-Tied Inverter under Weak Grids.	CoRR	2024	DBLP DOI BibTeX RDF
13	Fei Tong, Jingtao Liu, Changzhan Gu, Junfa Mao	Displacement Motion Sensing with Asynchronous Bandpass Sampling Using a Single-Channel Dual-PLL SSB low-IF Doppler Radar.	WiSNeT	2024	DBLP DOI BibTeX RDF
13	Yuhwan Shin, Junseok Lee, Juyeop Kim, Yongwoo Jo, Jaehyouk Choi	10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique.	ISSCC	2024	DBLP DOI BibTeX RDF