| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Shijie Zhou 0001, Rajgopal Kannan, Viktor K. Prasanna |
Accelerating low rank matrix completion on FPGA.  |
ReConFig  |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | |
International Conference on ReConFigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, December 4-6, 2017 |
ReConFig |
2017 |
DBLP BibTeX RDF |
|
| 1 | Ian J. Barge, Cristinel Ababei |
H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Engel 0003, Andreas Koch 0001 |
Energy-efficient reconfiguration of flash-based FPGAs in heterogeneous wireless sensor nodes. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Siyuan Xu, Jianqi Chen, Benjamin Carrión Schäfer |
HW/SW co-design experimental framework using configurable SoCs. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew Boutros, Brett Grady, Mustafa Abbas, Paul Chow |
Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Pongstorn Maidee, Alireza Kaviani, Kevin Zeng |
LinkBlaze: Efficient global data movement for FPGAs. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Michele Paolino, Sebastien Pinneterre, Daniel Raho |
FPGA virtualization with accelerators overcommitment for network function virtualization. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj |
Side-channel resistant soft core processor for lightweight block ciphers. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad K. A. Hamdan, Diane T. Rover |
VHDL generator for a high performance convolutional neural network FPGA-based accelerator. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Paul Rogers, Rajesh Kavasseri, Scott C. Smith |
An FPGA-in-the-loop approach for HDL motor controller verification. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Diogo Parrinha, Ricardo Chaves |
Flexible and low-cost HSM based on non-volatile FPGAs. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Metzli Ramirez-Martinez, Francisco Sanchez-Fernandez, Philippe Brunet, Sidi Mohammed Senouci, El-Bay Bourennane |
Dynamic management of a partial reconfigurable hardware architecture for pedestrian detection in regions of interest. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Young H. Cho, Siddharth S. Bhargav |
Fine-grained on-line power monitoring for soft microprocessor based system-on-chip. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan Moritz Joseph, Morten Mey, Kristian Ehlers, Christopher Blochwitz, Tobias Winker, Thilo Pionteck |
Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Benedikt Janßen, Fatih Korkmaz, Halil Derya, Michael Hübner 0001, Mário Lopes Ferreira, João Canas Ferreira |
Towards a type 0 hypervisor for dynamic reconfigurable systems. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuncay Soylu, Oguzhan Erdem, Aydin Carus, Edip S. Güner |
Simple CART based real-time traffic classification engine on FPGAs. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sizhuo Zhang, Hari Angepat, Derek Chiou |
HGum: Messaging framework for hardware accelerators. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Usman Tariq, Umer I. Cheema, Fahad Saeed |
Power-efficient and highly scalable parallel graph sampling using FPGAs. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Claudio Rubattu, Francesca Palumbo, Maxime Pelcat |
Adaptive software-augmented hardware reconfiguration with dataflow design automation. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Lukas Sommer, Julian Oppermann, Jaco A. Hofmann, Andreas Koch 0001 |
Synthesis of interleaved multithreaded accelerators from OpenMP loops. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Salvador Ibarra-Delgado, Remberto Sandoval-Arechiga, María Brox, Manuel A. Ortiz |
Software defined network controller: A neat solution administration for reconfigurable multi-core NoC. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Panasayya Yalla, Jens-Peter Kaps |
Evaluation of the CAESAR hardware API for lightweight implementations. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich |
A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Christian Plessi |
Keynote 2 - FPGA-accelerated high-performance computing - Close to breakthrough or pipedream? |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jose Fernando Zazo, Jorge E. López de Vergara |
An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Girish Deshpande, Dinesh K. Bhatia |
Microchannels for thermal management in FPGAs. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ievgen Kabin, Zoya Dyka, Dan Kreiser, Peter Langendörfer |
Horizontal address-bit DPA against montgomery kP implementation. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Tobias Drewes, Jan Moritz Joseph, Thilo Pionteck |
An FPGA-based prototyping framework for Networks-on-Chip. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Rasha Karakchi, Lothrop O. Richards, Jason D. Bakos |
A Dynamically Reconfigurable Automata Processor Overlay. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Joao Lopes, Diogo Sousa 0002, João Canas Ferreira |
Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Umer Farooq 0001, Habib Mehrez, Muhammad Khurram Bhatti |
Comparison of direct and switch-based inter-FPGA routing interconnect for multi-FPGA systems. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Lucas B. da Silva, Danilo Damião Almeida, José Augusto Miranda Nacif, Ismael Sanchez-Osorio, Carlos A. Hernandez-Martinez, Ricardo Ferreira 0001 |
Exploring the dynamics of large-scale gene regulatory networks using hardware acceleration on a heterogeneous CPU-FPGA platform. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | David C. Keezer, Jingchi Yang |
Biologically inspired hierarchical structure for self-repairing FPGAs. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | César Torres-Huitzil, Bernard Girau |
Fault tolerance in neural networks: Neural design and hardware implementation. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hanqing Zeng, Chi Zhang 0022, Viktor K. Prasanna |
Fast generation of high throughput customized deep learning accelerators on FPGAs. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Siavash Rezaei, César-Alejandro Hernández-Calderón, Saeed Mirzamohammadi, Eli Bozorgzadeh, Alexander V. Veidenbaum, Alex Nicolau, Michael J. Prather |
Data-rate-aware FPGA-based acceleration framework for streaming applications. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaco A. Hofmann, Jens Korinth, Andreas Koch 0001 |
A scalable latency-insensitive architecture for FPGA-accelerated semi-global matching in stereo vision applications. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Asgar Sohanghpurwala, Peter M. Athanas |
An effective probability distribution SAT solver on reconfigurable hardware. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ho-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma 0001, Manish Kumar Jaiswal, Sam M. H. Ho, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So |
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Benjamin R. Buhrow, William J. Goetzinger, Barry K. Gilbert |
1 Tb/s anti-replay protection with 20-port on-chip RAM memory in FPGAs. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | João Canas Ferreira, Jose Fonseca |
An FPGA implementation of a long short-term memory neural network. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Tobias Lieske, Marc Reichenbach, Burkhard Ringlein, Dietmar Fey |
Dataflow optimization for programmable embedded image preprocessing accelerators. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura |
FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan Moritz Joseph, Tobias Winker, Kristian Ehlers, Christopher Blochwitz, Thilo Pionteck |
Hardware-accelerated pose estimation for embedded systems using Vivado HLS. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas B. Preußer, Markus Krause |
Survey on and re-evaluation of wide adder architectures on FPGAs. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Farnoud Farahmand, Ekawat Homsirikamol, Kris Gaj |
A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Becher, Stefan Wildermann, Moritz Mühlenthaler, Jürgen Teich |
ReOrder: Runtime datapath generation for high-throughput multi-stream processing. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Atil U. Ay, Erdinç Öztürk, Francisco Rodríguez-Henríquez, Erkay Savas |
Design and implementation of a constant-time FPGA accelerator for fast elliptic curve cryptography. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Andres Jacoby, Daniel Llamocca |
Dual fixed-point CORDIC processor: Architecture and FPGA implementation. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Robért Glein, Florian Rittner, Albert Heuberger |
Adaptive single-event effect mitigation for dependable processing systems. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sen Ma, David Andrews 0001, Shanyuan Gao, Jaime Cummins |
Breeze computing: A just in time (JIT) approach for virtualizing FPGAs in the cloud. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Graham Schelle |
Keynote 1 - Growing the ReConFig community through python, zynq and hardware overlays. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Gundolf Kiefer, Matthias Vahl, Julian Sarcher, Michael Schaeferling |
A configurable architecture for the generalized hough transform applied to the analysis of huge aerial images and to traffic sign detection. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jose Fernando Zazo, Sergio López-Buedo, Gustavo Sutter, Javier Aracil 0001 |
Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Qianqiao Chen, Vaibhawa Mishra, Georgios Zervas |
Reconfigurable computing for network function virtualization: A protocol independent switch. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas B. Preußer, Martin Zabel, Patrick Lehmann 0001, Rainer G. Spallek |
The portable open-source IP core and utility library PoC. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Bernhard Jungk, Marc Stöttinger |
Hobbit - Smaller but faster than a dwarf: Revisiting lightweight SHA-3 FPGA implementations. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Matej Bartik, Sven Ubik, Pavel Kubalík |
A novel and efficient method to initialize FPGA embedded memory content in asymptotically constant time. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Steffen Vaas, Marc Reichenbach, Ulrich Margull, Dietmar Fey |
The R2-D2 toolchain - Automated porting of safety-critical applications to FPGAs. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Lukas Johannes Jung, Christian Hochberger |
Optimal processor interface for CGRA-based accelerators implemented on FPGAs. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Thorbjörn Posewsky, Daniel Ziener |
Efficient deep neural network acceleration through FPGA-based batch processing. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Tobias Kalb, Diana Göhringer |
Enabling dynamic and partial reconfiguration in Xilinx SDSoC. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Vaibhawa Mishra, Qianqiao Chen, Georgios Zervas |
REoN: A protocol for reliable software-defined FPGA partial reconfiguration over network. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Karam, Tamzidul Hoque, Sandip Ray, Mark M. Tehranipoor, Swarup Bhunia |
Technical demonstration session: Software toolflow for FPGA bitstream obfuscation. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Becher, Jutta Pirkl, Achim Herrmann, Jürgen Teich, Stefan Wildermann |
Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Habib ul Hasan Khan, Diana Göhringer |
FPGA debugging by a device start and stop approach. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sebastian Meisner, Marco Platzner |
Thread shadowing: On the effectiveness of error detection at the hardware thread level. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Di Febbo, Stefano Mattoccia, Carlo Dal Mutto |
Real-time image distortion correction: Analysis and evaluation of FPGA-compatible algorithms. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Karam, Tamzidul Hoque, Sandip Ray, Mark M. Tehranipoor, Swarup Bhunia |
Robust bitstream protection in FPGA-based systems through low-overhead obfuscation. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jens Rettkowski, Konstantin Friesen, Diana Göhringer |
RePaBit: Automated generation of relocatable partial bitstreams for Xilinx Zynq FPGAs. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kledermon Garcia, Duarte Lopes de Oliveira, Roberto d'Amore, Lester de Abreu Faria, Joao Luis V. Oliveira |
FPGA implementation of optimized XBM specifications by transformation for AFSMs. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Michail S. Vavouras, Christos-Savvas Bouganis |
Area-driven partial reconfiguration for SEU mitigation on SRAM-based FPGAs. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Thaddeus Koehn, Peter Athanas |
Automating structured matrix-matrix multiplication for stream processing. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings |
Packing a modern Xilinx FPGA using RapidSmith. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Wen Wang 0007, Jakub Szefer, Ruben Niederhagen |
Solving large systems of linear equations over GF(2) on FPGAs. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sam M. H. Ho, Maolin Wang, Ho-Cheung Ng, Hayden Kwok-Hay So |
Towards FPGA-assisted spark: An SVM training acceleration case study. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Skip Booth |
Keynote 2 - FPGAs in the datacenter - A software view. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Meloni, Gianfranco Deriu, Francesco Conti 0001, Igor Loi, Luigi Raffo, Luca Benini |
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | N. Nila-Olmedo, Fortino Mendoza-Mondragón, Alejandro Espinosa-Calderon, Moreno |
ARM+FPGA platform to manage solid-state-smart transformer in smart grid application. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Khaled E. Ahmed, Mohamed R. M. Rizk, Mohammed M. Farag |
Overloaded CDMA interconnect for Network-on-Chip (OCNoC). |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ernst Joachim Houtgast, Vlad Mihai Sima, Giacomo Marchiori, Koen Bertels, Zaid Al-Ars |
Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara |
FPGA-based encrypted network traffic identification at 100 Gbit/s. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura |
An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Pham Nam Khanh, Khin Mi Mi Aung, Akash Kumar 0001 |
Automatic framework to generate reconfigurable accelerators for option pricing applications. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Akihiko Hamada, Hiroki Matsutani |
Design and implementation of hardware cache mechanism and NIC for column-oriented databases. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Rasha Karakchi, Jordan A. Bradshaw, Jason D. Bakos |
High-level synthesis of a genomic database search engine. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Paul Rogers, Rajesh Kavasseri, Scott C. Smith |
An FPGA-based design for joint control and monitoring of permanent magnet synchronous motors. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter M. Athanas, René Cumplido, Claudia Feregrino, Ron Sass (eds.) |
International Conference on ReConFigurable Computing and FPGAs, ReConFig 2016, Cancun, Mexico, November 30 - Dec. 2, 2016 |
ReConFig |
2016 |
DBLP BibTeX RDF |
|
| 1 | Florian Rittner, Robért Glein, Albert Heuberger |
Detection and Isolation of permanent faults in FPGAs with remote access. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Nobuyuki Yahiro, Bo Liu 0031, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen 0002 |
A multi-functional memory unit with PLA-based reconfigurable decoder. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Tiziana Fanni, Luigi Raffo |
Coarse grain reconfiguration: Power estimation and management flow for hybrid gated systems. |
ReConFig |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Vincent Mirian, Paul Chow |
Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs. |
ReConFig |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Joshua S. Monson, Brad L. Hutchings |
Using shadow pointers to trace C pointer values in FPGA circuits. |
ReConFig |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Poona Bahrebar, Dirk Stroobandt |
Design and exploration of routing methods for NoC-based multicore systems. |
ReConFig |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Gordon Ghiu |
Keynote 2 - Towards datacenter computing with FPGAs. |
ReConFig |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Benjamin Buhrow, Karl E. Fritz, Barry K. Gilbert, Erik S. Daniel |
A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols. |
ReConFig |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Jean-Pierre David |
Low latency solver for linear equation systems in floating point arithmetic. |
ReConFig |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Armando Astarloa, Naiara Moreira, Unai Bidarte, Marcelo Urbina, David Modrono |
FPGA based nodes for sub-microsecond synchronization of cyber-physical production systems on high availability ring networks. |
ReConFig |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Omar W. Ibraheem, Arif Irwansyah, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert 0001 |
A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms. |
ReConFig |
2015 |
DBLP DOI BibTeX RDF |
|
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