Search results for "SRT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
24	Paolo Montuschi, Luigi Ciminiera	Reducing Iteration Time When Result Digit is Zero for Radix 2 SRT Division and Square Root with Redundant Remainders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF
24	David M. Mandelbaum	Some Results on a SRT Type Division Scheme.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF
24	Ted E. Williams, Mark A. Horowitz	A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages.	IEEE Symposium on Computer Arithmetic	1991	DBLP DOI BibTeX RDF
24	George S. Taylor	Radix 16 SRT dividers with overlapped quotient selection stages: A 225 nanosecond double precision divider for the S-1 Mark IIB.	IEEE Symposium on Computer Arithmetic	1985	DBLP DOI BibTeX RDF
24	Mehdi Kargahi, Ali Movaghar 0001	A Method for Performance Analysis of Earliest-Deadline-First Scheduling Policy.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	soft real-time (SRT) systems, performance modeling, multiprocessor systems, earliest-deadline-first (EDF), analytical methods, approximation methods
24	Behrooz Parhami	Tight Upper Bounds on the Minimum Precision Required of the Divisor and the Partial Remainder in High-Radix Division.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	digit-selector PLA, high-radix division, p-d plot, quotient digit selection, SRT division, Digit-recurrence division
24	Takafumi Aoki, Kimihiko Nakazawa, Tatsuo Higuchi 0001	High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables.	ISMVL	2000	DBLP DOI BibTeX RDF	Quotient digit selection tables, High-radix division, VLSI, Computer arithmetic, Signed-digit number systems, SRT division
24	Eric M. Schwarz, Michael J. Flynn	Parallel High-Radix Nonrestoring Division.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	parallel high-radix nonrestoring division, quotient estimation, generalized partial remainder, carry propagate adder, high-radix division, logic design, logic design, latency, computer arithmetic, digital arithmetic, combinatorial algorithm, SRT division
16	Yang Xu 0016, Shengqun Tang, Youwei Xu, Ruliang Xiao, Lina Fang	Discovering Web Services Based on Match History.	AWIC	2007	DBLP DOI BibTeX RDF
16	Neil Burgess, Chris N. Hinds	Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
16	Luigi Freda, Francesco Loiudice, Giuseppe Oriolo	A Randomized Method for Integrated Exploration.	IROS	2006	DBLP DOI BibTeX RDF
16	Neil Burgess	Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
16	ZhiHui Lv 0002, YiPing Zhong, Weiming Fu, Shiyong Zhang	GOD Queuing : A Novel Grid-based Resource Co-allocation Scheme in Distributed Multimedia System.	CIT	2005	DBLP DOI BibTeX RDF
16	Woo-Chan Park, Tack-Don Han, Sung-Bong Yang	A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
16	Horng-Shyang Liao, Jung-Hong Chuang, Cheng-Chung Lin	Efficient rendering of dynamic clouds.	VRCAI	2004	DBLP DOI BibTeX RDF	cloud simulation, dynamic clouds rendering
16	Jen-Shiun Chiang, Min-Shiou Tsai	A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	floating-point division, new Svoboda-Tung division, radix-4, Svoboda-Tung division, computer arithmetic, prescaling, signed digit number system
16	David W. Matula, Alex Fit-Florea	Prescaled Integer Division.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
16	Guenter Gerwig, Holger Wetter, Eric M. Schwarz, Juergen Haess	High Performance Floating-Point Unit with 116 Bit Wide Divider.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
16	Xiaojun Wang, Brent E. Nelson	Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs.	FCCM	2003	DBLP DOI BibTeX RDF
16	Herbert A. Meyer, Michael Hildebrandt	Towards time design: pacing of hypertext navigation by system response times.	CHI Extended Abstracts	2002	DBLP DOI BibTeX RDF	time design, usability, hypertext, system response time
16	Luiz Maltar, Felipe M. G. França, Vladimir Castro Alves, Cláudio L. Amorim	An FPGA-Based Fan Beam Image Reconstruction Module.	FCCM	1999	DBLP DOI BibTeX RDF
16	Christoph Kern, Tarik Ono-Tesfaye, Mark R. Greenstreet	A Light-Weight Framework for Hardware Verification.	TACAS	1999	DBLP DOI BibTeX RDF
16	David Ingram	Soft Real Time Scheduling for General Purpose Client-Server Systems.	Workshop on Hot Topics in Operating Systems	1999	DBLP DOI BibTeX RDF	Real Time, Operating Systems, Linux, Client-Server
16	Gensoh Matsubara, Nobuhiro Ide	A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit.	ASYNC	1997	DBLP DOI BibTeX RDF	floating point, division, square root, self-timed
16	Jean-Paul Theis, Harald Schlimper	Ultrafast compact CMOS dividers.	ICPADS	1997	DBLP DOI BibTeX RDF	CMOS dividers, ultrafast, restoring division, floating-point division, 0.3 mum, parallelization, timing, layout, compact, dividing circuits, divider circuits
16	J. Arjun Prabhu, Gregory B. Zyner	167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF
16	Marianne E. Louie, Milos D. Ercegovac	On digit-recurrence division implementations for field programmable gate arrays.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
16	Jordi Cortadella, Tomás Lang	Division with speculation of quotient digits.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF