Search results for "SoPC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Amin Farmahini Farahani, Sied Mehdi Fakhraie, Saeed Safari	SOPC-Based Architecture for Discrete Particle Swarm Optimization.	ICECS	2007	DBLP DOI BibTeX RDF
23	Pierre Vanhauwaert, Régis Leveugle, Philippe Roche	A Flexible SoPC-based Fault Injection Environment.	DDECS	2006	DBLP DOI BibTeX RDF
23	Mehdi Salmani Jelodar, Mehdi Kamal, Sied Mehdi Fakhraie, Majid Nili Ahmadabadi	SOPC-Based Parallel Genetic Algorithm.	IEEE Congress on Evolutionary Computation	2006	DBLP DOI BibTeX RDF
23	Stéphane Mancini, Michel Desvignes	Ray Casting on a SOPC : Algorithm and Memory Hierarchy Trade-Off.	CIT	2006	DBLP DOI BibTeX RDF
23	Thomas Ea, Frédéric Amiel, Alicja Michalowska, Florence Rossant, Amara Amara	Contribution of Custom Instructions on SoPC for iris recognition application.	ICECS	2006	DBLP DOI BibTeX RDF
23	Marta Portela-García, Luca Sterpone, Celia López-Ongil, Matteo Sonza Reorda, Massimo Violante	A Fault Injection Environment for SoPC's Embedded Microprocessors.	LATW	2006	DBLP BibTeX RDF
23	Fangjun Jian, Jizhong Han, Chengde Han, Qin Zhang, Xuhui Liu	Design and Implementation of SoPC with Multi-Bus on a Chip.	ESA	2006	DBLP BibTeX RDF
23	Armando Astarloa, Unai Bidarte, Jesús Lázaro 0001, Aitzol Zuloaga, Jagoba Arias	Multiprocessor SoPC-Core for FAT volume computation.	Microprocess. Microsystems	2005	DBLP DOI BibTeX RDF
23	John McAllister, Roger F. Woods, Darren Gerard Reilly, Scott Fischaber, R. Hasson	Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms.	SAMOS	2005	DBLP DOI BibTeX RDF
23	Jing Ma 0006, Xinming Huang 0001	A SoPC Architecture of MIMO Sphere Decoder for Mobile Communications.	ERSA	2005	DBLP BibTeX RDF
23	Stefano Zammattio	SOPC Builder, a Novel Design Methodology for IP Integration.	SoC	2005	DBLP DOI BibTeX RDF
23	Christophe Wolinski, Krzysztof Kuchcinski, Maya B. Gokhale	A constraints programming approach to communication scheduling on SoPC architectures.	FPGA	2004	DBLP DOI BibTeX RDF
23	Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha	An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs.	DSD	2003	DBLP DOI BibTeX RDF
23	Hiroaki Takada, Shinya Honda, Reiji Nishiyama, Hiroshi Yuyama	Hardware/Software Co-Configuration for Multiprocessor SoPC.	WSTFES	2003	DBLP DOI BibTeX RDF
23	Ciaran Toal, Sakir Sezer, Xing Yu	A Pipelined SoPC Architecture for 2.5 Gbps Network Processing.	FCCM	2003	DBLP DOI BibTeX RDF
23	Ranianand Venkata, Wilson Wong, Tina Tran, Vinson Chan, Tim Hoang, Henry Lui, Uinh Ton, Sergey Shomurryev, Chong Lee, Shoujun Waiig, Huy Ngo, Malik Kdhani, Victor Maruri, Tin Lai, Tam Kpuyeu, Arch Zaliziiyak, Mei Luo, Toan Nguyen, Kazi Asaduzzaman, Siniardeep Maangat, John Lam, Rakesh Patel	Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment.	CICC	2003	DBLP DOI BibTeX RDF
23	Andrew Morton, Wayne M. Loucks	Real-Time Kernel Support for Coprocessors: Empirical Study of an SoPC.	Embedded Systems and Applications	2003	DBLP BibTeX RDF
23	Brian Dalay	Accelerating system performance using SOPC builder.	SoC	2003	DBLP DOI BibTeX RDF
17	Shiuh-Jer Huang, Shian-Shin Wu	Vision-Based Robotic Motion Control for Non-autonomous Environment.	J. Intell. Robotic Syst.	2009	DBLP DOI BibTeX RDF	Self-organizing fuzzy control, FPGA chip, Visual servo, Robotic system
17	Avinash Malik, Zoran A. Salcic, Alain Girault, Adam Walker, Sung Chul Lee	A customizable multiprocessor for Globally Asynchronous Locally Synchronous execution.	JTRES	2009	DBLP DOI BibTeX RDF	synchronous and asynchronous concurrency, multiprocessor, GALS, reactivity
17	Ali Koudri, Joël Champeau, Denis Aulagnier, Philippe Soulard	MoPCoM/MARTE Process Applied to a Cognitive Radio System Design and Analysis.	ECMDA-FA	2009	DBLP DOI BibTeX RDF
17	Martin Rozkovec	Implementation of Dynamically Reconfigurable Test Architecture for FPGA Circuits.	DDECS	2008	DBLP DOI BibTeX RDF
17	Xiaojuan Li, Yong Guan, Huimei Yuan	A Novel Course System and Engineering Practice Design for Embed System Education.	CSSE (5)	2008	DBLP DOI BibTeX RDF
17	Hendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt	Improving External Memory Access for Avalon Systems on Programmable Chips..	FPL	2007	DBLP DOI BibTeX RDF
17	Sascha Uhrig, Jörg Wiese	jamuth: an IP processor core for embedded Java real-time systems.	JTRES	2007	DBLP DOI BibTeX RDF	Java execution environment, embedded system-on-a-chip implementation, virtual machine, real-time embedded system, multithreaded processor, Java processor, embedded operating system
17	I-Hsuan Huang, Chih-Chun Wang, Shih-Min Chu, Cheng-Zen Yang	Function-Level Multitasking Interface Design in an Embedded Operating System with Reconfigurable Hardware.	EUC	2007	DBLP DOI BibTeX RDF	hardware function, FPGA-based computer, ?C/OS, Reconfigurable computing, multitasking
17	Narashiman Chakravarthy, Jizhong Xiao	FPGA-based Control System for Miniature Robots.	IROS	2006	DBLP DOI BibTeX RDF
17	Stéphane Simard, Rachid Beguenane, Éric Larouche, Luc Morin	A 2005 review of FPGA arithmetic (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
17	Klaus Hartmann, Otmar Loffeld, Seyed Eghbal Ghobadi, Valerij Peters, T. D. Arun Prasad, Arnd Sluiter, Wolfgang Weihs, Tobias Lerch, Oliver Lottner	Klassifizierungsaspekte bei der 3D-Szenenexploration mit einer neuen 2D/3D-Multichip-Kamera.	AMS	2005	DBLP DOI BibTeX RDF
17	Luís Gomes 0001, Anikó Costa	Teaching Formal Methods Within System-on-a-Programmable-Chip Design.	MSE	2005	DBLP DOI BibTeX RDF
17	Rainer Ohlendorf, Andreas Herkersdorf, Thomas Wild	FlexPath NP: a network processor concept with application-driven flexible processing paths.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	dynamically reconfigurable processors, network processors, hardware accelerators, IP networking, application-specific architectures
17	John D. Carter, Ming Xu, William B. Gardner	Rapid Prototyping of Embedded Software Using Selective Formalism.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
17	Ian McRitchie, T. John Brown, Ivor T. A. Spence	A Java framework for the static reflection, composition and synthesis of software components.	PPPJ	2003	DBLP BibTeX RDF	adaptable, component, product line, aspect-oriented
17	Julio A. de Oliveira Filho, Manoel Eusébio de Lima, Paulo Romero Martins Maciel	Petri Net Based Interface Analysis for Fast IP-Core Integration.	MEMOCODE	2003	DBLP DOI BibTeX RDF
17	Ciaran Toal, Sakir Sezer	A Programmable and Highly Pipelined PPP Architecture for Gigabit IP over SDH/SONET.	IPDPS	2003	DBLP DOI BibTeX RDF