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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 127 occurrences of 97 keywords
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Results
Found 203 publication records. Showing 194 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | Roderick Bloem, Swen Jacobs, Ayrat Khalimov 0001 |
Parameterized Synthesis Case Study: AMBA AHB. |
CoRR |
2014 |
DBLP BibTeX RDF |
|
26 | Roderick Bloem, Swen Jacobs, Ayrat Khalimov 0001 |
Parameterized Synthesis Case Study: AMBA AHB. |
SYNT |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Javier Jalle, Jaume Abella 0001, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Francisco J. Cazorla |
AHRB: A high-performance time-composable AMBA AHB bus. |
RTAS |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Laurentiu Acasandrei, Angel Barriga |
AMBA bus hardware accelerator IP for Viola-Jones face detection. |
IET Comput. Digit. Tech. |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Yashdeep Godhal, Krishnendu Chatterjee, Thomas A. Henzinger |
Synthesis of AMBA AHB from formal specification: a case study. |
Int. J. Softw. Tools Technol. Transf. |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Xiongfei Liao, Jun Zhou 0017, Xin Liu 0015 |
Exploring AMBA AXI on-Chip interconnection for TSV-based 3D SoCs. |
3DIC |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Marcel Pockrandt, Paula Herber, Sabine Glesner |
Model checking a SystemC/TLM design of the AMBA AHB protocol. |
ESTIMedia |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Holger Michel, Frank Bubenhagen, Björn Fiethe, Harald Michalik, Björn Osterloh, Wayne Sullivan, Alex Wishart, Jørgen Ilstad, Sandi Habinc |
AMBA to SoCWire network on Chip bridge as a backbone for a Dynamic Reconfigurable Processing unit. |
AHS |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Alistair A. McEwan, Steve A. Schneider |
Modelling and analysis of the AMBA bus using CSP and B. |
Concurr. Comput. Pract. Exp. |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Liang-Bi Chen, Jiun-Cheng Ju, Chien-Chou Wang, Ing-Jer Huang |
HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms. |
IEICE Trans. Inf. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Yashdeep Godhal, Krishnendu Chatterjee, Thomas A. Henzinger |
Synthesis of AMBA AHB from Formal Specification |
CoRR |
2010 |
DBLP BibTeX RDF |
|
26 | Jih-Ching Chiu, Kai-Ming Yang, Mu-Chi Chang |
The Rendezvous Mechanism for the Multi-core AMBA System. |
ICPP Workshops |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Guangrong Pan, Da Feng, Qin Wang 0004, Yue Qi, Meiqiang Yu |
The Design and Implementation of AMBA Interfaced High-Performance SDRAM Controller for HDTV SoC. |
CSIE (3) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Yi-Ting Lin, Chien-Chou Wang, Ing-Jer Huang |
AMBA AHB bus potocol checker with efficient debugging mechanism. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Jennifer Jayme, Anastacia P. Ballesil, Joy Alinda Reyes |
Analysis of Different AMBA-Based Bus Interconnection Schemes for ARM7 Multicore Environment. |
PDPTA |
2008 |
DBLP BibTeX RDF |
|
26 | Jaehoon Song, Juhee Han, Dooyoung Kim, Hyunbean Yi, Sungju Park |
Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC. |
ATS |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Alistair A. McEwan, Steve A. Schneider |
Modeling and Analysis of the AMBA Bus Using CSP and B. |
CPA |
2007 |
DBLP BibTeX RDF |
|
26 | Hasan Amjad |
Verification of AMBA Using a Combination of Model Checking and Theorem Proving. |
AVoCS |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Alberto Paucar-Caceres, R. Thorpe |
Mapping the structure of MBA programmes: a comparative study of the structure of accredited AMBA programmes in the United Kingdom. |
J. Oper. Res. Soc. |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Adeoye Olugbon, Tughrul Arslan, Iain Lindsay |
A Formal Approach to Virtualisation and Provisioning in AMBA AHB-based Reconfigurable Systems-on-Chip. |
SoC |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Kong Woei Susanto, Thomas F. Melham |
An AMBA-ARM7 Formal Verification Platform. |
ICFEM |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan |
Crosstalk Immune Coding from Area and Power Perspective for high performance AMBA based SoC systems. |
VLSI-SOC |
2003 |
DBLP BibTeX RDF |
|
26 | Massimo Conti, Marco Caldari, Simone Orcioni |
Dynamic Power Management of an AMBA-based Platform in SystemC. |
FDL |
2003 |
DBLP BibTeX RDF |
|
26 | Youngwoo Kim, Kyoung Park, Myungjoon Kim |
AMBA based multiprocessor system. |
SoC |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Marco Caldari, Massimo Conti, Paolo Crippa, Simone Orcioni, M. Solazzi, Claudio Turchetti |
Dynamic power management in an AMBA-based battery-powered system. |
ICECS |
2002 |
DBLP DOI BibTeX RDF |
|
26 | David Flynn |
AMBA: enabling reusable on-chip designs. |
IEEE Micro |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Yi-Ting Lin, Wen-Chi Shiue, Ing-Jer Huang |
A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
AMBA AHB, backward trace, bus tracer, circular buffer, forward trace, compression |
23 | Arjan Bink, Richard York |
ARM996HS: The First Licensable, Clockless 32-Bit Processor Core. |
IEEE Micro |
2007 |
DBLP DOI BibTeX RDF |
clockless, low EME, TiDE, Haste, VLSI, low power, SoC, asynchronous, processor, circuit design, ARM, AMBA |
23 | Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang |
A network security processor design based on an integrated SOC design and test platform. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
HMAC-MD5, HMAC-SHA1, AES, RSA, AMBA, RNG |
23 | Francesco Poletti, Paul Marchal, David Atienza, Luca Benini, Francky Catthoor, Jose Manuel Mendias |
An integrated hardware/software approach for run-time scratchpad management. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
AMBA AHB, scratchpad, DMA, dynamic allocation |
14 | Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran |
Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
converter synthesis, protocol compatibility, System-on-chip, automatic design |
14 | Shivram Dattaray Joshi |
Background of the Astadhyayi. |
Sanskrit Computational Linguistics |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Ricardo Bedin França, Leandro Buss Becker, Jean-Paul Bodeveix, Jean-Marie Farines, Mamoun Filali |
Towards Safe Design of Synchronous Bus Protocols in Event-B. |
SBMF |
2009 |
DBLP DOI BibTeX RDF |
synchronous systems, Event-B, parameterized systems, bus protocols |
14 | Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Gunar Schirner, Rainer Dömer |
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling. |
ACM Trans. Embed. Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
system-on-chip, System level design, transaction level modeling |
14 | Julien Schmaltz, Dominique Borrione |
A functional formalization of on chip communications. |
Formal Aspects Comput. |
2008 |
DBLP DOI BibTeX RDF |
Formal methods, Networks on chip, Automated theorem proving, Communication architectures |
14 | Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran |
A Formal Approach To The Protocol Converter Problem. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Sudeep Pasricha, Nikil D. Dutt |
ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Tse-Wei Chen 0001, Chih-Hao Sun, Jun-Ying Bai, Han-Ru Chen, Shao-Yi Chien |
Architectural analyses of K-Means silicon intellectual property for image segmentation. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov |
Protecting bus-based hardware IP by secret sharing. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
cryptography, manufacturing, integrated circuits, computer crime |
14 | Gunar Schirner, Rainer Dömer |
Result-Oriented Modeling - A Novel Technique for Fast and Accurate TLM. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Roderick Bloem, Stefan J. Galler, Barbara Jobstmann, Nir Piterman, Amir Pnueli, Martin Weiglhofer |
Interactive presentation: Automatic hardware synthesis from specifications: a case study. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi |
Functional Test-Case Generation by a Control Transaction Graph for TLM Verification. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Huan-Kai Peng, Chun-Hsin Lee, Jian-Wen Chen, Tzu-Jen Lo, Yung-Hung Chang, Sheng-Tsung Hsu, Yuan-Chun Lin, Ping Chao, Wei-Cheng Hung, Kai-Yuan Jan |
A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC Platform. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Kathi Fisler |
Two-Dimensional Regular Expressions for Compositional Bus Protocols. |
FMCAD |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Martin Oberkönig, Martin Schickel, Hans Eveking |
A Quantitative Completeness Analysis for Property-Sets. |
FMCAD |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Nikil D. Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha |
Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chih-Wei Jen |
A Compact DSP Core with Static Floating-Point Arithmetic. |
J. VLSI Signal Process. |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Sanghun Lee, Chanho Lee |
A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti 0001 |
Synthesis of system verilog assertions. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya |
Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Michael Cowell, Adam Postula |
Rachael SPARC: An Open Source 32-bit Microprocessor Core for SoCs. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Min Wu, Xiaoyang Zeng, Jun Han 0003, Yongyi Wu, Yibo Fan |
A high-performance platform-based SoC for information security. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Hong Yue, Zhiying Wang 0003, Kui Dai |
A Heterogeneous Embedded MPSoC for Multimedia Applications. |
HPCC |
2006 |
DBLP DOI BibTeX RDF |
Transport Triggered Architecture, DSP, Embedded Processor, Heterogeneous MPSoC |
14 | Jianjun Guo, Kui Dai, Zhiying Wang 0003 |
A Heterogeneous Multi-core Processor Architecture for High Performance Computing. |
Asia-Pacific Computer Systems Architecture Conference |
2006 |
DBLP DOI BibTeX RDF |
TTA, SoC, heterogeneous, multi-core |
14 | Gunar Schirner, Rainer Dömer |
Fast and accurate transaction level models using result oriented modeling. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Michel Metzger, Frédéric Bastien, Frédéric Rousseau 0001, Julie Vachon, El Mostapha Aboulhamid |
Introspection Mechanisms for Semi-Formal Verification in a System-Level Design Environment. |
IEEE International Workshop on Rapid System Prototyping |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Marcello Coppola |
Trends and Trade-offs in Designing Highly Robust Throughput on Chip Communication Network. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen |
Language-Based High Level Transaction Extraction on On-chip Buses. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Sung Bum Pan, Daesung Moon, Kichul Kim, Yongwha Chung |
A VLSI Implementation of Minutiae Extraction for Secure Fingerprint Authentication. |
CIS |
2006 |
DBLP DOI BibTeX RDF |
fingerprint authentication, minutiae extraction, VLSI, SoC |
14 | Moonvin Song, Yunmo Chung |
SoC Design of Speaker Connection System by Efficient Cosimulation. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Hans-Joachim Stolberg, Mladen Berekovic, Sören Moch, Lars Friebe, Mark Bernd Kulaczewski, Sebastian Flügel, Heiko Klußmann, Andreas Dehnhardt, Peter Pirsch |
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing. |
J. VLSI Signal Process. |
2005 |
DBLP DOI BibTeX RDF |
multimedia, VLSI, system-on-chip, multi-core, surveillance, MPEG-4 |
14 | Luca Benini, Davide Bertozzi, Alessandro Bogliolo, Francesco Menichelli, Mauro Olivieri |
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC. |
J. VLSI Signal Process. |
2005 |
DBLP DOI BibTeX RDF |
system-on-chip simulation, design space exploration, multiprocessor embedded systems |
14 | Shankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grøndahl Olsen, Jens Sparsø, Jan Madsen |
A Network Traffic Generator Model for Fast Network-on-Chip Simulation. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Ambar A. Gadkari, S. Ramesh 0002 |
Automated Synthesis of Assertion Monitors using Visual Specifications. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Chun-Nan Liu, Tsung-Han Tsai 0001 |
SoC platform based design of MPEG-2/4 AAC audio decoder. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Yan-Chen Lu, Chun-Fu Shen, Chi-Kuang Chen, Ju-Lung Fann |
Performance-driven optimization for video accelerator design [video coding]. |
ISCAS (5) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Gang-Hoon Seo, Won-Yong Jung, Seongsoo Lee, Jae-Kyung Wee |
Pipelined Bidirectional Bus Architecture for Embedded Multimedia SoCs. |
EUC |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Samy Meftali, Jean-Luc Dekeyser, Isaac D. Scherson |
Scalable Multistage Network for Multiprocessor System-on-Chip Design. |
ISPAN |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Sangik Choi, Shinwook Kang |
Implementation of an On-Chip Bus Bridge between Heterogeneous Buses with Different Clock Frequencies. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
communication architectures, on-chip bus |
14 | Sören Moch, Mladen Berekovic, Hans-Joachim Stolberg, Lars Friebe, Mark Bernd Kulaczewski, Andreas Dehnhardt, Peter Pirsch |
HIBRID-SOC: a multi-core architecture for image and video applications. |
SIGARCH Comput. Archit. News |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti 0001 |
The BUSpec platform for automated generation of verification aids for standard bus protocols. |
MEMOCODE |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan |
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Francesco Menichelli, Mauro Olivieri, Luca Benini, Monica Donno, Labros Bisdounis |
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Abhijit K. Deb, Axel Jantsch, Johnny Öberg |
System Design for DSP Applications Using the MASIC Methodology. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Vijay D'Silva, S. Ramesh 0001, Arcot Sowmya |
Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou |
On compliance test of on-chip bus for SOC. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Norbert Pramstaller, Johannes Wolkerstorfer |
A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Kanishka Lahiri, Anand Raghunathan |
Power analysis of system-level on-chip communication architectures. |
CODES+ISSS |
2004 |
DBLP DOI BibTeX RDF |
system-on-chip, network-on-chip, low-power design, power analysis, communication architectures |
14 | Yann Thoma, Eduardo Sanchez, Daniel Roggen, Carl Hetherington, Juan Manuel Moreno |
Prototyping with a Bio-Inspired Reconfigurable Chip. |
IEEE International Workshop on Rapid System Prototyping |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen |
A compact DSP core with static floating-point unit & its microcode generation. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
DSP core, digital signal processor, floating-point units |
14 | Jürgen Becker 0001, Martin Vorbach |
Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC). |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Franco Carbognani, Christopher K. Lennard, C. Norris Ip, Allan Cochrane, Paul Bates |
Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch |
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Martin Vorbach, Jürgen Becker 0001 |
Reconfigurable Processor Architectures for Mobile Phones. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Ciaran Toal, Sakir Sezer |
A 32-Bit SoPC Implementation of a P5. |
ISCC |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Ansuman Banerjee, Pallab Dasgupta, Partha Pratim Chakrabarti |
Open computation tree logic with fairness. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Davide Bertozzi, Luca Benini, Giovanni De Micheli |
Low Power Error Resilient Encoding for On-Chip Data Buses. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Davide Bertozzi, Luca Benini, Bruno Riccò |
Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding. |
ISCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Rainer Dorsch, Ramón Huerta Rivera, Hans-Joachim Wunderlich, Martin Fischer |
Adapting an SoC to ATE Concurrent Test Capabilities. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
ATE, SoC Test, Concurrent Test, Test Resource Partitioning |
14 | Marcio T. Oliveira, Alan J. Hu |
High-Level specification and automatic generation of IP interface monitors. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
formal verification, pipelining, regular expressions, alternation |
14 | Arindam Chakrabarti, Pallab Dasgupta, P. P. Chakrabarti 0001, Ansuman Banerjee |
Formal verification of module interfaces against real time specifications. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
formal verification, temporal logic |
14 | Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu |
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
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