Search results for "netlists"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
13	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Fixing Design Errors With Counterexamples and Resynthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
13	Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko	WireMap: FPGA technology mapping for improved routability.	FPGA	2008	DBLP DOI BibTeX RDF	area flow, cut enumeration, edge flow, FPGA, technology mapping
13	David J. Greaves, Satnam Singh	Kiwi: Synthesis of FPGA Circuits from Parallel Programs.	FCCM	2008	DBLP DOI BibTeX RDF
13	Azam Beg, P. W. Chandana Prasad, Walid Ibrahim, Emad Abu Shama	Utilizing synthesis to verify Boolean function models.	ISCAS	2008	DBLP DOI BibTeX RDF
13	Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong	Place-and-Route Impact on the Security of DPL Designs in FPGAs.	HOST	2008	DBLP DOI BibTeX RDF
13	Jason Baumgartner, Hari Mony, Adnan Aziz	Optimal Constraint-Preserving Netlist Simplification.	FMCAD	2008	DBLP DOI BibTeX RDF
13	Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton	Improvements to Technology Mapping for LUT-Based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
13	Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li 0001, Weiping Shi, Chin Ngai Sze	Fast Algorithms for Slew-Constrained Minimum Cost Buffering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
13	Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Node Mergers in the Presence of Don't Cares.	ASP-DAC	2007	DBLP DOI BibTeX RDF
13	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Fixing Design Errors with Counterexamples and Resynthesis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	simulation-based verification, digital design errors, error-correction framework, resynthesis techniques, goal-directed search, entropy-guided search, counterexamples, digital designs, combinational equivalence-checking
13	Shiyan Hu, Jiang Hu	Pattern sensitive placement for manufacturability.	ISPD	2007	DBLP DOI BibTeX RDF	placement, physical design, manufacturability
13	Rainer Scholz	Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations.	ARC	2007	DBLP DOI BibTeX RDF
13	Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout	A nonlinear cell macromodel for digital applications.	ICCAD	2007	DBLP DOI BibTeX RDF
13	Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi	An Efficient Algorithm for RLC Buffer Insertion.	ISQED	2007	DBLP DOI BibTeX RDF
13	Christopher R. Clark, David E. Schimmel	Modeling the data-dependent performance of pattern-matching architectures.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, pattern matching
13	Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton	Improvements to technology mapping for LUT-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	area recovery, cut enumeration, lossless synthesis, FPGA, technology mapping
13	Gerd Vandersteen, Stephane Bronckers, Petr Dobrovolný, Yves Rolain	Systematic stability-analysis method for analog circuits.	DATE	2006	DBLP DOI BibTeX RDF
13	Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii	Enabling fine-grain leakage management by voltage anchor insertion.	DATE	2006	DBLP DOI BibTeX RDF
13	Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky Ramachandran	Solving hard instances of floorplacement.	ISPD	2006	DBLP DOI BibTeX RDF	floorplacement, benchmarks, placement, floorplanning, RTL, circuit layout
13	Jarrod A. Roy, David A. Papa, Aaron N. Ng, Igor L. Markov	Satisfying whitespace requirements in top-down placement.	ISPD	2006	DBLP DOI BibTeX RDF	placement, physical design, floorplanning
13	Evgeny Fiksman, Yitzhak Birk, Oskar Mencer	ASC-Based Acceleration in an FPGA with a Processor Core Using Software-Only Skills.	FCCM	2006	DBLP DOI BibTeX RDF
13	Beth Isaksen, Valeria Bertacco	Verification through the principle of least astonishment.	ICCAD	2006	DBLP DOI BibTeX RDF
13	Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li 0001, Weiping Shi	A new RLC buffer insertion algorithm.	ICCAD	2006	DBLP DOI BibTeX RDF
13	André K. Nieuwland, Samir Jasarevic, Goran Jerin	Combinational Logic Soft Error Analysis and Protection.	IOLTS	2006	DBLP DOI BibTeX RDF
13	Lun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula	Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions.	ASAP	2006	DBLP DOI BibTeX RDF
13	Vyas Krishnan, Srinivas Katkoori	Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation.	ISQED	2006	DBLP DOI BibTeX RDF
13	Robin J. Bruce, Richard Chamberlain, Malachy Devlin, Stephen Marshall	Poster reception - Implementing algorithms on FPGAs using high-level languages and low-level libraries.	SC	2006	DBLP DOI BibTeX RDF
13	Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li 0001, Weiping Shi, Cliff C. N. Sze	Fast algorithms for slew constrained minimum cost buffering.	DAC	2006	DBLP DOI BibTeX RDF	slew constraint, physical design, buffer insertion
13	Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester	Switch-factor based loop RLC modeling for efficient timing analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
13	Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev	Design and Analysis of Dual-Rail Circuits for Security Applications.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Alternating spacer protocol, dual-rail encoding, hazard-free design, cryptography, power analysis, design automation, hardware security
13	Fei Li 0003, Yizhou Lin, Lei He 0001, Deming Chen, Jason Cong	Power modeling and characteristics of field programmable gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
13	Qinghua Liu, Malgorzata Marek-Sadowska	A study of netlist structure and placement efficiency.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
13	Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail	Realizable reduction of interconnect circuits including self and mutual inductances.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
13	Song Peng, David Fang, John Teifel, Rajit Manohar	Automated synthesis for asynchronous FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	asychronous circuits, programmable logic, automated synthesis
13	Viresh Paruthi, Christian Jacobi 0002, Kai Weber 0001	Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting.	CHARME	2005	DBLP DOI BibTeX RDF
13	Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große	SyCE: An Integrated Environment for System Design in SystemC.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
13	Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet	The "Backend Duplication" Method.	CHES	2005	DBLP DOI BibTeX RDF	secured backend, differential signals, Information leakage
13	Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu	Piece-wise approximations of RLCK circuit responses using moment matching.	DAC	2005	DBLP DOI BibTeX RDF	RC, RLCK circuits, interconnect timing analysis, moments, RLC
13	Dominik Stoffel, Markus Wedler, Peter Warkentin, Wolfgang Kunz	Structural FSM traversal.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
13	Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck	Exploration of pipelined FPGA interconnect structures.	FPGA	2004	DBLP DOI BibTeX RDF	PipeRoute, pipelined FPGA, pipelined interconnect, registered routing, architecture explorations
13	Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke	Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques.	DATE	2004	DBLP DOI BibTeX RDF
13	Pierluigi Daglio, David Iezzi, Danilo Rimondi, Carlo Roma, Salvatore Santapa	Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components.	DATE	2004	DBLP DOI BibTeX RDF
13	Ivan Blunno, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou	Handshake Protocols for De-Synchronization.	ASYNC	2004	DBLP DOI BibTeX RDF
13	Mark Holland, Scott Hauck	Automatic Creation of Reconfigurable PALs/PLAs for SoC.	FPL	2004	DBLP DOI BibTeX RDF
13	Rajarshi Mukherjee, Seda Ogrenci Memik	Power-Driven Design Partitioning.	FPL	2004	DBLP DOI BibTeX RDF
13	Rajarshi Mukherjee, Seda Ogrenci Memik	Power Management for FPGAs: Power-Driven Design Partitioning.	FCCM	2004	DBLP DOI BibTeX RDF
13	Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra	ELF-Murphy Data on Defects and Test Sets.	VTS	2004	DBLP DOI BibTeX RDF
13	Martin Trefzer, Jörg Langeheine, Johannes Schemmel, Karlheinz Meier	New Genetic Operators to Facilitate Understanding of Evolved Transistor Circuits.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
13	Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev	Improving the Security of Dual-Rail Circuits.	CHES	2004	DBLP DOI BibTeX RDF
13	Victor V. Zyuban	Optimization of scannable latches for low energy.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
13	Abdel Ejnioui, N. Ranganathan	Multiterminal net routing for partial crossbar-based multi-FPGA systems.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
13	Mitrajit Chatterjee, Dhiraj K. Pradhan	A BIST Pattern Generator Design for Near-Perfect Fault Coverage.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	core logic, built-in self-test, synthesis, fault coverage, Linear feedback shift registers, test pattern generation, scan, SOC
13	Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel	Interconnect Driven Low Power High-Level Synthesis.	PATMOS	2003	DBLP DOI BibTeX RDF
13	Akshay Sharma, Carl Ebeling, Scott Hauck	PipeRoute: a pipelining-aware router for FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	BFS, PipeRoute, retimed circuits, routing, pipelining, minimum spanning tree, retiming, pipelined circuits
13	Herman Schmit	Extra-dimensional Island-Style FPGAs.	FPL	2003	DBLP DOI BibTeX RDF
13	Markus Hütter, Holger Bock, Michael Scheppler	A New Reconfigurable Architecture for Single Cycle Context Switching.	IPDPS	2003	DBLP DOI BibTeX RDF
13	Saurabh N. Adya, Igor L. Markov, Paul Villarrubia	On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis.	ICCAD	2003	DBLP DOI BibTeX RDF
13	Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester	Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF	RLC model, loop inductance, switch-factor, current return loop, data-bus and clock, static timing analysis, slew rate
13	Pallav Gupta, Lin Zhong 0001, Niraj K. Jha	A High-level Interconnect Power Model for Design Space Exploration.	ICCAD	2003	DBLP DOI BibTeX RDF
13	Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter	Realizable reduction of RLC circuits using node elimination.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
13	Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail	Realizable RLCK circuit crunching.	DAC	2003	DBLP DOI BibTeX RDF	crunching, simulation, interconnect, passive, realizable, model order reduction
13	Yu Cao 0001, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu	Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
13	Jason Baumgartner, Andreas Kuehlmann, Jacob A. Abraham	Property Checking via Structural Analysis.	CAV	2002	DBLP DOI BibTeX RDF
13	Khaled Benkrid, Danny Crookes, Abdsamad Benkrid, Samir Belkacemi	A Prolog-Based Hardware Development Environment.	FPL	2002	DBLP DOI BibTeX RDF
13	André DeHon, Randy Huang, John Wawrzynek	Hardware-Assisted Fast Routing.	FCCM	2002	DBLP DOI BibTeX RDF
13	Fazrena A. Hamid, Tom J. Kazmierski	Synthesis and optimization of analog VLSI filters from VHDL-AMS parse trees.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
13	Mika Kontiala, Aarne Heinonen, Jari Nurmi	Low-power methodology issues in digital circuit design.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
13	Ajay J. Daga, Loa Mize, Subramanyam Sripada, Chris Wolff, Qiuyang Wu	Automated timing model generation.	DAC	2002	DBLP DOI BibTeX RDF	EDA, static timing analysis, model generation
13	Chau-Shen Chen, TingTing Hwang, C. L. Liu 0001	Architecture driven circuit partitioning.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
13	Rony Kay, Rob A. Rutenbar	Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
13	Arlindo L. Oliveira	Techniques for the creation of digital watermarks in sequentialcircuit designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
13	Rolf Drechsler, Wolfgang Günther 0001, Lothar Linhard, Gerhard Angst	Level Assignment for Displaying Combinational Logic.	DSD	2001	DBLP DOI BibTeX RDF
13	Kee Sup Kim, Rathish Jayabharathi, Craig Carstens	SpeedGrade: An RTL Path Delay Fault Simulator.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
13	Klaus Harbich, Erich Barke	PuMA++: From Behavioral Specification to Multi-FPGA-Prototype.	FPL	2001	DBLP DOI BibTeX RDF
13	Albert Simpson, Jill K. Hunter, Moira Wylie, Yi Hu, David Mann	Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processing.	FPL	2001	DBLP DOI BibTeX RDF
13	Sheng Sun, Larry McMurchie, Carl Sechen	A High-Performance 64-bit Adder Implemented in Output Prediction Logic.	ARVLSI	2001	DBLP DOI BibTeX RDF
13	Wolfgang Günther 0001, Rolf Drechsler	Performance Driven Optimization for MUX based FPGAs.	VLSI Design	2001	DBLP DOI BibTeX RDF
13	Shengchao Qin, Zongyan Qiu, Jifeng He 0001	Constructing Hardware/Software Interface Using Protocol Converters.	APAQS	2001	DBLP DOI BibTeX RDF	protocol converter, program algebra, Hardware/software partition
13	Shantanu Dutt, Wenyong Deng	Probability-based approaches to VLSI circuit partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
13	Wen-Jong Fang, Allen C.-H. Wu	Multiway FPGA partitioning by fully exploiting design hierarchy.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	fine-grained synthesis, functional clustering, multi-way partitioning, multiple-FPGA synthesis
13	Joerg Abke, Erich Barke	CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
13	Wolfgang Günther 0001, Rolf Drechsler	ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs.	EUROMICRO	2000	DBLP DOI BibTeX RDF
13	Thomas Kutzschebauch	Efficient Logic Optimization Using Regularity Extraction.	ICCD	2000	DBLP DOI BibTeX RDF
13	Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen	Output Prediction Logic: A High-Performance CMOS Design Technique.	ICCD	2000	DBLP DOI BibTeX RDF
13	Peivand F. Tehrani, Shang Woo Chyou, Uma Ekambaram	Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk.	ISQED	2000	DBLP DOI BibTeX RDF	simulation, VLSI, timing, Crosstalk, DSM, static, transistor
13	Rajesh Pendurkar, Craig A. Tovey, Abhijit Chatterjee	Single-probe traversal optimization for testing of MCM substrate interconnections.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
13	Lluís Ribas, Jordi Carrabina	Digital MOS Circuit Partitioning with Symbolic Modeling.	DATE	1999	DBLP DOI BibTeX RDF	switch-level circuit analysis, symbolic circuit traversal, circuit partitioning, symbolic modeling
13	Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu	A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs.	ASP-DAC	1999	DBLP DOI BibTeX RDF
13	Paul Tafertshofer, Andreas Ganz	SAT based ATPG using fast justification and propagation in the implication graph.	ICCAD	1999	DBLP DOI BibTeX RDF
13	Russell Tessier	Incremental Compilation for Logic Emulation.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	virtual wire, scheduling, partitioning, incremental, logic emulation
13	Per Lindgren, Rolf Drechsler, Bernd Becker 0001	Synthesis of Pseudo Kronecker Lattice Diagrams.	ICCD	1999	DBLP DOI BibTeX RDF
13	Michael D. Hutton, Jonathan Rose	Equivalence classes of clone circuits for physical-design benchmarking.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
13	Chia-Pin R. Liu, Jacob A. Abraham	Transistor Level Synthesis for Static CMOS Combinational Circuits.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
13	Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, Derek G. Corneil	Characterization and parameterized generation of synthetic combinational benchmark circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
13	James Hwang, Cameron Patterson, S. Mohan, Eric Dellinger, Sujoy Mitra, Ralph Wittig	Generating Layouts for Self-implementing Modules.	FPL	1998	DBLP DOI BibTeX RDF
13	Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke	An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping.	FPL	1998	DBLP DOI BibTeX RDF
13	P. S. Nagendra Rao, C. S. Jayathirtha, C. S. Raghavendra Prasad	New Net Models for Spectral Netlist Partitioning.	VLSI Design	1998	DBLP DOI BibTeX RDF	Netlist Partitioning, Spectral Partitioning Net Models, Clique Models, Star Models, Graph Partitioning
13	Wen-Jong Fang, Allen C.-H. Wu	A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
13	Kenneth L. Shepard, Vinod Narayanan, Peter C. Elmendorf, Gutuan Zheng	Global harmony: coupled noise analysis for full-chip RC interconnect networks.	ICCAD	1997	DBLP DOI BibTeX RDF	interconnect, noise, static timing analysis
13	Franco Fummi, Mariagiovanna Sami, F. Tartarini	Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF