Search results for "radix-4"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Srikant Kumar Beura, Sudeshna Manjari Mahanta, Bishnulatpam Pushpa Devi, Prabir Saha	Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication.	Integr.	2024	DBLP DOI BibTeX RDF
14	Christopher Grimm, Jinseok Lee, Naveen Verma	Training Neural Networks With In-Memory-Computing Hardware and Multi-Level Radix-4 Inputs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
14	David M. Harris, James E. Stine, Milos D. Ercegovac, Alberto Nannarelli, Katherine Parry, Cedar Turek	Unified Digit Selection for Radix-4 Recurrence Division and Square Root.	IEEE Trans. Computers	2024	DBLP DOI BibTeX RDF
14	Dongseok Im, Hoi-Jun Yoo	LUTein: Dense-Sparse Bit-Slice Architecture With Radix-4 LUT-Based Slice-Tensor Processing Units.	HPCA	2024	DBLP DOI BibTeX RDF
14	Rui Xiao, Yewei Zhang, Bo Wang 0020, Yanfeng Xu, Jicong Fan, Haibin Shen, Kejie Huang	A Low-Power In-Memory Multiplication and Accumulation Array With Modified Radix-4 Input and Canonical Signed Digit Weights.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
14	Gunho Park, Jaeha Kung, Youngjoo Lee	Simplified Compressor and Encoder Designs for Low-Cost Approximate Radix-4 Booth Multiplier.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
14	Quan Cheng, Liuyao Dai, Mingqiang Huang, Ao Shen, Wei Mao 0002, Masanori Hashimoto, Hao Yu 0001	A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
14	Shubhanjay S. Pujari, M. Bhaskar 0001	Design and FPGA Implementation of Pre-computation Based Radix-4 Hyperbolic CORDIC for Direct Digital Synthesis.	J. Signal Process. Syst.	2023	DBLP DOI BibTeX RDF
14	Muhammad Akmal Shafique, Kashif Inayat, Jeong-A Lee	CSA Based Radix-4 Gemmini Systolic Array for Machine Learning Applications.	HEART	2023	DBLP DOI BibTeX RDF
14	Christopher Grimm, Naveen Verma	Neural Network Training on In-Memory-Computing Hardware With Radix-4 Gradients.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
14	Boon-Chiao Chang, Wai-Kong Lee, Bok-Min Goi, Seong Oun Hwang	High Performance Integer Multiplier on FPGA with Radix-4 Number Theoretic Transform.	KSII Trans. Internet Inf. Syst.	2022	DBLP DOI BibTeX RDF
14	Christopher Grimm, Naveen Verma	Neural Network Training on In-memory-computing Hardware with Radix-4 Gradients.	CoRR	2022	DBLP DOI BibTeX RDF
14	Oguz Meteer, Arvid B. Van Den Brink, Marco Jan Gerrit Bekooij	Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating.	DSD	2022	DBLP DOI BibTeX RDF
14	Morgana Macedo Azevedo da Rosa, Guilherme Paim, Jorge Castro-Godínez, Eduardo A. C. da Costa, Rafael Iankowski Soares, Sergio Bampi	AxRSU: Approximate Radix-4 Squarer Unit.	ISCAS	2022	DBLP DOI BibTeX RDF
14	Subodh Kumar Singhal, Sujit Kumar Patel, Anurag Mahajan, Gaurav Saxena	Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applications.	Turkish J. Electr. Eng. Comput. Sci.	2021	DBLP DOI BibTeX RDF
14	Kun-Lin Tsai, Yen-Jen Chang, Chien-Ho Wang, Cheng-Tse Chiang	Accuracy-Configurable Radix-4 Adder With a Dynamic Output Modification Scheme.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
14	Mir Majid Ghasemi, Amir Fathi, Morteza Mousazadeh, Abdollah Khoei	A new high speed and low power decoder/encoder for Radix-4 Booth multiplier.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
14	Rui Xiao, Kejie Huang, Yewei Zhang, Haibin Shen	A Low Power In-Memory Multiplication andAccumulation Array with Modified Radix-4 Inputand Canonical Signed Digit Weights.	CoRR	2021	DBLP BibTeX RDF
14	Ratko Pilipovic	A Hybrid Radix-4 and Approximate Logarithmic Multiplier for Energy Efficient Image Processing.		2021	DOI RDF
14	Srikant Kumar Beura, Gudmalwar Ashishkumar Prabhakar, Sudesna Manjari Mahanta, Bishnulatpam Pushpa Devi, Prabir Saha	Design and Analysis of Inexact 3: 2 Compressor-based Radix-4 Multiplier towards Image Multiplication.	ICCCNT	2021	DBLP DOI BibTeX RDF
14	Yen-Jen Chang, Yu-Cheng Cheng, Shao-Chi Liao, Chun-Huo Hsiao	A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism.	IEEE Access	2020	DBLP DOI BibTeX RDF
14	Ratko Pilipovic, Patricio Bulic	On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding.	IEEE Access	2020	DBLP DOI BibTeX RDF
14	Pramod Patali, Shahana Thottathikkulam Kassim	Efficient modular hybrid adders and Radix-4 booth multipliers for DSP applications.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
14	James E. Stine, Kevin Hill	An Efficient Implementation of Radix-4 Integer Division Using Scaling.	MWSCAS	2020	DBLP DOI BibTeX RDF
14	Guilherme da Costa Ferreira, Leandro M. G. Rocha, Eduardo A. C. da Costa, Sergio Bampi	Combining m=2 Multipliers and Adder Compressors for Power Efficient Radix-4 Butterfly.	MWSCAS	2020	DBLP DOI BibTeX RDF
14	Tomotaka Kawabata, Hiroshi Tsutsui	An Evaluation of High-Throughput Scalable Radix-4 FFT Processor Architecture Using Fixed-Point Arithmetic.	APSIPA	2020	DBLP BibTeX RDF
14	Aditya Sankaran, M. Srikanth Reddy, K. R. Arunkumar, M. Bhaskar 0001	Design and Implementation of 1024 Point Pipelined Radix 4 FFT Processor on FPGA for Biomedical Signal Processing Applications.	iSES	2020	DBLP DOI BibTeX RDF
14	Ying Liang, Yuan Meng, Shengkai Wang, Jun Yang	Research on Optimization Technology of Radix-4 FFT in FPGA Implementation.	EITCE	2020	DBLP DOI BibTeX RDF
14	Duncan J. M. Moss, David Boland, Philip H. W. Leong	A Two-Speed, Radix-4, Serial-Parallel Multiplier.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
14	Matthew Gaalswyk, James E. Stine	A Low-Power Recurrence-Based Radix 4 Divider Using Signed-Digit Addition.	ISVLSI	2019	DBLP DOI BibTeX RDF
14	Tingting Zhang, Weiqiang Liu 0001, Jie Han 0001, Fabrizio Lombardi	Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders.	NANOARCH	2019	DBLP DOI BibTeX RDF
14	Yashrajsinh Parmar, Krishnamurthy Sridharan	Precomputation-based radix-4 CORDIC for approximate rotations and Hough transform.	IET Circuits Devices Syst.	2018	DBLP DOI BibTeX RDF
14	Mirko Myllykoski, Tuomo Rossi, Jari Toivanen	On solving separable block tridiagonal linear systems using a GPU implementation of radix-4 PSCR method.	J. Parallel Distributed Comput.	2018	DBLP DOI BibTeX RDF
14	Xiaoting Sun, Yi Guo, Zhenhao Liu, Shinji Kimura	A Radix-4 Partial Product Generation-Based Approximate Multiplier for High-speed and Low-power Digital Signal Processing.	ICECS	2018	DBLP DOI BibTeX RDF
14	Yashrajsinh Parmar, K. Sridharan 0001	Hardware-Efficient Velocity Estimation of Dynamic Obstacles Based on a Novel Radix-4 CORDIC and FPGA Implementation.	IECON	2018	DBLP DOI BibTeX RDF
14	Kaitlin N. Smith, Tim LaFave, Duncan L. MacFarlane, Mitchell A. Thornton	A Radix-4 Chrestenson Gate for Optical Quantum Computation.	ISMVL	2018	DBLP DOI BibTeX RDF
14	Po-Hsun Chang, Chen-Yang Lin, Chia-Hsiang Sun, Yen-Chin Liao, Hsie-Chia Chang	A 188-Length Full Code Rate 333Mbps 1.08mm2 Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Mario Garrido, Miguel Angel Sánchez, María Luisa López Vallejo, Jesús Grajal	A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
14	Weiqiang Liu 0001, Liangyu Qian, Chenghua Wang, Honglan Jiang, Jie Han 0001, Fabrizio Lombardi	Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
14	Alexandru Amaricai, Ovidiu Sicoe, Oana Boncalo	On the Redundant Representation of Partial Remainders in Radix-4 SRT Dividers.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
14	Hussein G. H. Hassan, Amr M. A. Hussien, Hossam A. H. Fahmy	Radix-4 successive cancellation decoding of polar codes with partial sum lookahead.	ICM	2017	DBLP DOI BibTeX RDF
14	Alekhya Lakkadi, Linda S. DeBrunner	Radix-4 modular pipeline fast Fourier transform algorithm.	ACSSC	2017	DBLP DOI BibTeX RDF
14	Kee-Won Kim, Hyun-Ho Lee, Seung-Hoon Kim	Low-Latency Radix-4 Multiplication Algorithm over Finite Fields.	FDSE	2017	DBLP DOI BibTeX RDF
14	Chun-Hsiang Lai, Yu-Cheng Cheng, Tung-Chi Wu, Yen-Jen Chang	Radix-4 adder design with refined carry.	DSC	2017	DBLP DOI BibTeX RDF
14	Kostas Tsoumanis, Nicholas Axelos, Nikolaos Moschopoulos, Georgios Zervakis 0001, Kiamal Z. Pekmestzi	Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
14	Shiann-Rong Kuang, Chih-Yuan Liang, Chun-Chi Chen	An Efficient Radix-4 Scalable Architecture for Montgomery Modular Multiplication.	IEEE Trans. Circuits Syst. II Express Briefs	2016	DBLP DOI BibTeX RDF
14	Guilherme Paim, Leonardo Bandeira Soares, Julio F. R. Oliveira, Eduardo Costa 0001, Sergio Bampi	A power-efficient imprecise radix-4 multiplier applied to high resolution audio processing.	ICECS	2016	DBLP DOI BibTeX RDF
14	Wen Yan, Milos D. Ercegovac	Radix-4 energy efficient carry-free truncated multiplier.	ACSSC	2016	DBLP DOI BibTeX RDF
14	Mohammed Zafar Ali Khan, Shaik A. Qadeer	A new variant of Radix-4 FFT.	WOCN	2016	DBLP DOI BibTeX RDF
14	Cheng-Hung Lin, Chih-Shiang Yu	Multimode Radix-4 SISO Kernel Design for Turbo/LDPC Decoding.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
14	Mehran Mozaffari Kermani, Niranjan Manoharan, Reza Azarderakhsh	Reliable Radix-4 Complex Division for Fault-Sensitive Applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
14	Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang	An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
14	Dan-El A. Montoya, J. A. Rosendo-Macías, Antonio Gómez Expósito	Short-time DFT computation by a modified radix-4 decimation-in-frequency algorithm.	Signal Process.	2014	DBLP DOI BibTeX RDF
14	Mirko Myllykoski, Tuomo Rossi	A parallel radix-4 block cyclic reduction algorithm.	Numer. Linear Algebra Appl.	2014	DBLP DOI BibTeX RDF
14	Sabooh Ajaz, Hanho Lee	An efficient radix-4 Quasi-cyclic shift network for QC-LDPC decoders.	IEICE Electron. Express	2014	DBLP DOI BibTeX RDF
14	Soumak Mookherjee, Linda DeBrunner, Victor E. DeBrunner	A high throughput and low power radix-4 FFT architecture.	ACSSC	2014	DBLP DOI BibTeX RDF
14	Milos D. Ercegovac, Lu Meng	Low-power radix-4 quotient generator.	ACSSC	2014	DBLP DOI BibTeX RDF
14	Senthilkumar Ranganathan, Ravikumar Krishnan, H. S. Sriharsha	Efficient Hardware Implementation of 1024 Point Radix-4 FFT.	SIRS	2014	DBLP DOI BibTeX RDF
14	Boppana Lakshmi, A. S. Dhar 0001	VLSI architecture for parallel radix-4 CORDIC.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
14	Shirin Pourashraf, Sayed Masoud Sayedi	Implementation of a low power 16-bit radix-4 pipelined SRT divider using a modified Split-Path Data Driven Dynamic Logic (SPD3L) structure.	Microelectron. J.	2013	DBLP DOI BibTeX RDF
14	S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy 0001, Ranjani Narayan	High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit.	ISCAS	2013	DBLP DOI BibTeX RDF
14	Shahzad Asif, Mark Vesterbacka	Performance analysis of radix-4 adders.	Integr.	2012	DBLP DOI BibTeX RDF
14	Rongchun Li, Yong Dou, Yuanwu Lei, Shi-Ce Ni, Song Guo 0003	Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA.	IEICE Trans. Commun.	2012	DBLP DOI BibTeX RDF
14	Lo'ai Ali Tawalbeh, Yaser Jararweh, Abidalrahman Mohammad	An integrated radix-4 modular divider/multiplier hardware architecture for cryptographic applications.	Int. Arab J. Inf. Technol.	2012	DBLP BibTeX RDF
14	Rizwan Asghar, Di Wu 0003, Ali Saeed, Yulin Huang, Dake Liu	Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support.	J. Signal Process. Syst.	2012	DBLP DOI BibTeX RDF
14	M. H. M. Larijani, M. B. Ghaznavi-Ghoushchi	A 2-bit/step SAR ADC structure with one radix-4 DAC.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
14	Sheng-Hong Wang, Wen-Ching Lin, Jheng-Hao Ye, Ming-Der Shieh	Fast scalable radix-4 Montgomery modular multiplier.	ISCAS	2012	DBLP DOI BibTeX RDF
14	Shirin Pourashraf, Sayed Masoud Sayedi	A low power D3L 16-bit radix- 4 pipelined SRT divider.	CCECE	2012	DBLP DOI BibTeX RDF
14	Trio Adiono, Marvin	Radix-4 Max-log-MAP parallel turbo decoder architecture with a new cache memory data flow for LTE.	ISPACS	2012	DBLP DOI BibTeX RDF
14	Alban Ferizi, Bernhard Hoeher, Melanie Jung, Georg Fischer 0001, Alexander Koelpin	Design and implementation of a fixed-point radix-4 FFT optimized for local positioning in wireless sensor networks.	SSD	2012	DBLP DOI BibTeX RDF
14	Boppana Lakshmi, A. S. Dhar 0001	VLSI architecture for low latency radix-4 CORDIC.	Comput. Electr. Eng.	2011	DBLP DOI BibTeX RDF
14	Atef Ibrahim, Fayez Gebali, Hamed Elsimary, Amin M. Nassar	Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm.	IEEE Trans. Parallel Distributed Syst.	2011	DBLP DOI BibTeX RDF	low power modular multipliers, scalability, cryptography, Montgomery multiplication, secure communications, Processor array
14	Gautam A. Shah, Tejmal S. Rathore	An Analog Architecture for the Radix-4 DHT.	UKSim	2011	DBLP DOI BibTeX RDF
14	Scott C.-H. Huang, Hsiao-Chun Wu	New General Approach to the Design of Arbitrary Radix-4 QAM Sequences for Low PMEPR and High Code-Rate.	GLOBECOM	2011	DBLP DOI BibTeX RDF
14	Ren-Xi Gong, Jiong-Quan Wei, Dan Sun, Ling-Ling Xie, Peng-Fei Shu, Xiao-Bi Meng	FPGA implementation of a CORDIC-based radix-4 FFT processor for real-time harmonic analyzer.	ICNC	2011	DBLP DOI BibTeX RDF
14	Yao-Lin Chen, Jen-Wei Lee, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee	A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit.	ISCAS	2011	DBLP DOI BibTeX RDF
14	Ramya Muralidharan, Chip-Hong Chang	A simple radix-4 Booth encoded modulo 2n+1 multiplier.	ISCAS	2011	DBLP DOI BibTeX RDF
14	Gyeonghoon Kim, Seungjin Lee 0001, Junyoung Park 0002, Hoi-Jun Yoo	A low-energy hybrid radix-4/-8 multiplier for portable multimedia applications.	ISCAS	2011	DBLP DOI BibTeX RDF
14	Hooman Nikmehr, Braden Phillips, Cheng-Chew Lim	A novel implementation of radix-4 floating-point division/square-root using comparison multiples.	Comput. Electr. Eng.	2010	DBLP DOI BibTeX RDF
14	Kaushik Bhattacharyya, Rakesh Biswas, Anindya Sundar Dhar, Swapna Banerjee	Architectural design and FPGA implementation of radix-4 CORDIC processor.	Microprocess. Microsystems	2010	DBLP DOI BibTeX RDF
14	Ingo Rust, Tobias G. Noll	A radix-4 single-precision floating point divider based on digit set interleaving.	ISCAS	2010	DBLP DOI BibTeX RDF
14	Waqar Hussain 0001, Fabio Garzia, Jari Nurmi	Exploiting control management to accelerate Radix-4 FFT on a reconfigurable platform.	SoC	2010	DBLP DOI BibTeX RDF
14	Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee	A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique.	APCCAS	2010	DBLP DOI BibTeX RDF
14	Pere Martí-Puig, Ramón Reig Bolaño	Radix-4 FFT algorithms with ordered input and output data.	DPS	2009	DBLP DOI BibTeX RDF
14	Ji-Hoon Kim, In-Cheol Park	A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE.	CICC	2009	DBLP DOI BibTeX RDF
14	Boppana Lakshmi, A. S. Dhar 0001	Low Latency VLSI Architecture for the Radix-4 CORDIC Algorithm.	ICIIS	2008	DBLP DOI BibTeX RDF
14	Jason Moore, Mitchell A. Thornton, David W. Matula	A low power radix-4 dual recoded integer squaring implementation for use in design of application specific arithmetic circuits.	ACSCC	2008	DBLP DOI BibTeX RDF
14	Masanori Furuta, Shoji Kawahito, Daisuke Miyazaki	A Digital-Calibration Technique for Redundant Radix-4 Pipelined Analog-to-Digital Converters.	IEEE Trans. Instrum. Meas.	2007	DBLP DOI BibTeX RDF
14	Chau-Yun Hsu, Tsung Sheng Kuo, Yuan Hung Hsu	Low complexity radix-4 butterfly design for the soft-decision Viterbi decoder.	Microprocess. Microsystems	2007	DBLP DOI BibTeX RDF
14	Hooman Nikmehr, Braden Phillips, Cheng-Chew Lim	A Fast Radix-4 Floating-Point Divider with Quotient Digit Selection by Comparison Multiples.	Comput. J.	2007	DBLP DOI BibTeX RDF
14	Nishant R. Srivastava	Interactive presentation: Radix 4 SRT division with quotient prediction and operand scaling.	DATE	2007	DBLP DOI BibTeX RDF
14	Yuan Hung Hsu, Chau-Yun Hsu, Tsung Sheng Kuo	Low Complexity Radix-4 Butterfly Design for the Viterbi Decoder.	VTC Fall	2006	DBLP DOI BibTeX RDF
14	Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu	The new architecture of radix-4 Chinese abacus adder.	ISMVL	2006	DBLP DOI BibTeX RDF
14	Jose Alberto Vite-Frias, René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno	VHDL core for 1024-point radix-4 FFT computation.	ReConFig	2005	DBLP DOI BibTeX RDF
14	Said Boussakta, Osama Alshibami, Ahmed Bouridane	Vector radix-4×4 for fast calculation of the 2-D new Mersenne number transform.	Signal Process.	2004	DBLP DOI BibTeX RDF
14	Jin-Hua Hong, Bin-Yan Tsai, Liang-Te Lu, Shao-Hui Shieh	A novel radix-4 bit-level modular multiplier for fast RSA cryptosystem.	ISCAS (2)	2004	DBLP BibTeX RDF
14	Mohd. Hasan, Tughrul Arslan, John S. Thompson	A novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications.	IEEE Trans. Consumer Electron.	2003	DBLP DOI BibTeX RDF
14	Said Boussakta, Osama Alshibami, Ahmed Bouridane	Radix-4×4 for fast calculation of the 2-D NMNT.	ICIP (1)	2003	DBLP DOI BibTeX RDF
14	Said Boussakta, Osama Alshibami, Ahmed Bouridane	Radix-4 decimation-in-frequency algorithm for the new Mersenne number transform.	ICECS	2003	DBLP DOI BibTeX RDF
14	Lai-Sze Au, Neil Burgess	Unified Radix-4 Multiplier for GF(p) and GF(2^n).	ASAP	2003	DBLP DOI BibTeX RDF