Search results for "routability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Seonggeun Ryu, Youngsong Mun	An Optimized Scheme for Mobile IPv6 Handover Between Domains Based on AAA.	EUC	2006	DBLP DOI BibTeX RDF
21	Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee	Crosstalk- and performance-driven multilevel full-chip routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
21	Hongbing Fan, Yu-Liang Wu	Crossbar based design schemes for switch boxes and programmable interconnection networks.	ASP-DAC	2005	DBLP DOI BibTeX RDF	switch matrix, FPGA, routing, interconnection network, layout, crossbar, switch box
21	Tai-Chen Chen, Yao-Wen Chang	Multilevel full-chip gridless routing considering optical proximity correction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
21	Chiu-Wing Sham, Evangeline F. Y. Young	Congestion prediction in floorplanning.	ASP-DAC	2005	DBLP DOI BibTeX RDF
21	Eric Hsiao-Kuang Wu, Y. Ahmet Sekercioglu, Greg Daley, Sathya Narayanan	An Analytical Study of Direct and Indirect Signaling for Mobile IPv6 in Mobile-to-Mobile Communications.	ISCC	2005	DBLP DOI BibTeX RDF
21	Qinghua Liu, Malgorzata Marek-Sadowska	A congestion-driven placement framework with local congestion prediction.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	cell padding, congestion prediction, placement migration
21	María Calderón, Carlos Jesus Bernardos, Marcelo Bagnulo, Ignacio Soto	Securing Route Optimisation in NEMO.	WiOpt	2005	DBLP DOI BibTeX RDF
21	Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung	CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
21	Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar	A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
21	Ulrich Brenner, Anna Pauli, Jens Vygen	Almost optimum placement legalization by minimum cost flow and dynamic programming.	ISPD	2004	DBLP DOI BibTeX RDF	placement, legalization, minimum-cost flow, detailed placement
21	Saurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov	Unification of partitioning, placement and floorplanning.	ICCAD	2004	DBLP DOI BibTeX RDF
21	Andrew B. Kahng, Igor L. Markov, Sherief Reda	On legalization of row-based placements.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	min-cut placement, legalization, detailed placement
21	Prabhakar Kudva, Andrew Sullivan, William E. Dougherty	Measurements for structural logic synthesis optimizations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
21	Yao-Wen Chang, Kai Zhu 0001, Guang-Ming Wu, D. F. Wong 0001, C. K. Wong	Analysis of FPGA/FPIC switch modules.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	FPIC, FPGA, synthesis, layout, Computer-aided design of VLSI
21	Seokjin Lee, Hua Xiang 0001, D. F. Wong 0001, Richard Y. Sun	Wire type assignment for FPGA routing.	FPGA	2003	DBLP DOI BibTeX RDF	min-cost flow algorithm, wire type assignment, FPGA routing
21	Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu	A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees.	DATE	2003	DBLP DOI BibTeX RDF
21	Jinan Lou, Shashidhar Thakur, Shankar Krishnamoorthy, Henry S. Sheng	Estimating routing congestion using probabilistic analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
21	Russell Tessier	Fast placement approaches for FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	field-programmable gate arrays, synthesis, layout, Computer-aided design of VLSI
21	Amit Singh 0001, Malgorzata Marek-Sadowska	Efficient circuit clustering for area and power reduction in FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF
21	Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Young	Congestion Estimation with Buffer Planning in Floorplan Design.	DATE	2002	DBLP DOI BibTeX RDF
21	Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar	Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search.	FPL	2002	DBLP DOI BibTeX RDF
21	Prabhakar Kudva, Andrew Sullivan, William E. Dougherty	Metrics for structural logic synthesis.	ICCAD	2002	DBLP DOI BibTeX RDF
21	Chau-Shen Chen, TingTing Hwang, C. L. Liu 0001	Architecture driven circuit partitioning.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
21	Jinan Lou, Shankar Krishnamoorthy, Henry S. Sheng	Estimating routing congestion using probabilistic analysis.	ISPD	2001	DBLP DOI BibTeX RDF
21	Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar	A comparative study of two Boolean formulations of FPGA detailed routing constraints.	ISPD	2001	DBLP DOI BibTeX RDF
21	Yao-Wen Chang, D. F. Wong 0001, C. K. Wong	Universal switch modules for FPGA design.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF
21	Yoshihiro Konno, Kazushi Nakamura, Tatsushige Bitoh, Koji Saga, Seiken Yano	A Consistent Scan Design System for Large-Scale ASICs.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
21	Larry McMurchie, Carl Ebeling	PathFinder: A Negotiation-based Performance-driven Router for FPGAs.	FPGA	1995	DBLP DOI BibTeX RDF
21	Jason Lee, Lesley Shannon	Predicting the performance of application-specific NoCs implemented on FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	performance, FPGAs, topologies, heterogeneous, NoCs, homogeneous, application-specific, routability
21	Keith So	Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space.	ISPD	2007	DBLP DOI BibTeX RDF	negotiated congestion, routability-driven routing, FPGA
21	Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian 0001	Prediction and reduction of routing congestion.	ISPD	2006	DBLP DOI BibTeX RDF	placement, physical design, congestion, routability
21	Jurjen Westra, Patrick Groeneveld	Is probabilistic congestion estimation worthwhile?	SLIP	2005	DBLP DOI BibTeX RDF	congestion estimation, degenerate global routing, probabilistic congestion estimation, congestion, routability
21	Xiaojian Yang, Maogang Wang, Ryan Kastner, Soheil Ghiasi, Majid Sarrafzadeh	Congestion reduction during placement with provably good approximation bound.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	placement, Physical design, congestion, routability
21	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen 0001, Yici Cai, Chung-Kuan Cheng, Jun Gu	An integrated floorplanning with an efficient buffer planning algorithm.	ISPD	2003	DBLP DOI BibTeX RDF	floorplanning, buffer insertion, routability
21	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen 0001, Yici Cai, Chung-Kuan Cheng, Jun Gu	Dynamic global buffer planning optimization based on detail block locating and congestion analysis.	DAC	2003	DBLP DOI BibTeX RDF	congestion, floorplanning, buffer insertion, routability
21	Jeffrey Z. Su, Wayne Wei-Ming Dai	Post-route optimization for improved yield using a rubber-band wiring model.	ICCAD	1997	DBLP DOI BibTeX RDF	Rubber-Band, Topological Wiring Even Wire Distribution, Yield, Design for Manufacturability, Spacing, Bridge Fault, Routability, Critical Area, Layout Optimization, Routing Congestion
21	Keumog Ahn, Sartaj Sahni	NP-Hard Module Rotation Problems.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	NP-hard module rotation problems, circuit modules, performance, computational complexity, circuit layout CAD, circuit layout CAD, routability
21	Chung-Kuan Cheng, So-Zen Yao, T. C. Hu	The Orientation of Modules Based on Graph Decomposition.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	layout stage, total net length, printed circuits, computational complexity, VLSI, VLSI, graph theory, NP-complete, modules, orientation, circuit layout CAD, routability, minimum cut, graph decomposition, printed circuit board, graph problem
19	Zijun Li 0005, Ziran Zhu, Huan He, Jianli Chen	An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs.	Integr.	2024	DBLP DOI BibTeX RDF
19	Yilu Chen, Miaodi Su, Hongzhi Ding, Shaohong Weng, Zhifeng Lin, Xiqiong Bai	High-correlation 3D routability estimation for congestion-guided global routing.	J. Supercomput.	2024	DBLP DOI BibTeX RDF
19	Fangzhou Wang, Jinwei Liu, Wing Ho Lau, Haocheng Li, Evangeline F. Y. Young	FastPass: A Fast Pin Access Analysis Framework for Detailed Routability Enhancement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
19	Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Tunhou Zhang, Jiang Hu, Yiran Chen 0001	Toward Fully Automated Machine Learning for Routability Estimator Development.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
19	Hailiang Li, Yan Huo, Yan Wang, Xu Yang, Miaohui Hao, Xiao Wang	A Lightweight Inception Boosted U-Net Neural Network for Routability Prediction.	CoRR	2024	DBLP DOI BibTeX RDF
19	Bing-Xun Song, Ting Xin Lin, Yih-Lang Li	Routability Booster " Synthesize a Routing Friendly Standard Cell Library by Relaxing BEOL Resources.	ISPD	2024	DBLP DOI BibTeX RDF
19	Chien-Pang Lu, Iris Hui-Ru Jiang, Chung-Ching Peng, Mohd Mawardi Mohd Razha, Alessandro Uber	Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization.	ISPD	2024	DBLP DOI BibTeX RDF
19	Jingsong Chen, Jian Kuang 0001, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young	PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
19	Daijoon Hyun, Sunwha Koh, Younggwang Jung, Taeyoung Kim, Youngsoo Shin	Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
19	Ping-Wei Huang, Yao-Wen Chang	Routability-driven Power/Ground Network Optimization Based on Machine Learning.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
19	Jonathan W. Greene	FPGA Mux Usage and Routability Estimates without Explicit Routing.	FPGA	2023	DBLP DOI BibTeX RDF
19	Daeyeon Kim, Jakang Lee, Seokhyeong Kang	Routability Prediction using Deep Hierarchical Classification and Regression.	DATE	2023	DBLP DOI BibTeX RDF
19	Andrew David Gunter, Steve Wilton	Reformulating the FPGA Routability Prediction Problem with Machine Learning.	FCCM	2023	DBLP DOI BibTeX RDF
19	Jai-Ming Lin, Tsung-Chun Tsai, Rui-Ting Shen	Routability-Driven Orientation-Aware Analytical Placement for System in Package.	ICCAD	2023	DBLP DOI BibTeX RDF
19	Seonghyeon Park, Daeyeon Kim, Seongbin Kwon, Seokhyeong Kang	Routability Prediction and Optimization Using Explainable AI.	ICCAD	2023	DBLP DOI BibTeX RDF
19	Xun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang	Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms.	ICCAD	2023	DBLP DOI BibTeX RDF
19	Younggwang Jung, Daijoon Hyun, Soyoon Choi, Youngsoo Shin	Power Distribution Network Optimization Using HLA-GCN for Routability Enhancement.	ICCAD	2023	DBLP DOI BibTeX RDF
19	Wonjae Lee, Insu Cho, Gangmin Cho, Youngsoo Shin	Routability-Driven Power Distribution Network Synthesis with IR-Drop Budgeting.	MLCAD	2023	DBLP DOI BibTeX RDF
19	Seonghyeon Park, Daeyeon Kim, Seokhyeong Kang	Invited: Acceleration on Physical Design: Machine Learning-based Routability Optimization.	SLIP	2023	DBLP DOI BibTeX RDF
19	Chieh-Yu Cheng, Ting-Chi Wang	Routability-aware Placement Guidance Generation for Mixed-size Designs.	ISQED	2023	DBLP DOI BibTeX RDF
19	Zhijie Cai, Peng Zou, Zhengtao Wu, Xingyu Tong, Jun Yu 0010, Jianli Chen, Yao-Wen Chang	PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration.	DAC	2023	DBLP DOI BibTeX RDF
19	Jai-Ming Lin, Liang-Chi Zane, Min-Chia Tsai, Yung-Chen Chen, Che-Li Lin, Chen-Fa Tsai	PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
19	Chung-Kuan Cheng, Andrew B. Kahng, Hayoung Kim, Minsoo Kim, Daeyeal Lee, Dongwon Park, Mingyu Woo	PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
19	Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li 0005, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen 0001	Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data.	CoRR	2022	DBLP DOI BibTeX RDF
19	Sheiny Fabre Almeida, José Luís Güntzel, Laleh Behjat, Cristina Meinhardt	Routability-Driven Detailed Placement Using Reinforcement Learning.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
19	Hao Chen 0059, Walker J. Turner, David Z. Pan, Haoxing Ren	Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories.	DATE	2022	DBLP DOI BibTeX RDF
19	Miaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou, Zhonghua Zhou, Yilu Chen, Jianli Chen, Yao-Wen Chang	High-Correlation 3D Routability Estimation for Congestion-guided Global Routing.	ASP-DAC	2022	DBLP DOI BibTeX RDF
19	Jiayuan He 0003, Udit Agarwal, Yihang Yang, Rajit Manohar, Keshav Pingali	SPRoute 2.0: A detailed-routability-driven deterministic parallel global router with soft capacity.	ASP-DAC	2022	DBLP DOI BibTeX RDF
19	Jai-Ming Lin, Hao-Yuan Hsieh, Hsuan Kung, Hao-Jia Lin	Routability-Driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs.	ICCAD	2022	DBLP DOI BibTeX RDF
19	Yuxuan Pan, Zhonghua Zhou, André Ivanov	Routability-driven Global Routing with 3D Congestion Estimation Using a Customized Neural Network.	ISQED	2022	DBLP DOI BibTeX RDF
19	Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li 0005, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen 0001	Towards collaborative intelligence: routability estimation based on decentralized private data.	DAC	2022	DBLP DOI BibTeX RDF
19	Abeer Y. Al-Hyari, Hannah Szentimrey, Ahmed Shamli, Timothy Martin, Gary Gréwal, Shawki Areibi	A Deep Learning Framework to Predict Routability for FPGA Circuit Placement.	ACM Trans. Reconfigurable Technol. Syst.	2021	DBLP DOI BibTeX RDF
19	Song Mu, Yi Zeng, Bo Wang	Routability-Enhanced Scheduling for Application Mapping on CGRAs.	IEEE Access	2021	DBLP DOI BibTeX RDF
19	Jia-Hong Chang, Shao-Yun Fang	Placement-guided pin layout substitution for routability optimization.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
19	Daeyeon Kim, Hyun-jeong Kwon, Sung-Yun Lee, Seungwon Kim, Mingyu Woo, Seokhyeong Kang	Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator.	DATE	2021	DBLP DOI BibTeX RDF
19	Siting Liu 0002, Qi Sun 0002, Peiyu Liao, Yibo Lin, Bei Yu 0001	Global Placement with Deep Learning-Enabled Explicit Routability Optimization.	DATE	2021	DBLP DOI BibTeX RDF
19	Chen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen 0001	Automatic Routability Predictor Development Using Neural Architecture Search.	ICCAD	2021	DBLP DOI BibTeX RDF
19	Jai-Ming Lin, Chung-Wei Huang, Liang-Chi Zane, Min-Chia Tsai, Che-Li Lin, Chen-Fa Tsai	Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs.	ICCAD	2021	DBLP DOI BibTeX RDF
19	Timothy Martin, Shawki Areibi, Gary Gréwal	Effective Machine-Learning Models for Predicting Routability During FPGA Placement.	MLCAD	2021	DBLP DOI BibTeX RDF
19	Sunwha Koh, Younggwang Jung, Daijoon Hyun, Youngsoo Shin	Routability Optimization for Extreme Aspect Ratio Design Using Convolutional Neural Network.	ISCAS	2021	DBLP DOI BibTeX RDF
19	Dongwon Park, Daeyeal Lee, Ilgweon Kang, Chester Holtz, Sicun Gao, Bill Lin 0001, Chung-Kuan Cheng	Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
19	Hannah Szentimrey, Abeer Y. Al-Hyari, Jérémy Foxcroft, Timothy Martin, David Noel, Gary William Grewal, Shawki Areibi	Machine Learning for Congestion Management and Routability Prediction within FPGA Placement.	ACM Trans. Design Autom. Electr. Syst.	2020	DBLP DOI BibTeX RDF
19	Jingyu Pan, Chen-Chia Chang, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen 0001	Automatic Routability Predictor Development Using Neural Architecture Search.	CoRR	2020	DBLP BibTeX RDF
19	Jingsong Chen, Jian Kuang 0001, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young	PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning.	ICCAD	2020	DBLP DOI BibTeX RDF
19	Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Dongwon Park	A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT.	ICCAD	2020	DBLP DOI BibTeX RDF
19	Run-Yi Wang, Yao-Wen Chang	Routability-Aware Pin Access Optimization for Monolithic 3D Designs.	ICCAD	2020	DBLP DOI BibTeX RDF
19	Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young	CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model.	DAC	2020	DBLP DOI BibTeX RDF
19	Abeer Y. Al-Hyari, Ziad Abuowaimer, Timothy Martin, Gary Gréwal, Shawki Areibi, Anthony Vannelli	Novel Congestion-estimation and Routability-prediction Methods based on Machine Learning for Modern FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2019	DBLP DOI BibTeX RDF
19	Jai-Ming Lin, You-Lun Deng, Szu-Ting Li, Bo-Heng Yu, Li-Yen Chang, Te-Wei Peng	Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
19	Prasun Datta, Shyamapada Mukherjee	Architecture-aware routability-driven placer for large-scale mixed-size designs.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
19	Yuan Wang, Martin A. Trefzer, Simon J. Bale, James Alfred Walker, Andy M. Tyrrell	Multi-objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs.	IET Comput. Digit. Tech.	2019	DBLP DOI BibTeX RDF
19	Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Lutong Wang	RePlAce: Advancing Solution Quality and Routability Validation in Global Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
19	Wei-Kai Cheng, Chih-Shuan Wu	Machine Learning Techniques for Building and Evaluation of Routability-driven Macro Placement.	ICCE-TW	2019	DBLP DOI BibTeX RDF
19	Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing Ren, Shao-Yun Fang, Yiran Chen 0001, Jiang Hu	Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model.	DATE	2019	DBLP DOI BibTeX RDF
19	Abeer Alhyari, Ahmed Shamli, Ziad Abuwaimer, Shawki Areibi, Gary Gréwal	A Deep Learning Framework to Predict Routability for FPGA Circuit Placement.	FPL	2019	DBLP DOI BibTeX RDF
19	Dongwon Park, Ilgweon Kang, Yeseong Kim, Sicun Gao, Bill Lin 0001, Chung-Kuan Cheng	ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques.	ISPD	2019	DBLP DOI BibTeX RDF
19	Genggeng Liu, Zhen Zhuang, Wenzhong Guo, Ting-Chi Wang	RDTA: An Efficient Routability-Driven Track Assignment Algorithm.	ACM Great Lakes Symposium on VLSI	2019	DBLP DOI BibTeX RDF
19	Zhonghua Zhou, Sunmeet Chahal, Tsung-Yi Ho, André Ivanov	Supervised-Learning Congestion Predictor For Routability-Driven Global Routing.	VLSI-DAT	2019	DBLP DOI BibTeX RDF
19	Jai-Ming Lin, Szu-Ting Li, Yi-Ting Wang	Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros.	DAC	2019	DBLP DOI BibTeX RDF
19	Oleg Petelin, Vaughn Betz	Wotan: Evaluating FPGA Architecture Routability without Benchmarks.	ACM Trans. Reconfigurable Technol. Syst.	2018	DBLP DOI BibTeX RDF
19	Wuxi Li, Shounak Dhar, David Z. Pan	UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF