Search results for "sequence-pair"

Found 115 publication records. Showing 115 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Saurabh N. Adya, Igor L. Markov	Fixed-outline floorplanning: enabling hierarchical design.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
6	Linfu Xiao, Evangeline F. Y. Young	Analog placement with common centroid and 1-D symmetry constraints.	ASP-DAC	2009	DBLP DOI BibTeX RDF
6	Itaru Tatsumi, Hitoshi Habe, Masatsugu Kidode	Context-oriented Layout Optimization of Large-Print Textbooks.	ICDAR	2009	DBLP DOI BibTeX RDF
6	Minsik Cho, David Z. Pan	Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
6	Song Chen 0001, Takeshi Yoshimura	Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
6	Ning Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake	Multi-SP: A Representation with United Rectangles for Analog Placement and Routing.	ISVLSI	2006	DBLP DOI BibTeX RDF
6	Nida Gökçe, Mubariz Eminov, Fevzi Belli	Coverage-Based, Prioritized Testing Using Neural Network Clustering.	ISCIS	2006	DBLP DOI BibTeX RDF	pair-wise coverage, importance degree, test ranking, clustering, competitive learning, Event sequence
6	Song Chen 0001, Takeshi Yoshimura	On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence.	APCCAS	2006	DBLP DOI BibTeX RDF
6	Satoshi Hashimoto, Kazunori Haruyama, Taro Nakamura, Toyohisa Nakajima, Yuko Osana	Office layout support system using island model genetic algorithm.	Congress on Evolutionary Computation	2005	DBLP DOI BibTeX RDF
6	Jill H. Y. Law, Evangeline F. Y. Young	Multi-bend bus driven floorplanning.	ISPD	2005	DBLP DOI BibTeX RDF	bus planning, floorplanning, VLSI CAD
6	Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh	Floorplanning with clock tree estimation.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
6	Rong Liu, Sheqin Dong, Xianlong Hong	Fixed-outline floorplanning based on common subsequence.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	common subsequence, floorplanning, fixed-outline
6	Shinn-Ying Ho, Shinn-Jang Ho, Yi-Kuang Lin, W. C.-C. Chu	An orthogonal simulated annealing algorithm for large floorplanning problems.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
6	Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani	Multi-level placement with circuit schema based clustering in analog IC layouts.	ASP-DAC	2004	DBLP DOI BibTeX RDF
6	Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong	Handling soft modules in general nonslicing floorplan usingLagrangian relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF

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