Search results for "verilog-HDL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Byung Cheol Song, Kang Wook Chun	Multi-resolution block matching algorithm and its VLSI architecture for fast motion estimation in an MPEG-2 video encoder.	IEEE Trans. Circuits Syst. Video Technol.	2004	DBLP DOI BibTeX RDF
19	Bin Sheng, Wen Gao 0001, Di Wu 0022	An implemented architecture of deblocking filter for H.264/AVC.	ICIP	2004	DBLP DOI BibTeX RDF
19	Jen-Shiun Chiang, Min-Shiou Tsai	A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	floating-point division, new Svoboda-Tung division, radix-4, Svoboda-Tung division, computer arithmetic, prescaling, signed digit number system
19	Jae Sung Lee, Myung Hoon Sunwoo	Design of New DSP Instructions and Their Hardware Architecture for High-Speed FFT.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	application specific digital signal processor, DMT, fast Fourier transform, OFDM
19	Amir K. Daneshbeh, M. Anwarul Hasan	A Unidirectional Bit Serial Systolic Architecture for Double-Basis Division over GF(2m).	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
19	Won Jay Song, Won Hee Kim, Bo Gwan Kim, Byung-Ha Ahn, Mun Kee Choi, Minho Kang	Conditional Access Module Systems for Digital Contents Protection Based on Hybrid/Fiber/Coax CATV Networks.	ISCIS	2003	DBLP DOI BibTeX RDF
19	Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-Seog Choi	54x54-bit radix-4 multiplier based on modified booth algorithm.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	compressor, adder, multiplier, booth encoder, wallace tree
19	Jacir Luiz Bordim, Yasuaki Ito, Koji Nakano	Accelerating the CKY Parsing Using FPGAs.	HiPC	2002	DBLP DOI BibTeX RDF
19	Hong Peng, Yassine Mokhtari, Sofiène Tahar	Environment Synthesis for Compositional Model Checking.	ICCD	2002	DBLP DOI BibTeX RDF
19	Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata	A cellular-automaton-type image extraction algorithm and its implementation using an FPGA.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
19	Taek Won Kwon, Chang-Seok You, Won-Seok Heo, Yong-Kyu Kang, Jun Rim Choi	Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
19	Keishi Chikamura, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura	IEEE1394 system simulation environment and a design of its link layer controller.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
19	Dae Won Kim, Taek Won Kwon, Jung Min Seo, Jae Kun Yu, Kyu Lee, Jung Hee Suk, Jun Rim Choi	A compatible DCT/IDCT architecture using hardwired distributed arithmetic.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
19	Shengchao Qin, Zongyan Qiu, Jifeng He 0001	Constructing Hardware/Software Interface Using Protocol Converters.	APAQS	2001	DBLP DOI BibTeX RDF	protocol converter, program algebra, Hardware/software partition
19	Oskar Mencer, Luc Séméria, Martin Morf, Jean-Marc Delosme	Application of Reconfigurable CORDIC Architectures.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
19	Achim Freimann	Framework for High-Level Power Estimation of Signal Processing Architectures.	PATMOS	2000	DBLP DOI BibTeX RDF
19	Tsutomu Yoshinaga, Masaya Hayashi, Maki Horita, Sayuri Nakamura, Kanemitsu Ootsu, Takanobu Baba	Recover-X: An Adaptive Router with Limited Escape Channels.	ICPADS	2000	DBLP DOI BibTeX RDF	wormhole routers, adaptive routing, hardware description language, hardware cost, deadlock recovery
19	Steven Trimberger, Raymond Pang, Amit Singh	A 12 Gbps DES Encryptor/Decryptor Core in an FPGA.	CHES	2000	DBLP DOI BibTeX RDF
19	Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta	An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection.	ASP-DAC	1999	DBLP DOI BibTeX RDF
19	C.-C. Wang, C. J. Huang, G.-C. Lin	A chip design of radix-4/2 64b/32b signed and unsigned integer divider using Compass cell library.	ISCAS (1)	1999	DBLP DOI BibTeX RDF