Search results for "register"

Hits ?▲	Authors	Title	Venue	Year	Link
11	Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini	Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra.	DATE	2021	DBLP DOI BibTeX RDF
11	Rozhin Yasaei, Shih-Yuan Yu, Mohammad Abdullah Al Faruque	GNN4TJ: Graph Neural Networks for Hardware Trojan Detection at Register Transfer Level.	DATE	2021	DBLP DOI BibTeX RDF
11	Ahmad M. Radaideh, Paul V. Gratz	CMRC: Comprehensive Microarchitectural Register Coalescing for GPGPUs.	DATE	2021	DBLP DOI BibTeX RDF
11	Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai	Multiport Register File Design for High-Performance Embedded Cores.	MCSoC	2021	DBLP DOI BibTeX RDF
11	Mikolaj Bojanczyk, Bartek Klin, Joshua Moerman	Orbit-Finite-Dimensional Vector Spaces and Weighted Register Automata.	LICS	2021	DBLP DOI BibTeX RDF
11	Cinthia Paola Pascual Cáceres, José Vicente Berná-Martínez, Francisco Maciá Pérez, Iren Lorenzo-Fonseca	Blockchain Validity Register for Healthcare Environments.	BLOCKCHAIN	2021	DBLP DOI BibTeX RDF
11	Fajar Wijitrisnanto, Sarwono Sutikno, Septafiansyah Dwi Putra	Efficient Machine Learning Model for Hardware Trojan Detection on Register Transfer Level.	ICSPIS	2021	DBLP DOI BibTeX RDF
11	Changming Cui, Junlin Huang	A 3DIC interconnect interface test and repair scheme based on Hybrid IEEE1838 Die Wrapper Register and BIST circuit.	ETS	2021	DBLP DOI BibTeX RDF
11	Wojciech Czerwinski, Antoine Mottet, Karin Quaas	New Techniques for Universality in Unambiguous Register Automata.	ICALP	2021	DBLP DOI BibTeX RDF
11	Simon Dierl, Falk Howar	A Taxonomy and Reductions for Common Register Automata Formalisms.	Model Checking, Synthesis, and Learning	2021	DBLP DOI BibTeX RDF
11	Haining Wang, Xin Xie, Allen Riddell	The Challenge of Vernacular and Classical Chinese Cross-Register Authorship Attribution.	CHR	2021	DBLP BibTeX RDF
11	Xiu-Wen Ye, Yuan Yuan Pan, Yu-Yan Peng, GuiQing Tan, GinQing Tan	Big Data Grave Register Information Management System Outside Cemeteries Under Internet of Things.	SGIoT	2021	DBLP DOI BibTeX RDF
11	Peer Adelt, Bastian Koppelmann, Wolfgang Mueller, Christoph Scheytt	Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.	MBMV	2021	DBLP BibTeX RDF
11	Vinicius Vielmo Cogo, Alysson Bessani	Brief Announcement: Auditable Register Emulations.	DISC	2021	DBLP DOI BibTeX RDF
11	Eyüp Eröz, Erkan Tanyildizi, Fatih Özkaynak	Determination of Suitable Configuration Parameters for Linear Feedback Shift Register using Binary Bat Optimization Algorithm.	EUROCON	2021	DBLP DOI BibTeX RDF
11	Martin Kostal, Michal Sojka	Register file management for PRET machines: work-in-progress.	CODES+ISSS	2021	DBLP DOI BibTeX RDF
11	Jade Mekki, Delphine Battistelli, Nicolas Béchet, Gwénolé Lecorvé	TREMoLo : un corpus multi-étiquettes de tweets en français pour la caractérisation des registres de langue (TREMoLo : a Multi-Label Corpus of French Tweets for Language Register Characterization).	TALN (1)	2021	DBLP BibTeX RDF
11	Ilya Tuzov, Pablo Andreu, Laura Medina, Tomás Picornell, Antonio Robles, Pedro López 0001, José Flich, Carles Hernández 0001	Improving the Robustness of Redundant Execution with Register File Randomization.	ICCAD	2021	DBLP DOI BibTeX RDF
11	Subhajit Dutta Chowdhury, Kaixin Yang, Pierluigi Nuzzo 0002	ReIGNN: State Register Identification Using Graph Neural Networks for Circuit Reverse Engineering.	ICCAD	2021	DBLP DOI BibTeX RDF
11	Vassos Hadzilacos, Xing Hu 0009, Sam Toueg	On Register Linearizability and Termination.	PODC	2021	DBLP DOI BibTeX RDF
11	Hidehiro Fujiwara, Yi-Hsin Nien, Chih-Yu Lin, Hsien-Yu Pan, Hao-Wen Hsu, Shin-Rung Wu, Yao-Yi Liu, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang	A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue.	ISSCC	2021	DBLP DOI BibTeX RDF
11	Léo Exibard, Emmanuel Filiot, Ayrat Khalimov 0001	Church Synthesis on Register Automata over Linearly Ordered Data Domains.	STACS	2021	DBLP DOI BibTeX RDF
11	Corentin Barloy, Lorenzo Clemente	Bidimensional Linear Recursive Sequences and Universality of Unambiguous Register Automata.	STACS	2021	DBLP DOI BibTeX RDF
11	Liu Liu 0009, Hongdong Li, Haodong Yao, Ruyi Zha	PluckerNet: Learn To Register 3D Line Reconstructions.	CVPR	2021	DBLP BibTeX RDF
11	Bernhard Göschlberger, Dragos Deliu	BiRank vs PageRank: Using SNA on Company Register Data for Fiscal Risk Prediction.	SNAMS	2021	DBLP DOI BibTeX RDF
11	Yongwon Shin, Hyojin Sung	Hybrid Register Allocation with Spill Cost and Pattern Guided Optimization.	LCPC	2021	DBLP DOI BibTeX RDF
11	Uday Kiran Naidu Ekkurthi, Venkatesh Dasari, Jyoshnavi Akiri, Chua-Chin Wang	A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop.	ISCAS	2021	DBLP DOI BibTeX RDF
11	Adrian Benton, Hanyang Li, Igor Malioutov	Cross-Register Projection for Headline Part of Speech Tagging.	EMNLP (1)	2021	DBLP DOI BibTeX RDF
11	Aiqing Wu, Mengni Bie, Longmei Nan, Wei Li 0131	Effective Register Allocation for Configurable VLIW Crypto-Processor.	ASICON	2021	DBLP DOI BibTeX RDF
11	Endri Kaja, Nicolas Gerlin, Mounika Vaddeboina, Luis Rivas, Sebastian Siegfried Prebeck, Zhao Han, Keerthikumara Devarajegowda, Wolfgang Ecker	Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models.	DFT	2021	DBLP DOI BibTeX RDF
11	Hikaru Takayashiki, Masayuki Sato 0001, Kazuhiko Komatsu, Hiroaki Kobayashi	Register Flush-free Runahead Execution for Modern Vector Processors.	SBAC-PAD	2021	DBLP DOI BibTeX RDF
11	Anupam Yadav	Power Optimization of 8-bit Register on Ultra Scale FPGA using Low Voltage CMOS I/O Standard.	ICCCNT	2021	DBLP DOI BibTeX RDF
11	Nusrat Farzana, Avinash Ayalasomayajula, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor	SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level.	VTS	2021	DBLP DOI BibTeX RDF
11	Samuel Rönnqvist, Valtteri Skantsi, Miika Oinonen, Veronika Laippala	Multilingual and Zero-Shot is Closing in on Monolingual Web Register Classification.	NoDaLiDa	2021	DBLP BibTeX RDF
11	Leandro L. S. França, Julierme Pinheiro, Joel B. Passos, José Luiz Portugal	TopoGeo: a data model for elaboration of cadastral survey plans and land register documents.	GEOINFO	2021	DBLP BibTeX RDF
11	Krisztián Bálint	The connection of a Blockchain with Students' Attendance Register based on Security Cameras.	SISY	2021	DBLP DOI BibTeX RDF
11	Slawomir Lasota 0001, Mohnish Pattathurajan	Parikh Images of Register Automata.	FSTTCS	2021	DBLP DOI BibTeX RDF
11	Ayazulla Khan Patan, Dimitrios Stathis 0001, Pudi Dhilleswararao, Yu Yang, Srinivas Boppu, Ahmed Hemani	Design and Implementation of Optimized Register File for Streaming Applications.	VDAT	2021	DBLP DOI BibTeX RDF
11	Yu Fu, Wei Wang 0314, Lingjia Meng, Qiongxiao Wang, Yuan Zhao, Jingqiang Lin	VIRSA: Vectorized In-Register RSA Computation with Memory Disclosure Resistance.	ICICS (1)	2021	DBLP DOI BibTeX RDF
11	Ana Paula Chaves 0001, Marco Aurélio Gerosa	The Impact of Chatbot Linguistic Register on User Perceptions: A Replication Study.	CONVERSATIONS	2021	DBLP DOI BibTeX RDF
11	Noushin Ghaderi, Andrea Adami, Leandro Lorenzelli	A low-power 6-bit successive approximation register ADC using a new split capacitor array method.	APCCAS	2021	DBLP DOI BibTeX RDF
11	Geonhwa Jeong, Eric Qin 0001, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna	RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU.	DAC	2021	DBLP DOI BibTeX RDF
11	Johannes Müller, Mohammad Rahmani Fadiheh, Anna Lena Duque Antón, Thomas Eisenbarth 0001, Dominik Stoffel, Wolfgang Kunz	A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level.	DAC	2021	DBLP DOI BibTeX RDF
11	Shunning Jiang, Yanghui Ou, Peitian Pan, Christopher Batten	UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling.	DAC	2021	DBLP DOI BibTeX RDF
11	Orfeas Panetas-Felouris, Spyridon Vlassis	A novel time register with process and temperature calibration.	MOCAST	2021	DBLP DOI BibTeX RDF
11	Hodjat Asghari Esfeden	Enhanced Register Data-Flow Techniques for High-Performance, Energy-Efficient GPUs.		2021	RDF
11	Laure Daviaud	Register complexity and determinisation of max-plus automata.	ACM SIGLOG News	2020	DBLP DOI BibTeX RDF
11	Kenshu Seto	Shift Register Initialization in Scalar Replacement for Reducing Code Size.	IPSJ Trans. Syst. LSI Des. Methodol.	2020	DBLP DOI BibTeX RDF
11	Yasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda, Hanpei Koike	Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping.	Integr.	2020	DBLP DOI BibTeX RDF
11	Arindrajit Ghosh, Uddalak Bhattacharya, Manish Kumar, Swapna Banerjee	Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology.	Integr.	2020	DBLP DOI BibTeX RDF
11	Won Jeon, Jun Hyun Park, Yoonsoo Kim, Gunjae Koo, Won Woo Ro	Hi-End: Hierarchical, Endurance-Aware STT-MRAM-Based Register File for Energy-Efficient GPUs.	IEEE Access	2020	DBLP DOI BibTeX RDF
11	Jian Chen, Fan Yu, Zhiqiang Wang, Lin Lin	Multichannel Ultrasound Focusing Delay Control Method Based on Variable-Length Shift Register for Airborne Ultrasound Tactile Feedback.	IEEE Access	2020	DBLP DOI BibTeX RDF
11	Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero	DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files.	IEEE Access	2020	DBLP DOI BibTeX RDF
11	Siva Nishok Dhanuskodi, Samuel Allen, Daniel E. Holcomb	Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
11	Suraj Pattanaik	A novel approach to design a digital clock triggered modified pulse latch for 16-bit shift register.	Int. J. Intell. Def. Support Syst.	2020	DBLP DOI BibTeX RDF
11	Jun-Cheol Jeon	Low-complexity QCA universal shift register design using multiplexer and D flip-flop based on electronic correlations.	J. Supercomput.	2020	DBLP DOI BibTeX RDF
11	Mohammad Samadi Gharajeh, Majid Haghparast	Towards designing quantum reversible 32-bit MIPS register file.	Int. J. High Perform. Syst. Archit.	2020	DBLP DOI BibTeX RDF
11	Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Chee Hoo Kok	Register-Transfer-Level Features for Machine-Learning-Based Hardware Trojan Detection.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2020	DBLP BibTeX RDF
11	Ryoma Senda, Yoshiaki Takata, Hiroyuki Seki	Generalized Register Context-Free Grammars.	IEICE Trans. Inf. Syst.	2020	DBLP BibTeX RDF
11	Ihsen Alouani, Hamzeh Ahangari, Ozcan Ozturk 0001, Smaïl Niar	Power-efficient reliable register file for aggressive-environment applications.	IET Comput. Digit. Tech.	2020	DBLP DOI BibTeX RDF
11	Shouping Li, Yang Guo, Jianjun Chen, Bin Liang	A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm.	Symmetry	2020	DBLP DOI BibTeX RDF
11	Xiayang Wang, Fuqian Huang, Haibo Chen 0001	Secure and Efficient Control Data Isolation with Register-Based Data Cloaking.	IEEE Trans. Computers	2020	DBLP DOI BibTeX RDF
11	Renkui Hou, Chu-Ren Huang, Kathleen Ahrens, Sophia Yat Mei Lee	Linguistic characteristics of Chinese register based on the Menzerath - Altmann law and text clustering.	Digit. Scholarsh. Humanit.	2020	DBLP DOI BibTeX RDF
11	Alireza Yazdanpanah, Sohrab Sajadimanesh, Saeed Safari	EREER: Energy-aware register file and execution unit using exploiting redundancy in GPGPUs.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
11	Quan Deng, Youtao Zhang, Zhenyu Zhao, Shuzheng Zhang, Minxuan Zhang, Jun Yang 0002	FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
11	Kai Yang, Qiang Li 0007, Xiaodong Lin 0001, Xin Chen, Limin Sun	iFinger: Intrusion Detection in Industrial Control Systems via Register-Based Fingerprinting.	IEEE J. Sel. Areas Commun.	2020	DBLP DOI BibTeX RDF
11	Mahdi Momeni, Mohammad Yavari	Shifting the sampled input signal in successive approximation register analog-to-digital converters to reduce the digital-to-analog converter switching energy and area.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
11	Gaurav Sharma 0008, Lava Bhargava, Vinod Kumar 0016	Automated Bug Resistant Test Intent with Register Header Database for Optimized Verification.	J. Electron. Test.	2020	DBLP DOI BibTeX RDF
11	R. Murugasami, U. S. Ragupathy 0001	Performance analysis of clock pulse generators and design of low power area efficient shift register using multiplexer based clock pulse generator.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
11	Mingyang Gong, Haichun Zhang, Chao Wang 0096, Qiaoling Tong, Zhenglin Liu	Design and implementation of robust and low-cost SRAM PUF using PMOS and linear shift register extractor.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
11	Alexandra Angerd, Erik Sintorn, Per Stenström	A GPU Register File using Static Data Compression.	CoRR	2020	DBLP BibTeX RDF
11	Mohammad Sadrosadati, Amirhossein Mirhosseini, Ali Hajiabadi, Seyed Borna Ehsani, Hajar Falahati, Hamid Sarbazi-Azad, Mario Drumond, Babak Falsafi, Rachata Ausavarungnirun, Onur Mutlu	Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation.	CoRR	2020	DBLP BibTeX RDF
11	Ian Rogers	Efficient global register allocation.	CoRR	2020	DBLP BibTeX RDF
11	Léo Exibard, Emmanuel Filiot, Ayrat Khalimov 0001	Register Games on Infinite Ordered Data Domains.	CoRR	2020	DBLP BibTeX RDF
11	Bharat Garhewal, Frits W. Vaandrager, Falk Howar, Timo Schrijvers, Toon Lenaerts, Rob Smits	Grey-Box Learning of Register Automata.	CoRR	2020	DBLP BibTeX RDF
11	Amir Hossein Sayyad Abdi, Mohsen Sharifi	Avoiding Register Overflow in the Bakery Algorithm.	CoRR	2020	DBLP BibTeX RDF
11	Andrzej S. Murawski, Steven J. Ramsay, Nikos Tzevelekos	Bisimilarity in fresh-register automata.	CoRR	2020	DBLP BibTeX RDF
11	Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini	Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra.	CoRR	2020	DBLP BibTeX RDF
11	Paul Ryan, Harshvardhan J. Pandit, Rob Brennan	Towards a Semantic Model of the GDPR Register of Processing Activities.	CoRR	2020	DBLP BibTeX RDF
11	Frits W. Vaandrager, Abhisek Midya	A Myhill-Nerode Theorem for Register Automata and Symbolic Trace Languages.	CoRR	2020	DBLP BibTeX RDF
11	Liu Liu 0009, Hongdong Li, Haodong Yao, Ruyi Zha	PlueckerNet: Learn to Register 3D Line Reconstructions.	CoRR	2020	DBLP BibTeX RDF
11	Gaëtan Douéneau-Tabot, Emmanuel Filiot, Paul Gastin	Register transducers are marble transducers.	CoRR	2020	DBLP BibTeX RDF
11	Carlo Galli, Stefano Guizzardi	Change in Format, Register and Narration Style in the Biomedical Literature: A 1948 Example.	Publ.	2020	DBLP DOI BibTeX RDF
11	Wen Shi, Tom Kelsey, Frank M. Sullivan	Efficient identification of patients eligible for clinical studies using case-based reasoning on Scottish Health Research register (SHARE).	BMC Medical Informatics Decis. Mak.	2020	DBLP DOI BibTeX RDF
11	Karoliina Lehtinen, Udi Boker	Register Games.	Log. Methods Comput. Sci.	2020	DBLP DOI BibTeX RDF
11	Shaull Almagor, Michaël Cadilhac, Filip Mazowiecki, Guillermo A. Pérez 0001	Weak Cost Register Automata are Still Powerful.	Int. J. Found. Comput. Sci.	2020	DBLP DOI BibTeX RDF
11	Florian Giesemann, Lukas Gerlach 0001, Guillermo Payá Vayá	Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW Compilers.	J. Signal Process. Syst.	2020	DBLP DOI BibTeX RDF
11	Serena Coetzee, Martijn Odijk, Bastiaan van Loenen, Janette Storm, Jantien E. Stoter	Stakeholder analysis of the governance framework of a national SDI dataset - whose needs are met in the buildings and address register of the Netherlands?	Int. J. Digit. Earth	2020	DBLP DOI BibTeX RDF
11	Chunguang Huang, Qun Ding	Performance of Finite Precision on Discrete Chaotic Map Based on a Feedback Shift Register.	Complex.	2020	DBLP DOI BibTeX RDF
11	Patrick Bahr, Graham Hutton	Calculating correct compilers II: Return of the register machines.	J. Funct. Program.	2020	DBLP DOI BibTeX RDF
11	Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang	Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
11	Youngbog Yoon, Chulwoo Kim	An Area-Efficient and Wide-Range Inter-Signal Skew Compensation Scheme With the Embedded Bypass Control Register Operating as a Binary Search Algorithm for DRAM Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
11	Zhenwei Zhang, Yi Shan, Yemin Dong	A 16 bit 200 kS/s successive approximation register ADC with foreground on-chip self-calibration.	IEICE Electron. Express	2020	DBLP DOI BibTeX RDF
11	Shailendra Kumar Tripathi, Bhupendra Gupta, K. K. Soundra Pandian	The Shortest Register With Non-Linear Update for Generating a Given Finite or Periodic Sequence.	IEEE Commun. Lett.	2020	DBLP DOI BibTeX RDF
11	Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith	Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits.	MWSCAS	2020	DBLP DOI BibTeX RDF
11	Nadja Piedade de Antônio, Renata Mendes de Araujo, Marcelo Fornazin, Rodrigo Pereira dos Santos	Scaling the Technology for Income Transfers: the trajectory of "Bolsa Família" Unique Register CadÚnico.	AMCIS	2020	DBLP BibTeX RDF
11	Paul Ryan, Harshvardhan J. Pandit, Rob Brennan	A Common Semantic Model of the GDPR Register of Processing Activities.	JURIX	2020	DBLP DOI BibTeX RDF
11	Oron Port, Yoav Etsion	Hardware Description Beyond Register-Transfer Level Languages.	FPGA	2020	DBLP DOI BibTeX RDF
11	Frits W. Vaandrager, Abhisek Midya	A Myhill-Nerode Theorem for Register Automata and Symbolic Trace Languages.	ICTAC	2020	DBLP DOI BibTeX RDF
11	Chandan Karfa, Ramanuj Chouksey, Christian Pilato, Siddharth Garg, Ramesh Karri	Is Register Transfer Level Locking Secure?	DATE	2020	DBLP DOI BibTeX RDF