Search results for "register"

Hits ?▲	Authors	Title	Venue	Year	Link
11	Marcio Gonçalves, Ivan Peter Lamb, Raphael Martins Brum, José Rodrigo Azambuja	Evaluating the Impact of Accuracy Relaxation in the Reliability of GPU Register Files.	ICECS	2019	DBLP DOI BibTeX RDF
11	Ya-Chu Chang, Tung-Wei Lin, Iris Hui-Ru Jiang, Gi-Joon Nam	Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing.	ISPD	2019	DBLP DOI BibTeX RDF
11	Giovanni Rinaldi, Marco Manca 0002	The International Register of Ideas and Innovations. A Visionary Social Network to Develop Innovation and Protect IP Using Blockchain and Proof-of-Originality Algorithm.	INSCI	2019	DBLP DOI BibTeX RDF
11	Cinzia Daraio, Renato Bruni, Giuseppe Catalano, Giorgio Matteucci, Alessandro Daraio, Monica Scannapieco, Daniel Wagner-Schuster, Benedetto Lepori	European Tertiary Education Register (ETER): Evolution of the Data Quality Approach.	ISSI	2019	DBLP BibTeX RDF
11	Elea Giménez-Toledo, Gunnar Sivertsen, Jorge Mañana-Rodríguez	International Register of Academic Book Publishers (IRAP): overview, current state and future challenges.	ISSI	2019	DBLP BibTeX RDF
11	Artiom Alhazov, Rudolf Freund, Sergiu Ivanov 0001	Register machines over groups.	NCMA	2019	DBLP BibTeX RDF
11	Jason Portillo, Travis Meade, John Hacker, Shaojie Zhang, Yier Jin	RERTL: Finite State Transducer Logic Recovery at Register Transfer Level.	AsianHOST	2019	DBLP DOI BibTeX RDF
11	Fang Li, Chao Yan, Ziyuan Zhu, Dan Meng	A Deep Malware Detection Method Based on General-Purpose Register Features.	ICCS (3)	2019	DBLP DOI BibTeX RDF
11	Soma Chaudhuri, Reginald Frank, Jennifer L. Welch	How Fast Reads Affect Multi-Valued Register Simulations.	PODC	2019	DBLP DOI BibTeX RDF
11	Antoine Mottet, Karin Quaas	The Containment Problem for Unambiguous Register Automata.	STACS	2019	DBLP DOI BibTeX RDF
11	Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001, Vivek De, Sanu Mathew	A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
11	Xinmiao Zhang, Yok Jye Tang	Reducing Parallel Linear Feedback Shift Register Complexity Through Input Tap Modification.	ISCAS	2019	DBLP DOI BibTeX RDF
11	Tao Han, Yuze Wang, Peng Liu 0016	Hardware Trojans Detection at Register Transfer Level Based on Machine Learning.	ISCAS	2019	DBLP DOI BibTeX RDF
11	Yuxuan Tang, Qingjun Fan, Yulang Feng, Hao Deng 0003, Runxi Zhang, Jinghong Chen	A Low-Power SiPM Readout Front-End with Fast Pulse Generation and Successive-Approximation Register ADC in 0.18 μm CMOS.	ISCAS	2019	DBLP DOI BibTeX RDF
11	Vassos Hadzilacos, Xing Hu 0009, Sam Toueg	Optimal Register Construction in M&M Systems.	OPODIS	2019	DBLP DOI BibTeX RDF
11	Thomas Goldbrunner, Nguyen Anh Vu Doan, Diogo Poças, Thomas Wild, Andreas Herkersdorf	Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications.	SoCC	2019	DBLP DOI BibTeX RDF
11	Zhi-Yin Lu, Jia-Feng Liu, Yunbing Pang, Zhengjie Li, Yufan Zhang, Jin-Mei Lai, Jian Wang 0036	A Low-delay Configurable Register for FPGA.	ASICON	2019	DBLP DOI BibTeX RDF
11	Li-Yi Xiao, Yuan-Gang Wang, Zu-Qiang Zhang, Jia-Qiang Li, Jie Li	Radiation Hardened Design of Pipeline and Register File in Processor.	ASICON	2019	DBLP DOI BibTeX RDF
11	Xiangnan Song, Shiying Zhang, Ju Zhou, Xuexiang Wang	A Variation Aware Register Clustering Methodology in Near-Threshold Region.	ASICON	2019	DBLP DOI BibTeX RDF
11	Michaela Brunner, Johanna Baehr, Georg Sigl	Improving on State Register Identification in Sequential Hardware Reverse Engineering.	HOST	2019	DBLP DOI BibTeX RDF
11	Werner Haselmayr, Daniel Wiesinger, Michael Lunglmayr	Counter-Based vs. Shift-Register-Based Signal Processing in Stochastic Computing.	EUROCAST (2)	2019	DBLP DOI BibTeX RDF
11	Ayrat Khalimov 0001, Orna Kupferman	Register-Bounded Synthesis.	CONCUR	2019	DBLP DOI BibTeX RDF
11	Ana Paula Chaves 0001, Eck Doerry, Jesse Egbert, Marco Aurélio Gerosa	It's How You Say It: Identifying Appropriate Register for Chatbot Language Design.	HAI	2019	DBLP DOI BibTeX RDF
11	Pengfei Yue, Ru Li 0004, Bin Pang	Register before Publishing with Smart Forwarding, Mitigate Content Poisoning Attack in ICN.	ISPA/BDCloud/SocialCom/SustainCom	2019	DBLP DOI BibTeX RDF
11	Manolis Chatzimpyrros, Konstantinos Solomos, Sotiris Ioannidis	You Shall Not Register! Detecting Privacy Leaks Across Registration Forms.	IOSec/MSTEC/FINSEC@ESORICS	2019	DBLP DOI BibTeX RDF
11	Miao Tony He, Jungmin Park, Adib Nahiyan, Apostol Vassilev 0001, Yier Jin, Mark M. Tehranipoor	RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level.	VTS	2019	DBLP DOI BibTeX RDF
11	Putt Sakdhnagool, Amit Sabne, Rudolf Eigenmann	Optimizing GPU programs by register demotion: poster.	PPoPP	2019	DBLP DOI BibTeX RDF
11	Yunho Oh, Gunjae Koo, Murali Annavaram, Won Woo Ro	Linebacker: preserving victim cache lines in idle register files of GPUs.	ISCA	2019	DBLP DOI BibTeX RDF
11	Priyanka Panigrahi, Rajesh Kumar Jha, Chandan Karfa	User Guided Register Manipulation in Digital Circuits.	VDAT	2019	DBLP DOI BibTeX RDF
11	M. Mahendra Reddy, Sounak Roy	Clock Pulse Based Foreground Calibration of a Sub-Radix-2 Successive Approximation Register ADC.	VDAT	2019	DBLP DOI BibTeX RDF
11	Hodjat Asghari Esfeden, Farzad Khorasani, Hyeran Jeon, Daniel Wong 0001, Nael B. Abu-Ghazaleh	CORF: Coalescing Operand Register File for GPUs.	ASPLOS	2019	DBLP DOI BibTeX RDF
11	Solène Tarride, Aurélie Lemaitre, Bertrand Coüasnon, Sophie Tardivel	Signature detection as a way to recognise historical parish register structure.	HIP@ICDAR	2019	DBLP DOI BibTeX RDF
11	Suhaib Ahmed, Vipan Kakkar	Modeling and simulation of an eight-bit auto-configurable successive approximation register analog-to-digital converter for cardiac and neural implants.	Simul.	2018	DBLP DOI BibTeX RDF
11	Jiafeng Xie, Pramod Kumar Meher, Xiaojun Zhou, Chiou-Yng Lee	Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2m) Based on Trinomials.	IEEE Trans. Multi Scale Comput. Syst.	2018	DBLP DOI BibTeX RDF
11	Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai	Bank-Aware Instruction Scheduler for a Multibanked Register File.	J. Inf. Process.	2018	DBLP DOI BibTeX RDF
11	M. Kiruba, V. Sumathy	Register Pre-Allocation based Folded Discrete Tchebichef Transformation Technique for Image Compression.	Integr.	2018	DBLP DOI BibTeX RDF
11	Shahrzad Kananizadeh, Kirill Kononenko	Improving on Linear Scan Register Allocation.	Int. J. Autom. Comput.	2018	DBLP DOI BibTeX RDF
11	Teng Yang, Doyun Kim, Jiangyi Li, Peter R. Kinget, Mingoo Seok	In~Situ and In-Field Technique for Monitoring and Decelerating NBTI in 6T-SRAM Register Files.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
11	Wenjun Wang, Wei-Ming Lin	Real-time physical register file allocation with neural networks for simultaneous multi-threading processors.	Int. J. High Perform. Syst. Archit.	2018	DBLP DOI BibTeX RDF
11	Lin Wang 0024, Ying Gao 0006, Yu Zhou, Xiaoni Du	On Searching Linear Transformations for the Register R of MICKEY-Family Ciphers.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2018	DBLP DOI BibTeX RDF
11	Jagadish Dasarahalli Narasimaiah, Laxminidhi Tonse, Mujoor Sankaranarayana Bhat	11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energy-efficient successive approximation register ADC in 90 nm complementary metal-oxide-semiconductor.	IET Circuits Devices Syst.	2018	DBLP DOI BibTeX RDF
11	Nehal N. Shah, Upena D. Dalal	Register array-based sum of absolute difference processor with parallel memory system for fast motion estimation.	IET Comput. Digit. Tech.	2018	DBLP DOI BibTeX RDF
11	Mitsuhiko Ota, Nicola Davies-Jenkins, Barbora Skarabela	Why Choo-Choo Is Better Than Train: The Role of Register-Specific Words in Early Vocabulary Growth.	Cogn. Sci.	2018	DBLP DOI BibTeX RDF
11	Ethan Douglas Quaid	Output Register Parallelism in an Identical Direct and Semi-Direct Speaking Test: A Case Study.	Int. J. Comput. Assist. Lang. Learn. Teach.	2018	DBLP DOI BibTeX RDF
11	Xiaolong Xie, Yun Liang 0001, Xiuhong Li, Yudong Wu, Guangyu Sun 0003, Tao Wang 0004, Dongrui Fan	CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs.	IEEE Trans. Computers	2018	DBLP DOI BibTeX RDF
11	Alexis Ramos, Anees Ullah, Pedro Reviriego, Juan Antonio Maestro	Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs.	IEEE Trans. Computers	2018	DBLP DOI BibTeX RDF
11	Parvaneh Babari, Manfred Droste, Vitaly Perevoshchikov	Weighted register automata and weighted logic on data words.	Theor. Comput. Sci.	2018	DBLP DOI BibTeX RDF
11	Benjamin Hackl, Clemens Heuberger, Helmut Prodinger	Reductions of binary trees and lattice paths induced by the register function.	Theor. Comput. Sci.	2018	DBLP DOI BibTeX RDF
11	Silvia Bonomi, Antonella Del Pozzo, Maria Potop-Butucaru	Optimal self-stabilizing synchronous mobile Byzantine-tolerant atomic register.	Theor. Comput. Sci.	2018	DBLP DOI BibTeX RDF
11	Dipankar Dey, Debasis Giri, Biswapati Jana, Tanmoy Maitra, Ram N. Mohapatra	Linear-feedback shift register-based multi-ant cellular automation and chaotic map-based image encryption.	Secur. Priv.	2018	DBLP DOI BibTeX RDF
11	Jonathan Bailey, John Kloosterman, Scott A. Mahlke	Scratch That (But Cache This): A Hybrid Register Cache/Scratchpad for GPUs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
11	Julia Wrobel	register: Registration for Exponential Family Functional Data.	J. Open Source Softw.	2018	DBLP DOI BibTeX RDF
11	Dani Voitsechov, Arslan Zulfiqar, Mark Stephenson, Mark Gebhart, Stephen W. Keckler	Software-Directed Techniques for Improved GPU Register File Utilization.	ACM Trans. Archit. Code Optim.	2018	DBLP DOI BibTeX RDF
11	Shao-Chung Wang, Li-Chen Kan, Chao-Lin Lee, Yuan-Shin Hwang, Jenq-Kuen Lee	Architecture and Compiler Support for GPUs Using Energy-Efficient Affine Register Files.	ACM Trans. Design Autom. Electr. Syst.	2018	DBLP DOI BibTeX RDF
11	Shaull Almagor, Michaël Cadilhac, Filip Mazowiecki, Guillermo A. Pérez 0001	Weak Cost Register Automata are Still Powerful.	CoRR	2018	DBLP BibTeX RDF
11	Julian Stecklina, Thomas Prescher 0002	LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels.	CoRR	2018	DBLP BibTeX RDF
11	Loris D'Antoni, Tiago Ferreira 0001, Matteo Sammartino, Alexandra Silva 0001	Symbolic Register Automata.	CoRR	2018	DBLP BibTeX RDF
11	Ayrat Khalimov 0001, Benedikt Maderbacher, Roderick Bloem	Bounded Synthesis of Register Transducers.	CoRR	2018	DBLP BibTeX RDF
11	Antoine Mottet, Karin Quaas	The Containment Problem for Unambiguous Register Automata.	CoRR	2018	DBLP BibTeX RDF
11	Karthik Airani, Rohit Guttal	A Machine Learning Framework for Register Placement Optimization in Digital Circuit Design.	CoRR	2018	DBLP BibTeX RDF
11	Roberto Castañeda Lozano, Mats Carlsson, Gabriel Hjort Blindell, Christian Schulte 0001	Combinatorial Register Allocation and Instruction Scheduling.	CoRR	2018	DBLP BibTeX RDF
11	Bao-Rong Chang, Hsiu Fen Tsai, Hsia-Chung Huang	Implementation of Smart Mobile Point-of-Sale Cash Register System.	J. Netw. Intell.	2018	DBLP BibTeX RDF
11	Myrto-Panagiota Zacharof, Anna Charalambidou	An Exploration of the Sub-Register of Chemical Engineering Research Papers Published in English.	Publ.	2018	DBLP DOI BibTeX RDF
11	Bjørn Kjos-Hanssen	Automatic complexity of shift register sequences.	Discret. Math.	2018	DBLP DOI BibTeX RDF
11	Yuanhui Ni, Weiwen Chen, Lei Wang, Keni Qiu	面向MLC STT-RAM的寄存器分配策略优化研究 (Optimization of Register Allocation Strategy for MLC STT-RAM).	计算机科学	2018	DBLP BibTeX RDF
11	Himchan Park, Qiwei Huang, Changzhi Yu, Seulki Kim, Gil-Cho Ahn, Jinwook Burm	Two CMOS time to digital converters using successive approximation register logic.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
11	Josef Eisl, David Leopoldseder, Hanspeter Mössenböck	Parallel trace register allocation.	ManLang	2018	DBLP DOI BibTeX RDF
11	Stéphane Clinchant, Hervé Déjean, Jean-Luc Meunier, Eva Maria Lang, Florian Kleber	Comparing Machine Learning Approaches for Table Recognition in Historical Register Books.	DAS	2018	DBLP DOI BibTeX RDF
11	Silvia Bonomi, Antonella Del Pozzo, Maria Potop-Butucaru, Sébastien Tixeuil	Brief Announcement: Optimal Self-stabilizing Mobile Byzantine-Tolerant Regular Register with Bounded Timestamps.	SSS	2018	DBLP DOI BibTeX RDF
11	Neeta Pandey, Kirti Gupta, Bharat Choudhary	MCML Dynamic Register Design.	MWSCAS	2018	DBLP DOI BibTeX RDF
11	Maryam Hemattil, Arash Ahmadi, Seyed Vahab Makkil, Majid Ahmadi	Hardware Design of Chaotic Pseudo-Random Number Generator Based on Nonlinear Feedback Shift Register.	MWSCAS	2018	DBLP DOI BibTeX RDF
11	Matej Bartík, Sven Ubik, Pavel Kubalík, Tomás Benes	Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
11	Davit Hayrapetyan, Aleksandr Manukvan, Grigor Tshagharyan	Implementation of Memory Static, Coupling and Dynamic Fault Models at the Register Transfer Level.	EWDTS	2018	DBLP DOI BibTeX RDF
11	Shail Dave, Mahesh Balasubramanian 0001, Aviral Shrivastava	URECA: Unified register file for CGRAs.	DATE	2018	DBLP DOI BibTeX RDF
11	Yunho Oh, Myung Kuk Yoon, William J. Song, Won Woo Ro	FineReg: Fine-Grained Register File Management for Augmenting GPU Throughput.	MICRO	2018	DBLP DOI BibTeX RDF
11	Farzad Khorasani, Hodjat Asghari Esfeden, Nael B. Abu-Ghazaleh, Vivek Sarkar	In-Register Parameter Caching for Dynamic Neural Nets with Virtual Persistent Processor Specialization.	MICRO	2018	DBLP DOI BibTeX RDF
11	Hidetsugu Irie, Toru Koizumi 0001, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai	STRAIGHT: Hazardless Processor Architecture Without Register Renaming.	MICRO	2018	DBLP DOI BibTeX RDF
11	Wei-Yu Chen, Guei-Yuan Lueh, Pratik Ashar, Kaiyu Chen, Buqi Cheng	Register allocation for Intel processor graphics.	CGO	2018	DBLP DOI BibTeX RDF
11	Hamid Tabani, José-María Arnau, Jordi Tubella, Antonio González 0001	A Novel Register Renaming Technique for Out-of-Order Processors.	HPCA	2018	DBLP DOI BibTeX RDF
11	Thomas Ferrère, Thomas A. Henzinger, N. Ege Saraç	A Theory of Register Monitors.	LICS	2018	DBLP DOI BibTeX RDF
11	Ayrat Khalimov 0001, Benedikt Maderbacher, Roderick Bloem	Bounded Synthesis of Register Transducers.	ATVA	2018	DBLP DOI BibTeX RDF
11	Joonas Multanen, Heikki Kultala, Pekka Jääskeläinen	Energy-Delay Trade-Offs in Instruction Register File Design.	NORCAS	2018	DBLP DOI BibTeX RDF
11	Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch 0001	ILP-Based Modulo Scheduling and Binding for Register Minimization.	FPL	2018	DBLP DOI BibTeX RDF
11	Vishwesh Jatala, Jayvant Anantpur, Amey Karkare	Reducing GPU Register File Energy.	Euro-Par	2018	DBLP DOI BibTeX RDF
11	Florian Kleber, Markus Diem, Hervé Déjean, Jean-Luc Meunier, Eva Maria Lang	Matching Table Structures of Historical Register Books using Association Graphs.	ICFHR	2018	DBLP DOI BibTeX RDF
11	Andrzej S. Murawski, Steven J. Ramsay, Nikos Tzevelekos	Polynomial-Time Equivalence Testing for Deterministic Fresh-Register Automata.	MFCS	2018	DBLP DOI BibTeX RDF
11	Inês Dias, Pedro Fonseca, Duarte Furtado, Inês Figueira, Paulo Franco, Vanda Cláudio, Helena Antunes, José Fragata, Cláudia Quaresma, Carla Quintão	Development of a Parameter Calculator in Cardiovascular Perfusion - BioMEP as a Tool for the Register of Physiological Parameters.	BIODEVICES	2018	DBLP DOI BibTeX RDF
11	Dirk Habich, Patrick Damme, Annett Ungethüm, Wolfgang Lehner	Make Larger Vector Register Sizes New Challenges?: Lessons Learned from the Area of Vectorized Lightweight Compression Algorithms.	DBTest@SIGMOD	2018	DBLP DOI BibTeX RDF
11	Jhohn Paulo E. de Chavez, Michaella M. Maala, Ellen Mhae M. Valencia, Adonis S. Santos, Francis A. Malabanan, Jay Nickson T. Tabing, Sherryl M. Gevana	Development of Resolution Scalable Successive Approximation Register ADC in 90nm CMOS Process Technology for Wireless Sensor Network.	TENCON	2018	DBLP DOI BibTeX RDF
11	Shaull Almagor, Michaël Cadilhac, Filip Mazowiecki, Guillermo A. Pérez 0001	Weak Cost Register Automata Are Still Powerful.	DLT	2018	DBLP DOI BibTeX RDF
11	Stefan Bramburger, Pavol Pitonak, Dirk Killat	A unary coded current steering DAC with sequential stepping of the thermometer coded register in 1 and 2 LSB steps.	MIPRO	2018	DBLP DOI BibTeX RDF
11	Hua Fan 0001, Chen Wang, Hailiang Xiong, Quanyuan Feng, Dagang Li, Kelin Zhang, Xiaopeng Diao, Lishuang Lin, Hadi Heidari	A Bit Cycling Method for Improving the DNL/INL in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).	NGCAS	2018	DBLP DOI BibTeX RDF
11	Hasancan Güngörer, Gürhan Küçük	Dynamic Capping of Physical Register Files in Simultaneous Multi-threading Processors for Performance.	ISCIS	2018	DBLP DOI BibTeX RDF
11	Nicola Ferro 0001, Luca Sinico	Graph Databases Benchmarking on the Italian Business Register.	SEBD	2018	DBLP BibTeX RDF
11	Jade Mekki, Delphine Battistelli, Gwénolé Lecorvé, Nicolas Béchet	Identification de descripteurs pour la caractérisation de registres (Feature identification for register characterization).	CORIA-TALN-RJC (DeFT)	2018	DBLP BibTeX RDF
11	Junichiro Kadomoto, Toru Koizumi 0001, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai	An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming.	FPT	2018	DBLP DOI BibTeX RDF
11	Georgy Lebedev, Marina Shakhova, Alexey Kholin, Oleg Malyarenko, Vladimir Bondarenko, Sergey V. Zykov	Application of a prospective assisted reproductive technologies register for calculating the probability of pregnancy.	KES	2018	DBLP DOI BibTeX RDF
11	Hoan Nguyen, Jihoon Jeong, Francois Atallah, Marc Jansen, Anthony Polomik, Daniel Yingling, Harsha Akkaraju, Brad Appel, Rahul Nadkarni, Keith A. Bowman	A 7NM Double-Pumped 6R6W Register File for Machine Learning Memory.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
11	Sying-Jyan Wang, Chin-Hung Lien, Katherine Shu-Min Li	Register PUF with No Power-Up Restrictions.	ISCAS	2018	DBLP DOI BibTeX RDF
11	Gaurav Sharma 0008, Lava Bhargava, Vinod Kumar 0016	Automated Coverage Register Access Technology on UVM Framework for Advanced Verification.	ISCAS	2018	DBLP DOI BibTeX RDF