Search results for "ARCS"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Anis Koubaa	A Service-Oriented Architecture for Virtualizing Robots in Robot-as-a-Service Clouds.	ARCS	2014	DBLP DOI BibTeX RDF
1	Ghazaleh Nazarian, Luigi Carro, Georgi Gaydadjiev	Towards Code Safety with High Performance.	ARCS	2014	DBLP DOI BibTeX RDF
1	Nizar Msadek, Rolf Kiefhaber, Bernhard Fechner, Theo Ungerer	Trust-Enhanced Self-configuration for Organic Computing Systems.	ARCS	2014	DBLP DOI BibTeX RDF
1	Antonio Barros, Luís Miguel Pinho	Non-preemptive Scheduling of Real-Time Software Transactional Memory.	ARCS	2014	DBLP DOI BibTeX RDF
1	Fabio Erculiani, Luca Abeni, Luigi Palopoli 0002	uBuild: Automated Testing and Performance Evaluation of Embedded Linux Systems.	ARCS	2014	DBLP DOI BibTeX RDF
1	Shuichi Oikawa	Independent Kernel/Process Checkpointing on Non-Volatile Main Memory for Quick Kernel Rejuvenation.	ARCS	2014	DBLP DOI BibTeX RDF
1	Xiaojun Zhai, Kofi Appiah, Shoaib Ehsan, Wah M. Cheung, Gareth Howells 0001, Huosheng Hu, Dongbing Gu, Klaus D. McDonald-Maier	Detecting Compromised Programs for Embedded System Applications.	ARCS	2014	DBLP DOI BibTeX RDF
1	Erik Maehle, Kay Römer, Wolfgang Karl, Eduardo Tovar (eds.)	Architecture of Computing Systems - ARCS 2014 - 27th International Conference, Lübeck, Germany, February 25-28, 2014. Proceedings	ARCS	2014	DBLP DOI BibTeX RDF
1	Hajer Herbegue, Mamoun Filali, Hugues Cassé	Formal Architecture Specification for Time Analysis.	ARCS	2014	DBLP DOI BibTeX RDF
1	Edward S. Canepa, Enas Odat, Ahmad H. Dehwah, Mustafa Mousa, Jiming Jiang, Christian G. Claudel	A Sensor Network Architecture for Urban Traffic State Estimation with Mixed Eulerian/Lagrangian Sensing Based on Distributed Computing.	ARCS	2014	DBLP DOI BibTeX RDF
1	Sihem Loukil, Slim Kallel, Mohamed Jmaiel	Middleware for Dynamically Adaptive Systems.	ARCS	2014	DBLP DOI BibTeX RDF
1	Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat	Resource-Aware Harris Corner Detection Based on Adaptive Pruning.	ARCS	2014	DBLP DOI BibTeX RDF
1	Sayyed Ali Mirsoleimani, Ali Karami, Farshad Khunjush	A Two-Tier Design Space Exploration Algorithm to Construct a GPU Performance Predictor.	ARCS	2014	DBLP DOI BibTeX RDF
1	Rafael Rosales, Michael Glaß, Jürgen Teich	Mahler: Sketch-Based Model-Driven Virtual Prototyping.	ARCS	2014	DBLP DOI BibTeX RDF
1	Krishna M. Kavi, Stefano Pianelli, Giandomenico Pisano, Giuseppe Regina, Mike Ignatowski	3D DRAM and PCMs in Processor Memory Hierarchy.	ARCS	2014	DBLP DOI BibTeX RDF
1	Rico Backasch, Christian Hochberger	Custom Reconfigurable Architecture Based on Virtex 5 Lookup Tables.	ARCS	2013	DBLP DOI BibTeX RDF
1	Boris Motruk, Jonas Diemer, Rainer Buchty, Mladen Berekovic	Power Monitoring for Mixed-Criticality on a Many-Core Platform.	ARCS	2013	DBLP DOI BibTeX RDF
1	Christian Herber, Andre Oliver Richter, Holm Rauchfuss, Andreas Herkersdorf	Self-virtualized CAN Controller for Multi-core Processors in Real-Time Applications.	ARCS	2013	DBLP DOI BibTeX RDF
1	Tobias Ziermann, Zoran Salcic, Jürgen Teich	HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN).	ARCS	2013	DBLP DOI BibTeX RDF
1	Alexandra Ferrerón-Labari, Marta Ortín-Obón, Darío Suárez Gracia, Jesús Alastruey-Benedé, Víctor Viñals Yúfera	Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors.	ARCS	2013	DBLP DOI BibTeX RDF
1	JongBeom Lim, Kwang-Sik Chung, Joon-Min Gil, Taeweon Suh, Heon-Chang Yu	An Unstructured Termination Detection Algorithm Using Gossip in Cloud Computing Environments.	ARCS	2013	DBLP DOI BibTeX RDF
1	Catalin Bogdan Ciobanu, Georgi Nedeltchev Gaydadjiev	Separable 2D Convolution with Polymorphic Register Files.	ARCS	2013	DBLP DOI BibTeX RDF
1	Marcin Pietron, Maciej Wielgosz, Dominik Zurek, Ernest Jamro, Kazimierz Wiatr	Comparison of GPU and FPGA Implementation of SVM Algorithm for Fast Image Segmentation.	ARCS	2013	DBLP DOI BibTeX RDF
1	Shiao-Li Tsao, Cheng-Kun Yu, Yi-Hsin Chang	Profiling Energy Consumption of I/O Functions in Embedded Applications.	ARCS	2013	DBLP DOI BibTeX RDF
1	Fabian Nowak, Ingo Besenfelder, Wolfgang Karl, Mareike Schmidtobreick, Vincent Heuveline	A Data-Driven Approach for Executing the CG Method on Reconfigurable High-Performance Systems.	ARCS	2013	DBLP DOI BibTeX RDF
1	Benjamin Betting, Julius von Rosen, Lars Hedrich, Uwe Brinkschulte	A Highly Dependable Self-adaptive Mixed-Signal Multi-core System-on-Chip.	ARCS	2013	DBLP DOI BibTeX RDF
1	Epifanio Gaona-Ramírez, José L. Abellán, Manuel E. Acacio, Juan Fernández 0001	Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory.	ARCS	2013	DBLP DOI BibTeX RDF
1	Stefan Wallentowitz, Thomas Wild, Andreas Herkersdorf	HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation.	ARCS	2013	DBLP DOI BibTeX RDF
1	Tomás Zahradnický, Róbert Lórencz	Architecture of a Parallel MOSFET Parameter Extraction System.	ARCS	2013	DBLP DOI BibTeX RDF
1	Muhammad Nadeem, HeeJong Park 0001, Zhenmin Li, Morteza Biglari-Abhari, Zoran Salcic	GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems.	ARCS	2013	DBLP DOI BibTeX RDF
1	Jan Hartmann, Walter Stechele, Erik Maehle	Self-adaptation for Mobile Robot Algorithms Using Organic Computing Principles.	ARCS	2013	DBLP DOI BibTeX RDF
1	Yang Xu 0019, Bo Wang 0010, Rafael Rosales, Ralph Hasholzner, Jürgen Teich	On Confident Task-Accurate Performance Estimation.	ARCS	2013	DBLP DOI BibTeX RDF
1	Hana Kubátová, Christian Hochberger, Martin Danek, Bernhard Sick (eds.)	Architecture of Computing Systems - ARCS 2013 - 26th International Conference, Prague, Czech Republic, February 19-22, 2013. Proceedings	ARCS	2013	DBLP DOI BibTeX RDF
1	Josef Hlavác, Róbert Lórencz	Arithmetic Unit for Computations in GF(p) with the Left-Shifting Multiplicative Inverse Algorithm.	ARCS	2013	DBLP DOI BibTeX RDF
1	Ahmad Lashgar, Amirali Baniasadi, Ahmad Khonsari	Inter-warp Instruction Temporal Locality in Deep-Multithreaded GPUs.	ARCS	2013	DBLP DOI BibTeX RDF
1	Tripti S. Warrier, B. Anupama, Madhu Mutyam	An Application-Aware Cache Replacement Policy for Last-Level Caches.	ARCS	2013	DBLP DOI BibTeX RDF
1	Maciej Zbierski	Iwazaru: The Byzantine Sequencer.	ARCS	2013	DBLP DOI BibTeX RDF
1	Jared Sherman, Krishna M. Kavi, Brandon Potter, Mike Ignatowski	A Multi-core Memory Organization for 3-D DRAM as Main Memory.	ARCS	2013	DBLP DOI BibTeX RDF
1	Arnau Prat-Pérez, David Dominguez-Sal, Josep Lluís Larriba-Pey, Pedro Trancoso	Producer-Consumer: The Programming Model for Future Many-Core Processors.	ARCS	2013	DBLP DOI BibTeX RDF
1	Mageda Sharafeddine, Haitham Akkary, Doug Carmean	Virtual Register Renaming.	ARCS	2013	DBLP DOI BibTeX RDF
1	Roman Bourgade, Christine Rochange, Pascal Sainrat	Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets.	ARCS	2013	DBLP DOI BibTeX RDF
1	Christian Beckhoff, Dirk Koch, Jim Tørresen	Automatic Floorplanning and Interface Synthesis of Island Style Reconfigurable Systems with GoAhead.	ARCS	2013	DBLP DOI BibTeX RDF
1	Simone Corbetta, William Fornaciari	Exploiting Thermal Coupling Information in MPSoC Dynamic Thermal Management.	ARCS	2013	DBLP DOI BibTeX RDF
1	Pascal Schleuniger, Anders Kusk, Jørgen Dall, Sven Karlsson	Synthetic Aperture Radar Data Processing on an FPGA Multi-core System.	ARCS	2013	DBLP DOI BibTeX RDF
1	Josef Strnadel	Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates.	ARCS	2013	DBLP DOI BibTeX RDF
1	Richard Membarth, Jan-Hugo Lupp, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert	Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging.	ARCS	2012	DBLP DOI BibTeX RDF
1	Nikita Nikitin, Jordi Cortadella	Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands.	ARCS	2012	DBLP DOI BibTeX RDF
1	Isaías A. Comprés Ureña, Michael Riepen, Michael Konow, Michael Gerndt	Invasive MPI on Intel's Single-Chip Cloud Computer.	ARCS	2012	DBLP DOI BibTeX RDF
1	Davide Zoni, Patrick Bellasi, William Fornaciari	A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures.	ARCS	2012	DBLP DOI BibTeX RDF
1	Christian Brehm, Matthias May, Christina Gimmler, Norbert Wehn	A Case Study on Error Resilient Architectures for Wireless Communication.	ARCS	2012	DBLP DOI BibTeX RDF
1	Frédéric Boniol, Hugues Cassé, Eric Noulard, Claire Pagetti	Deterministic Execution Model on COTS Hardware.	ARCS	2012	DBLP DOI BibTeX RDF
1	Panayiotis Petrides, George Nicolaides, Pedro Trancoso	HPC Performance Domains on Multi-core Processors with Virtualization.	ARCS	2012	DBLP DOI BibTeX RDF
1	Atis Elsts, Rihards Balass, Janis Judvaitis, Reinholds Zviedris, Girts Strazdins, Artis Mednis, Leo Selavo	SADmote: A Robust and Cost-Effective Device for Environmental Monitoring.	ARCS	2012	DBLP DOI BibTeX RDF
1	Volker Hampel, Thilo Pionteck, Erik Maehle	An Approach for Performance Estimation of Hybrid Systems with FPGAs and GPUs as Coprocessors.	ARCS	2012	DBLP DOI BibTeX RDF
1	Andreas Barthels, Joachim Fröschl, Hans-Ulrich Michel, Uwe Baumgarten	An Architecture for Power Management in Automotive Systems.	ARCS	2012	DBLP DOI BibTeX RDF
1	Andreas Heinig, Vincent John Mooney, Florian Schmoll, Peter Marwedel, Krishna V. Palem, Michael Engel	Classification-Based Improvement of Application Robustness and Quality of Service in Probabilistic Computer Systems.	ARCS	2012	DBLP DOI BibTeX RDF
1	Matthew Bielby, Miles Gould, Nigel P. Topham	Design Space Exploration of Hybrid Ultra Low Power Branch Predictors.	ARCS	2012	DBLP DOI BibTeX RDF
1	Yang Xu 0019, Rafael Rosales, Bo Wang 0010, Martin Streubühr, Ralph Hasholzner, Christian Haubelt, Jürgen Teich	A Very Fast and Quasi-accurate Power-State-Based System-Level Power Modeling Methodology.	ARCS	2012	DBLP DOI BibTeX RDF
1	Hao Zhang 0020, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano	Vertical Link On/Off Control Methods for Wireless 3-D NoCs.	ARCS	2012	DBLP DOI BibTeX RDF
1	Ademola Fawibe, Jared Sherman, Krishna M. Kavi, Mike Ignatowski, David Mayhew	New Memory Organizations for 3D DRAM and PCMs.	ARCS	2012	DBLP DOI BibTeX RDF
1	Oussama Tahan, Mohamed Shawky	Using Dynamic Task Level Redundancy for OpenMP Fault Tolerance.	ARCS	2012	DBLP DOI BibTeX RDF
1	Andreas Herkersdorf, Kay Römer, Uwe Brinkschulte (eds.)	Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28 - March 2, 2012. Proceedings	ARCS	2012	DBLP DOI BibTeX RDF
1	Jens Brandenburg, Benno Stabernack	A Generic and Non-intrusive Profiling Methodology for SystemC Multi-core Platform Simulation Models.	ARCS	2012	DBLP DOI BibTeX RDF
1	Sebastian Mattheis, Tobias Schuele, Andreas Raabe, Thomas Henties, Urs Gleim	Work Stealing Strategies for Parallel Stream Processing in Soft Real-Time Systems.	ARCS	2012	DBLP DOI BibTeX RDF
1	Gadi Oxman, Shlomo Weiss, Yitzhak (Tsahi) Birk	Streamlined Network-on-Chip for Multicore Embedded Architectures.	ARCS	2012	DBLP DOI BibTeX RDF
1	Pascal Schleuniger, Sally A. McKee, Sven Karlsson	Design Principles for Synthesizable Processor Cores.	ARCS	2012	DBLP DOI BibTeX RDF
1	Mladen Berekovic, William Fornaciari, Uwe Brinkschulte, Cristina Silvano (eds.)	Architecture of Computing Systems - ARCS 2011 - 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings	ARCS	2011	DBLP DOI BibTeX RDF
1	David Kramer, Rainer Buchty, Wolfgang Karl	A Light-Weight Approach for Online State Classification of Self-organizing Parallel Systems.	ARCS	2011	DBLP DOI BibTeX RDF
1	Pedro Trancoso, Norbert Martínez-Bazan, Josep Lluís Larriba-Pey	Memory-, Bandwidth-, and Power-Aware Multi-core for a Graph Database Workload.	ARCS	2011	DBLP DOI BibTeX RDF
1	Martin Schindewolf, Alexander Esselson, Wolfgang Karl	Compiler-Assisted Selection of a Software Transactional Memory System.	ARCS	2011	DBLP DOI BibTeX RDF
1	Jaroslav Sykora, Leos Kafka, Martin Danek, Lukas Kohout	Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3.	ARCS	2011	DBLP DOI BibTeX RDF
1	Hao Shen, Frédéric Pétrot	Using Amdahl's Law for Performance Analysis of Many-Core SoC Architectures Based on Functionally Asymmetric Processors.	ARCS	2011	DBLP DOI BibTeX RDF
1	Matteo Pusceddu, Simone Ceccolini, Antonino Tumeo, Gianluca Palermo, Donatella Sciuto	Emulating Transactional Memory on FPGA Multiprocessors.	ARCS	2011	DBLP DOI BibTeX RDF
1	Catalin Bogdan Ciobanu, Xavier Martorell, Georgi Kuzmanov, Alex Ramírez, Georgi Gaydadjiev	Scalability Evaluation of a Polymorphic Register File: A CG Case Study.	ARCS	2011	DBLP DOI BibTeX RDF
1	Oscar Almer, Nigel P. Topham, Björn Franke	A Learning-Based Approach to the Automated Design of MPSoC Networks.	ARCS	2011	DBLP DOI BibTeX RDF
1	Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert	Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration.	ARCS	2011	DBLP DOI BibTeX RDF
1	Michael Wittke, Carsten Grenz, Jörg Hähner	Towards Organic Active Vision Systems for Visual Surveillance.	ARCS	2011	DBLP DOI BibTeX RDF
1	Stefan Metzlaff, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer	A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware.	ARCS	2011	DBLP DOI BibTeX RDF
1	Kamil Kloch, Gerald Pirkl, Paul Lukowicz, Carl Fischer	Emergent Behaviour in Collaborative Indoor Localisation: An Example of Self-organisation in Ubiquitous Sensing Systems.	ARCS	2011	DBLP DOI BibTeX RDF
1	Angham A. Abdulahad Sabagh, Adil Al-Yasiri	An Extensible Framework for Context-Aware Smart Environments.	ARCS	2011	DBLP DOI BibTeX RDF
1	Nasibeh Teimouri, Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad	Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths.	ARCS	2011	DBLP DOI BibTeX RDF
1	Jörg Sachße, Heinz-Dietrich Wuttke, Steffen Ostendorff, Jorge H. Meza Escobar	Architecture of an Adaptive Test System Built on FPGAs.	ARCS	2011	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Ben H. H. Juurlink	An Instruction to Accelerate Software Caches.	ARCS	2011	DBLP DOI BibTeX RDF
1	Andreas Kern, Dominik Reinhard, Thilo Streichert, Jürgen Teich	Gateway Strategies for Embedding of Automotive CAN-Frames into Ethernet-Packets and Vice Versa.	ARCS	2011	DBLP DOI BibTeX RDF
1	Son Truong Nguyen, Shigeru Oyanagi	An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel Allocation.	ARCS	2011	DBLP DOI BibTeX RDF
1	Yuto Hayamizu, Kazuo Goda, Miyuki Nakano, Masaru Kitsuregawa	Application-Aware Power Saving for Online Transaction Processing Using Dynamic Voltage and Frequency Scaling in a Multicore Environment.	ARCS	2011	DBLP DOI BibTeX RDF
1	Antonino Tumeo, Simone Secchi, Oreste Villa	Experiences with String Matching on the Fermi Architecture.	ARCS	2011	DBLP DOI BibTeX RDF
1	Volker Hampel, Grigori Goronzy, Erik Maehle	A Code-Based Analytical Approach for Using Separate Device Coprocessors in Computing Systems.	ARCS	2011	DBLP DOI BibTeX RDF
1	Marius Grannæs, Magnus Jahre, Lasse Natvig	Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy.	ARCS	2011	DBLP DOI BibTeX RDF
1	Johannes Zeppenfeld, Andreas Herkersdorf	Autonomic Workload Management for Multi-core Processor Systems.	ARCS	2010	DBLP DOI BibTeX RDF
1	Görkem Asilioglu, Emine Merve Kaya, Oguz Ergin	Complexity-Effective Rename Table Design for Rapid Speculation Recovery.	ARCS	2010	DBLP DOI BibTeX RDF
1	Muhammad Yasir Qadri, Dorian Matichard, Klaus D. McDonald-Maier	JetBench: An Open Source Real-time Multiprocessor Benchmark.	ARCS	2010	DBLP DOI BibTeX RDF
1	Roman Plyaskin, Andreas Herkersdorf	A Method for Accurate High-Level Performance Evaluation of MPSoC Architectures Using Fine-Grained Generated Traces.	ARCS	2010	DBLP DOI BibTeX RDF
1	Martin Schindewolf, David Kramer, Marcelo Cintra	Compiler-Directed Performance Model Construction for Parallel Programs.	ARCS	2010	DBLP DOI BibTeX RDF
1	Yi Liu 0013, Yangming Su, Cui Zhang, Mingyu Wu 0004, Xin Zhang, He Li, Depei Qian	Efficient Transaction Nesting in Hardware Transactional Memory.	ARCS	2010	DBLP DOI BibTeX RDF
1	Matthias Bonn, Hartmut Schmeck	The JoSchKa System: Organic Job Distribution in Heterogeneous and Unreliable Environments.	ARCS	2010	DBLP DOI BibTeX RDF
1	Karsten Schwan, Ada Gavrilovska, Sudhakar Yalamanchili	HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors.	ARCS	2010	DBLP DOI BibTeX RDF
1	Fabian Nowak, Rainer Buchty	A Tightly Coupled Accelerator Infrastructure for Exact Arithmetics.	ARCS	2010	DBLP DOI BibTeX RDF
1	Kamil Kloch, Jan W. Kantelhardt, Paul Lukowicz, Patrick Wüchner, Hermann de Meer	Ad-Hoc Information Spread between Mobile Devices: A Case Study in Analytical Modeling of Controlled Self-organization in IT Systems.	ARCS	2010	DBLP DOI BibTeX RDF
1	Jan-Philipp Steghöfer, Pratik Mandrekar, Florian Nafz, Hella Seebach, Wolfgang Reif	On Deadlocks and Fairness in Self-organizing Resource-Flow Systems.	ARCS	2010	DBLP DOI BibTeX RDF

Publications at "ARCS"( http://dblp.L3S.de/Venues/ARCS )