Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Yuko Nakase, Sadahiro Kimura |
Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 5, pp. 118-132, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Paolo Meloni, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, Menno Lindwer |
Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2012, pp. 580584:1-580584:16, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre |
Loop Acceleration Exploration for ASIP Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 20(4), pp. 684-696, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Hsuanchun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda |
A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12), pp. 2373-2383, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Mahmoud A. Said, Omar A. Nasr, Ahmed F. Shalash |
Embedded reconfigurable synchronization & acquisition ASIP for a multi-standard OFDM receiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Embed. Syst. ![In: EURASIP J. Embed. Syst. 2012, pp. 2, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Hanan M. Hassan, Karim Mohamed, Ahmed F. Shalash |
Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Embed. Syst. ![In: EURASIP J. Embed. Syst. 2012, pp. 3, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Paolo Meloni, Sebastiano Pomata, Luigi Raffo, Roberta Piscitelli, Andy D. Pimentel |
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: 2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XII, Samos, Greece, July 16-19, 2012, pp. 310-317, 2012, IEEE, 978-1-4673-2295-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Yifan Bo, Jun Han 0003, Yao Zou, Xiaoyang Zeng |
A low power ASIP for precision configurable FFT processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APSIPA ![In: Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA 2012, Hollywood, CA, USA, December 3-6, 2012, pp. 1-4, 2012, IEEE, 978-1-4673-4863-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
20 | Quan Jinguo, Jinbin Ju, Qian Chen, Yan Zhang |
Fine-grained analysis and design of ASIP instruction set for application of encryption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNC ![In: International Conference on Computing, Networking and Communications, ICNC 2012, Maui, HI, USA, January 30 - February 2, 2012, pp. 144-148, 2012, IEEE Computer Society, 978-1-4673-0008-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Sebastiano Pomata, Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Menno Lindwer |
Exploiting binary translation for fast ASIP design space exploration on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, pp. 566-569, 2012, IEEE, 978-1-4577-2145-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Bertrand Le Gal, Christophe Jégo |
Design of an ASIP LDPC Decoder Compliant with Digital Communication Standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: 2012 IEEE Workshop on Signal Processing Systems, Quebec City, QC, Canada, October 17-19, 2012, pp. 19-24, 2012, IEEE, 978-1-4673-2986-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Zhongbo Wang, Zhiping Jia, Lei Ju 0001, Renhai Chen |
ASIP-based Design and Implementation of RSA for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC-ICESS ![In: 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, HPCC-ICESS 2012, Liverpool, United Kingdom, June 25-27, 2012, pp. 1375-1382, 2012, IEEE Computer Society, 978-1-4673-2164-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Jochen Rust, Steffen Paul |
Design and implementation of a neurocomputing ASIP for environmental monitoring in WSN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, pp. 129-132, 2012, IEEE, 978-1-4673-1261-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Hsuanchun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda |
A Reconfigurable High Performance ASIP Engine for Image Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, IPDPS 2012, Shanghai, China, May 21-25, 2012, pp. 368-375, 2012, IEEE Computer Society, 978-1-4673-0974-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Xiaolin Chen, Andreas Minwegen, Yahia Hassan, David Kammler, Shuai Li, Torsten Kempf, Anupam Chattopadhyay, Gerd Ascheid |
FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012, 29 April - 1 May 2012, Toronto, Ontario, Canada, pp. 69-76, 2012, IEEE Computer Society, 978-0-7695-4699-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Joon Ho Hyun, Myung Jin Park, Young Hwan Kim, Hi-Seok Kim |
ASIP-based control system for LED matrix display. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 3061-3064, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Bertrand Le Gal, Christophe Jégo |
FPGA prototyping of an ASIP LDPC decoder for the DVB-T2 standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASIP ![In: Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, DASIP 2012, Karlsruhe, Germany, October 23-25, 2012, pp. 1-2, 2012, IEEE, 978-1-4673-2089-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
20 | Mochamad Asri, Hsuanchun Liao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda |
A reconfigurable ASIP-based approach for high performance image signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, December 2-5, 2012, pp. 611-614, 2012, IEEE, 978-1-4577-1728-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Antoine Trouvé, Kazuaki J. Murakami |
Augmenting DR-ASIP flexibility through multi-mode custom instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 39(4), pp. 90-93, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Zdenek Prikryl, Jakub Kroustek, Tomas Hruska, Dusan Kolár |
Fast just-in-time translated simulator for ASIP design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, pp. 279-282, 2011, IEEE Computer Society, 978-1-4244-9755-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Gregor Schewior, Holger Flatt, Carsten Dolar, Christian Banz, Holger Blume |
A hardware accelerated configurable ASIP architecture for embedded real-time video-based driver assistance applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: 2011 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XI, Samos, Greece, July 18-21, 2011, pp. 209-216, 2011, IEEE, 978-1-4577-0802-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Esther P. Adeva, Björn Mennenga, Gerhard P. Fettweis |
Scalable ASIP implementation and parallelization of a MIMO sphere detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: 2011 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XI, Samos, Greece, July 18-21, 2011, pp. 233-241, 2011, IEEE, 978-1-4577-0802-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Jochen Rust, Christof Osewold, Steffen Paul |
Implementation of a Low Power Low Complexity ASIP for various Sphere Decoding Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EW ![In: European Wireless 2011, April 27-29, 2011, Vienna, Austria., 2011, VDE-Verlag, 978-3-8007-3343-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
20 | Purushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel |
A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pp. 228-233, 2011, IEEE, 978-1-61284-208-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Reza Faghih Mirzaee, Mohammad Eshghi |
Design of an ASIP IDEA crypto processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NESEA ![In: Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, NESEA 2011, Perth, Australia, December 8-9, 2011, pp. 1-7, 2011, IEEE Computer Society, 978-1-4673-0495-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Jinbin Ju, Quan Jinguo, Qian Chen, Yan Zhang |
Fine-grained analysis and design of ASIP instruction set for application of encryption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RACS ![In: Research in Applied Computation Symposium, RACS '11, Miami, FL, USA, October 19-22, 2011, pp. 44-49, 2011, ACM, 978-1-4503-1087-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Ji Qiu, Xiang Gao, Yifei Jiang, Xu Xiao |
An ultra-fast hybrid simulation framework for ASIP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, pp. 711-714, 2011, IEEE, 978-1-4577-1845-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Mariusz Grad, Christian Plessl |
Just-in-Time Instruction Set Extension - Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 25th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2011, Anchorage, Alaska, USA, 16-20 May 2011 - Workshop Proceedings, pp. 278-285, 2011, IEEE, 978-1-61284-425-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Anup Sarma, Soubhagya Sutar, Vijay Kumar Sharma, Kamala Kanta Mahapatra |
An ASIP for image enhancement applications in spatial domain using LISA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReTIS ![In: International Conference on Recent Trends in Information Systems, ReTIS 2011, December 21-23, 2011, Jadavpur University, Kolkata, India, Proceedings, pp. 175-179, 2011, IEEE, 978-1-4577-0792-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Rachid Al-Khayat, Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel |
Area and throughput optimized ASIP for multi-standard turbo decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Symposium on Rapid System Prototyping ![In: Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, RSP 2011, Karlsruhe, Germany, 24-27 May, 2011, pp. 79-84, 2011, IEEE, 978-1-4577-0658-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Hong Chinh Doan, Haris Javaid, Sri Parameswaran |
Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, Taipei, Taiwan, October 13-14, 2011, pp. 56-65, 2011, IEEE Computer Society, 978-1-4577-2123-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Simon Rajotte, Diana Carolina Gil, J. M. Pierre Langlois |
Combining ISA extensions and subsetting for improved ASIP performance and cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 653-656, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Hanan M. Hassan, Ahmed F. Shalash, Karim Mohamed |
FPGA Implementation of an ASIP for high throughput DFT/DCT 1D/2D engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 1255-1258, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Hee Kwan Eun, Sung Jo Hwang, Myung Hoon Sunwoo, Young Hwan Kim, Hi-Seok Kim |
Integer-pel Motion Estimation specific instructions and their hardware architecture for ASIP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 953-956, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Christian Brehm, Thomas Ilnseher, Norbert Wehn |
A scalable multi-ASIP architecture for standard compliant trellis decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2011, Jeju, South Korea, November 17-18, 2011, pp. 349-352, 2011, IEEE, 978-1-4577-0709-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Takaya Kaji, Shingo Yoshizawa, Yoshikazu Miyanaga |
Development of an ASIP-based singular value decomposition processor in SVD-MIMO systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPACS ![In: International Symposium on Intelligent Signal Processing and Communications Systems, ISPACS 2011, Chiang Mai, Thailand, December 7-9, 2011, pp. 1-5, 2011, IEEE, 978-1-4577-2165-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura |
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 3, pp. 161-178, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 3, pp. 222-233, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Fethi Tlili, Akram Ghorbel |
ASIP Solution for Implementation of H.264 Multi Resolution Motion Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Commun. Netw. Syst. Sci. ![In: Int. J. Commun. Netw. Syst. Sci. 3(5), pp. 453-461, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Götz Kappen, Lothor Kurz, O. Priebe, Tobias G. Noll |
Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 58(1), pp. 41-51, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Matthias Alles, Timo Vogt, Christian Brehm, Norbert Wehn |
FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Systems ![In: Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications., pp. 293-314, 2010, Springer, 978-9-04-813484-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Ioanna Tsekoura, Georgios N. Selimis, Jos Hulzink, Francky Catthoor, Jos Huisken, Harmke de Groot, Constantinos E. Goutis |
Exploration of cryptographic ASIP designs for wireless sensor nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010, pp. 827-830, 2010, IEEE, 978-1-4244-8155-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Emrah Tasdemir, Götz Kappen, Tobias G. Noll |
Potential of using block floating point arithmetic in ASIP-based GNSS-receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010, pp. 293-296, 2010, IEEE Computer Society, 978-1-4244-6967-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel |
ASIP-Based Universal Demapper for Multiwireless Standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 1(1), pp. 9-13, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Olivier Muller, Amer Baghdadi, Michel Jézéquel |
From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 17(1), pp. 92-102, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rainer Leupers, Rudolf Mathar, Heinrich Meyr |
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2009, pp. 56, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
20 | Atif Raza Jafri, Daoud Karakolah, Amer Baghdadi, Michel Jézéquel |
ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, pp. 1620-1625, 2009, IEEE, 978-1-4244-3781-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Christian Bachmann, Andreas Genser, Jos Hulzink, Mladen Berekovic, Christian Steger |
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, pp. 1614-1619, 2009, IEEE, 978-1-4244-3781-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Praveen Raghavan, Francky Catthoor |
Register file exploration for a multi-standard wireless forward error correction ASIP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2009, October 7-9, 2009, Tampere, Finland, pp. 024-029, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid |
Task management in MPSoCs: An ASIP approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009, pp. 587-594, 2009, ACM, 978-1-60558-800-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel |
Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, Shortening the Path from Specification to Prototype, RSP 2009, Paris, France, 23-26 June 2009, pp. 130-133, 2009, IEEE Computer Society, 978-0-7695-3690-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Steffen Kunze, Emil Matús, Gerhard P. Fettweis |
ASIP Decoder Architecture for Convolutional and LDPC Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 2457-2460, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Andreas Genser, Christian Bachmann, Christian Steger, Jos Hulzink, Mladen Berekovic |
Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 177-182, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Ha-young Jeong, Min-young Cho, Won Hur, Yong-Surk Lee |
A Partial Access Mechanism on a Register for Low-Cost Embedded Multimedia ASIP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 91-C(7), pp. 1171-1174, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song 0002, Satoshi Goto |
Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(6), pp. 1478-1487, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Sergio Saponara, Michele Casula, Luca Fanucci |
ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Real Time Image Process. ![In: J. Real Time Image Process. 3(3), pp. 201-216, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Olivier Muller, Amer Baghdadi, Michel Jézéquel |
From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: The 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, Shortening the Path from Specification to Prototype, 2-5 June 2008, Monterey, California, USA, pp. 128-134, 2008, IEEE Computer Society, 978-0-7695-3180-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | N. T. Ngo, Trang T. T. Do, Thinh M. Le, Y. S. Kadam, Amine Bermak |
ASIP-controlled Inverse Integer Transform for H.264/AVC Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: The 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, Shortening the Path from Specification to Prototype, 2-5 June 2008, Monterey, California, USA, pp. 158-164, 2008, IEEE Computer Society, 978-0-7695-3180-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Jun-Young Lee, Jae-Jin Lee, MooKyoung Jeong, Nak-Woong Eum, Seongmo Park |
A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3462-3465, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Nima Karimpour Darav, Shaahin Hessabi |
Polymorphism-Aware Common Bus in an Object-Oriented ASIP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSICC ![In: Advances in Computer Science and Engineering - 13th International CSI Computer Conference, CSICC 2008, Kish Island, Iran, March 9-11, 2008 Revised Selected Papers, pp. 115-122, 2008, 978-3-540-89984-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Zheng Shen, Hu He 0001, Yanjun Zhang, Yihe Sun |
A Video Specific Instruction Set Architecture for ASIP design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2007, pp. 58431:1-58431:7, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Oliver Schliebusch, Heinrich Meyr, Rainer Leupers |
Optimized ASIP synthesis from architecture description language models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2007 |
RDF |
|
20 | Carsten Gremzow |
Compiled low-level virtual instruction set simulation and profiling for code partitioning and ASIP-synthesis in hardware/software co-design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCSC ![In: Proceedings of the 2007 Summer Computer Simulation Conference, SCSC 2007, San Diego, California, USA, July 16-19, 2007, pp. 741-748, 2007, Simulation Councils, Inc., 1-56555-316-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
hardware/software co-synthesis, instruction set architecture simulation, quantitative dataflow analysis, profiling, coarse-grained parallelism, LLVM |
20 | Reimund Klemm, Javier Prieto Sabugo, Hendrik Ahlendorf, Gerhard P. Fettweis |
Using LISATek for the Design of an ASIP Core including Floating Point Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Erlangen, Germany, March 5-7, 2007, pp. 161-169, 2007, Shaker, 978-3-8322-5956-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
20 | Michael De Nil, Lennart Yseboodt, Frank Bouwens, Jos Hulzink, Mladen Berekovic, Jos Huisken, Jef L. van Meerbergen |
Ultra Low Power ASIP Design for Wireless Sensor Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007, pp. 1352-1355, 2007, IEEE, 978-1-4244-1377-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Gert Goossens |
Multi-ASIP SoCs - or how to design ultra-low power architectures for wireless and multi-media systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: International Symposium on System-on-Chip, SoC 2007, Tampere, Finland, November 20-21, 2007, pp. 1, 2007, IEEE, 978-1-4244-1368-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Paul Morgan, Richard Taylor |
ASIP Instruction Encoding for Energy and Area Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 797-800, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Angela Yun Zhu, Xi Li 0003, Laurence Tianruo Yang, Jun Yang |
A Fast Instruction Set Evaluation Method for ASIP Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2006, Seoul, Korea, August 1-4, 2006, Proceedings, pp. 489-498, 2006, Springer, 3-540-36679-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Zhou Zhixiong, Yang Xu, He Hu 0002, Yihe Sun |
A Retargetable Compiler of VLIW ASIP for Media Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2006 International Conference on Embedded Systems & Applications, Las Vegas, Nevada, USA, June 26-29, 2006, pp. 46-52, 2006, CSREA Press, 1-60132-017-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
20 | Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Memory Access Micro-Profiling for ASIP Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 255-262, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Vijayakumar Kalyanaraman, Matthias Müller 0002, Sven Simon 0001, Mario Steinert, Holger Gryska |
Power reduction of ASIPs by distributing the workload on several ASIP-instances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: Proceedings of the 2005 European Conference on Circuit Theory and Design, ECCTD 2005, Cork, Ireland, August 29th - September 1st 2005, pp. 457-460, 2005, IEEE, 0-7803-9066-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler |
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 193-199, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Fine-grained application source code profiling for ASIP design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 329-334, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
profiling, ASIPs, codesign, customizable processors |
20 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
An efficient technique for exploring register file size in ASIP design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12), pp. 1693-1699, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Heinrich Meyr |
Application specific instruction-set processors (ASIP's) for wireless communications: design, cost, and energy efficiency vs. flexibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: Proceedings of the 2004 International Symposium on System-on-Chip, Tampere, Finland, November 16-18, 2004, pp. 1-2, 2004, IEEE, 0-7803-8558-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Yeong-Geol Kim, Tag-Gon Kim |
An Efficient Method for System-Level Exploration of Global Optimum in a Parameterized ASIP Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12), pp. 3297-3302, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
20 | Newton Cheung, Jörg Henkel, Sri Parameswaran |
Rapid Configuration & Instruction Selection for an ASIP: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Embedded Software for SoC ![In: Embedded Software for SoC, pp. 403-417, 2003, Kluwer / Springer, 978-1-4020-7528-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Jun Kyoung Kim, Tag Gon Kim |
Trace-driven rapid pipeline architecture evaluation scheme for ASIP design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 129-134, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai |
Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP (2) ![In: 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '03, Hong Kong, April 6-10, 2003, pp. 485-488, 2003, IEEE, 0-7803-7663-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft |
Object-Oriented ASIP Design and Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2003, September 23-26, 2003, Frankfurt, Germany, Proceedings, pp. 680-692, 2003, ECSI. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
20 | Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai |
Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, ICME 2003, 6-9 July 2003, Baltimore, MD, USA, pp. 149-152, 2003, IEEE Computer Society, 0-7803-7965-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai |
Design space exploration for DSP applications using the ASIP development system PEAS-III. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2002, May 13-17 2002, Orlando, Florida, USA, pp. 3168-3171, 2002, IEEE, 0-7803-7402-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Andreas Hoffmann 0002, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr |
A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2001, San Jose, CA, USA, November 4-8, 2001, pp. 625-630, 2001, IEEE Computer Society, 0-7803-7249-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Sérgio Akira Ito, Luigi Carro, Ricardo Pezzuol Jacobi |
System Design Based on Single Language and Single-Chip Java ASIP Microcontroller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 703-707, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Henjo Schot, Henk Corporaal |
Automated Design of an ASIP for Image Processing Applications (Research Note). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29 - September 1, 2000, Proceedings., pp. 1105-1109, 2000, Springer, 3-540-67956-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi |
PEAS-III: An ASIP Design Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 430-436, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Jean-Gabriel Cousin, Olivier Sentieys, Daniel Chillet |
Multi-algorithm ASIP synthesis and power estimation for DSP applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 621-624, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | I-Horng Jeng, Feipei Lai, Yuh-Dar Tseng |
FACE: Fine-tuned Architecture Codesign Environment for ASIP Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 4(4), pp. 329-351, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Kayhan Küçükçakar |
An ASIP design methodology for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Seventh International Workshop on Hardware/Software Codesign, CODES 1999, Rome, Italy, 1999, pp. 17-21, 1999, ACM, 1-58113-132-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Michael Gschwind |
Instruction set selection for ASIP design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Seventh International Workshop on Hardware/Software Codesign, CODES 1999, Rome, Italy, 1999, pp. 7-11, 1999, ACM, 1-58113-132-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Margarida F. Jacome, Gustavo de Veciana |
Lower bound on latency for VLIW ASIP datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 261-269, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Hoon Choi, Ju Hwan Yi, Jong-Yeol Lee, In-Cheol Park, Chong-Min Kyung |
Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 939-944, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Alauddin Yousif Alomary |
A hardware/software codesign partitioner for ASIP design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of Third International Conference on Electronics, Circuits, and Systems, ICECS 1996, Rodos, Greece, October 13-16, 1996, pp. 251-254, 1996, IEEE, 0-7803-3650-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
20 | Christian Veith, Klaus Buchenrieder, Andreas Pyttel |
Mapping statechart models onto an FPGA-based ASIP architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996, pp. 184-189, 1996, IEEE Computer Society Press, 0-8186-7573-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
20 | Rainer Leupers, Peter Marwedel |
Instruction-Set Modeling for ASIP Code Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 77-80, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
20 | Clifford Liem, Trevor C. May, Pierre G. Paulin |
Instruction-Set Matching and Selection for DSP and ASIP Code Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDAC-ETC-EUROASIC ![In: EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France, pp. 31-37, 1994, IEEE Computer Society, 0-8186-5410-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
20 | Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi |
An ASIP instruction set optimization algorithm with functional module sharing constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993, pp. 526-532, 1993, IEEE Computer Society / ACM, 0-8186-4490-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Andreas Loos, Michael Schmidt 0004, Dietmar Fey, Jens Grobel |
Dynamically Programmable Image Processor for Compact Vision Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 10th IEEE International Conference on Computer and Information Technology, CIT 2010, Bradford, West Yorkshire, UK, June 29-July 1, 2010, pp. 33-40, 2010, IEEE Computer Society, 978-0-7695-4108-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Embedded image processors, dynamically programmable ASIP |
18 | Per Karlström, Wenbiao Zhou, Dake Liu |
Operation Classification for Control Path Synthetization with NoGAP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Seventh International Conference on Information Technology: New Generations, ITNG 2010, Las Vegas, Nevada, USA, 12-14 April 2010, pp. 1195-1200, 2010, IEEE Computer Society, 978-0-7695-3984-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Control path, CAD, Pipelining, ADL, ASIP, RTL |
18 | David Novo, Min Li 0001, Robert Fasthuber, Praveen Raghavan, Francky Catthoor |
Exploiting finite precision information to guide data-flow mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 248-253, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
finite precision, mapping efficiency, ASIP |