Search results for "ASIP"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Yuko Nakase, Sadahiro Kimura	Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology.	IPSJ Trans. Syst. LSI Des. Methodol.	2012	DBLP DOI BibTeX RDF
20	Paolo Meloni, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, Menno Lindwer	Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper.	VLSI Design	2012	DBLP DOI BibTeX RDF
20	Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre	Loop Acceleration Exploration for ASIP Architecture.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
20	Hsuanchun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda	A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
20	Mahmoud A. Said, Omar A. Nasr, Ahmed F. Shalash	Embedded reconfigurable synchronization & acquisition ASIP for a multi-standard OFDM receiver.	EURASIP J. Embed. Syst.	2012	DBLP DOI BibTeX RDF
20	Hanan M. Hassan, Karim Mohamed, Ahmed F. Shalash	Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine.	EURASIP J. Embed. Syst.	2012	DBLP DOI BibTeX RDF
20	Paolo Meloni, Sebastiano Pomata, Luigi Raffo, Roberta Piscitelli, Andy D. Pimentel	Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems.	ICSAMOS	2012	DBLP DOI BibTeX RDF
20	Yifan Bo, Jun Han 0003, Yao Zou, Xiaoyang Zeng	A low power ASIP for precision configurable FFT processing.	APSIPA	2012	DBLP BibTeX RDF
20	Quan Jinguo, Jinbin Ju, Qian Chen, Yan Zhang	Fine-grained analysis and design of ASIP instruction set for application of encryption.	ICNC	2012	DBLP DOI BibTeX RDF
20	Sebastiano Pomata, Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Menno Lindwer	Exploiting binary translation for fast ASIP design space exploration on FPGAs.	DATE	2012	DBLP DOI BibTeX RDF
20	Bertrand Le Gal, Christophe Jégo	Design of an ASIP LDPC Decoder Compliant with Digital Communication Standards.	SiPS	2012	DBLP DOI BibTeX RDF
20	Zhongbo Wang, Zhiping Jia, Lei Ju 0001, Renhai Chen	ASIP-based Design and Implementation of RSA for Embedded Systems.	HPCC-ICESS	2012	DBLP DOI BibTeX RDF
20	Jochen Rust, Steffen Paul	Design and implementation of a neurocomputing ASIP for environmental monitoring in WSN.	ICECS	2012	DBLP DOI BibTeX RDF
20	Hsuanchun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda	A Reconfigurable High Performance ASIP Engine for Image Signal Processing.	IPDPS Workshops	2012	DBLP DOI BibTeX RDF
20	Xiaolin Chen, Andreas Minwegen, Yahia Hassan, David Kammler, Shuai Li, Torsten Kempf, Anupam Chattopadhyay, Gerd Ascheid	FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP.	FCCM	2012	DBLP DOI BibTeX RDF
20	Joon Ho Hyun, Myung Jin Park, Young Hwan Kim, Hi-Seok Kim	ASIP-based control system for LED matrix display.	ISCAS	2012	DBLP DOI BibTeX RDF
20	Bertrand Le Gal, Christophe Jégo	FPGA prototyping of an ASIP LDPC decoder for the DVB-T2 standard.	DASIP	2012	DBLP BibTeX RDF
20	Mochamad Asri, Hsuanchun Liao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda	A reconfigurable ASIP-based approach for high performance image signal processing.	APCCAS	2012	DBLP DOI BibTeX RDF
20	Antoine Trouvé, Kazuaki J. Murakami	Augmenting DR-ASIP flexibility through multi-mode custom instructions.	SIGARCH Comput. Archit. News	2011	DBLP DOI BibTeX RDF
20	Zdenek Prikryl, Jakub Kroustek, Tomas Hruska, Dusan Kolár	Fast just-in-time translated simulator for ASIP design.	DDECS	2011	DBLP DOI BibTeX RDF
20	Gregor Schewior, Holger Flatt, Carsten Dolar, Christian Banz, Holger Blume	A hardware accelerated configurable ASIP architecture for embedded real-time video-based driver assistance applications.	ICSAMOS	2011	DBLP DOI BibTeX RDF
20	Esther P. Adeva, Björn Mennenga, Gerhard P. Fettweis	Scalable ASIP implementation and parallelization of a MIMO sphere detector.	ICSAMOS	2011	DBLP DOI BibTeX RDF
20	Jochen Rust, Christof Osewold, Steffen Paul	Implementation of a Low Power Low Complexity ASIP for various Sphere Decoding Algorithms.	EW	2011	DBLP BibTeX RDF
20	Purushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel	A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding.	DATE	2011	DBLP DOI BibTeX RDF
20	Reza Faghih Mirzaee, Mohammad Eshghi	Design of an ASIP IDEA crypto processor.	NESEA	2011	DBLP DOI BibTeX RDF
20	Jinbin Ju, Quan Jinguo, Qian Chen, Yan Zhang	Fine-grained analysis and design of ASIP instruction set for application of encryption.	RACS	2011	DBLP DOI BibTeX RDF
20	Ji Qiu, Xiang Gao, Yifei Jiang, Xu Xiao	An ultra-fast hybrid simulation framework for ASIP.	ICECS	2011	DBLP DOI BibTeX RDF
20	Mariusz Grad, Christian Plessl	Just-in-Time Instruction Set Extension - Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
20	Anup Sarma, Soubhagya Sutar, Vijay Kumar Sharma, Kamala Kanta Mahapatra	An ASIP for image enhancement applications in spatial domain using LISA.	ReTIS	2011	DBLP DOI BibTeX RDF
20	Rachid Al-Khayat, Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel	Area and throughput optimized ASIP for multi-standard turbo decoding.	International Symposium on Rapid System Prototyping	2011	DBLP DOI BibTeX RDF
20	Hong Chinh Doan, Haris Javaid, Sri Parameswaran	Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos.	ESTIMedia	2011	DBLP DOI BibTeX RDF
20	Simon Rajotte, Diana Carolina Gil, J. M. Pierre Langlois	Combining ISA extensions and subsetting for improved ASIP performance and cost.	ISCAS	2011	DBLP DOI BibTeX RDF
20	Hanan M. Hassan, Ahmed F. Shalash, Karim Mohamed	FPGA Implementation of an ASIP for high throughput DFT/DCT 1D/2D engine.	ISCAS	2011	DBLP DOI BibTeX RDF
20	Hee Kwan Eun, Sung Jo Hwang, Myung Hoon Sunwoo, Young Hwan Kim, Hi-Seok Kim	Integer-pel Motion Estimation specific instructions and their hardware architecture for ASIP.	ISCAS	2011	DBLP DOI BibTeX RDF
20	Christian Brehm, Thomas Ilnseher, Norbert Wehn	A scalable multi-ASIP architecture for standard compliant trellis decoding.	ISOCC	2011	DBLP DOI BibTeX RDF
20	Takaya Kaji, Shingo Yoshizawa, Yoshikazu Miyanaga	Development of an ASIP-based singular value decomposition processor in SVD-MIMO systems.	ISPACS	2011	DBLP DOI BibTeX RDF
20	Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura	Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP).	IPSJ Trans. Syst. LSI Des. Methodol.	2010	DBLP DOI BibTeX RDF
20	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions.	IPSJ Trans. Syst. LSI Des. Methodol.	2010	DBLP DOI BibTeX RDF
20	Fethi Tlili, Akram Ghorbel	ASIP Solution for Implementation of H.264 Multi Resolution Motion Estimation.	Int. J. Commun. Netw. Syst. Sci.	2010	DBLP DOI BibTeX RDF
20	Götz Kappen, Lothor Kurz, O. Priebe, Tobias G. Noll	Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers.	J. Signal Process. Syst.	2010	DBLP DOI BibTeX RDF
20	Matthias Alles, Timo Vogt, Christian Brehm, Norbert Wehn	FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
20	Ioanna Tsekoura, Georgios N. Selimis, Jos Hulzink, Francky Catthoor, Jos Huisken, Harmke de Groot, Constantinos E. Goutis	Exploration of cryptographic ASIP designs for wireless sensor nodes.	ICECS	2010	DBLP DOI BibTeX RDF
20	Emrah Tasdemir, Götz Kappen, Tobias G. Noll	Potential of using block floating point arithmetic in ASIP-based GNSS-receivers.	ASAP	2010	DBLP DOI BibTeX RDF
20	Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel	ASIP-Based Universal Demapper for Multiwireless Standards.	IEEE Embed. Syst. Lett.	2009	DBLP DOI BibTeX RDF
20	Olivier Muller, Amer Baghdadi, Michel Jézéquel	From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
20	David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rainer Leupers, Rudolf Mathar, Heinrich Meyr	Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves.	IACR Cryptol. ePrint Arch.	2009	DBLP BibTeX RDF
20	Atif Raza Jafri, Daoud Karakolah, Amer Baghdadi, Michel Jézéquel	ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications.	DATE	2009	DBLP DOI BibTeX RDF
20	Christian Bachmann, Andreas Genser, Jos Hulzink, Mladen Berekovic, Christian Steger	A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing.	DATE	2009	DBLP DOI BibTeX RDF
20	Praveen Raghavan, Francky Catthoor	Register file exploration for a multi-standard wireless forward error correction ASIP.	SiPS	2009	DBLP DOI BibTeX RDF
20	Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid	Task management in MPSoCs: An ASIP approach.	ICCAD	2009	DBLP DOI BibTeX RDF
20	Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel	Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer.	IEEE International Workshop on Rapid System Prototyping	2009	DBLP DOI BibTeX RDF
20	Steffen Kunze, Emil Matús, Gerhard P. Fettweis	ASIP Decoder Architecture for Convolutional and LDPC Codes.	ISCAS	2009	DBLP DOI BibTeX RDF
20	Andreas Genser, Christian Bachmann, Christian Steger, Jos Hulzink, Mladen Berekovic	Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing.	ASAP	2009	DBLP DOI BibTeX RDF
20	Ha-young Jeong, Min-young Cho, Won Hur, Yong-Surk Lee	A Partial Access Mechanism on a Register for Low-Cost Embedded Multimedia ASIP.	IEICE Trans. Electron.	2008	DBLP DOI BibTeX RDF
20	Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song 0002, Satoshi Goto	Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2008	DBLP DOI BibTeX RDF
20	Sergio Saponara, Michele Casula, Luca Fanucci	ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing.	J. Real Time Image Process.	2008	DBLP DOI BibTeX RDF
20	Olivier Muller, Amer Baghdadi, Michel Jézéquel	From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding.	IEEE International Workshop on Rapid System Prototyping	2008	DBLP DOI BibTeX RDF
20	N. T. Ngo, Trang T. T. Do, Thinh M. Le, Y. S. Kadam, Amine Bermak	ASIP-controlled Inverse Integer Transform for H.264/AVC Compression.	IEEE International Workshop on Rapid System Prototyping	2008	DBLP DOI BibTeX RDF
20	Jun-Young Lee, Jae-Jin Lee, MooKyoung Jeong, Nak-Woong Eum, Seongmo Park	A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Nima Karimpour Darav, Shaahin Hessabi	Polymorphism-Aware Common Bus in an Object-Oriented ASIP.	CSICC	2008	DBLP DOI BibTeX RDF
20	Zheng Shen, Hu He 0001, Yanjun Zhang, Yihe Sun	A Video Specific Instruction Set Architecture for ASIP design.	VLSI Design	2007	DBLP DOI BibTeX RDF
20	Oliver Schliebusch, Heinrich Meyr, Rainer Leupers	Optimized ASIP synthesis from architecture description language models.		2007	RDF
20	Carsten Gremzow	Compiled low-level virtual instruction set simulation and profiling for code partitioning and ASIP-synthesis in hardware/software co-design.	SCSC	2007	DBLP BibTeX RDF	hardware/software co-synthesis, instruction set architecture simulation, quantitative dataflow analysis, profiling, coarse-grained parallelism, LLVM
20	Reimund Klemm, Javier Prieto Sabugo, Hendrik Ahlendorf, Gerhard P. Fettweis	Using LISATek for the Design of an ASIP Core including Floating Point Operations.	MBMV	2007	DBLP BibTeX RDF
20	Michael De Nil, Lennart Yseboodt, Frank Bouwens, Jos Hulzink, Mladen Berekovic, Jos Huisken, Jef L. van Meerbergen	Ultra Low Power ASIP Design for Wireless Sensor Nodes.	ICECS	2007	DBLP DOI BibTeX RDF
20	Gert Goossens	Multi-ASIP SoCs - or how to design ultra-low power architectures for wireless and multi-media systems.	SoC	2007	DBLP DOI BibTeX RDF
20	Paul Morgan, Richard Taylor	ASIP Instruction Encoding for Energy and Area Reduction.	DAC	2007	DBLP DOI BibTeX RDF
20	Angela Yun Zhu, Xi Li 0003, Laurence Tianruo Yang, Jun Yang	A Fast Instruction Set Evaluation Method for ASIP Designs.	EUC	2006	DBLP DOI BibTeX RDF
20	Zhou Zhixiong, Yang Xu, He Hu 0002, Yihe Sun	A Retargetable Compiler of VLIW ASIP for Media Signal Processing.	ESA	2006	DBLP BibTeX RDF
20	Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Memory Access Micro-Profiling for ASIP Design.	DELTA	2006	DBLP DOI BibTeX RDF
20	Vijayakumar Kalyanaraman, Matthias Müller 0002, Sven Simon 0001, Mario Steinert, Holger Gryska	Power reduction of ASIPs by distributing the workload on several ASIP-instances.	ECCTD	2005	DBLP DOI BibTeX RDF
20	Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler	Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation.	ICCD	2005	DBLP DOI BibTeX RDF
20	Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Fine-grained application source code profiling for ASIP design.	DAC	2005	DBLP DOI BibTeX RDF	profiling, ASIPs, codesign, customizable processors
20	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	An efficient technique for exploring register file size in ASIP design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
20	Heinrich Meyr	Application specific instruction-set processors (ASIP's) for wireless communications: design, cost, and energy efficiency vs. flexibility.	SoC	2004	DBLP DOI BibTeX RDF
20	Yeong-Geol Kim, Tag-Gon Kim	An Efficient Method for System-Level Exploration of Global Optimum in a Parameterized ASIP Design.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2003	DBLP BibTeX RDF
20	Newton Cheung, Jörg Henkel, Sri Parameswaran	Rapid Configuration & Instruction Selection for an ASIP: A Case Study.	Embedded Software for SoC	2003	DBLP DOI BibTeX RDF
20	Jun Kyoung Kim, Tag Gon Kim	Trace-driven rapid pipeline architecture evaluation scheme for ASIP design.	ASP-DAC	2003	DBLP DOI BibTeX RDF
20	Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai	Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III.	ICASSP (2)	2003	DBLP DOI BibTeX RDF
20	Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft	Object-Oriented ASIP Design and Synthesis.	FDL	2003	DBLP BibTeX RDF
20	Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai	Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III.	ICME	2003	DBLP DOI BibTeX RDF
20	Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai	Design space exploration for DSP applications using the ASIP development system PEAS-III.	ICASSP	2002	DBLP DOI BibTeX RDF
20	Andreas Hoffmann 0002, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr	A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA.	ICCAD	2001	DBLP DOI BibTeX RDF
20	Sérgio Akira Ito, Luigi Carro, Ricardo Pezzuol Jacobi	System Design Based on Single Language and Single-Chip Java ASIP Microcontroller.	DATE	2000	DBLP DOI BibTeX RDF
20	Henjo Schot, Henk Corporaal	Automated Design of an ASIP for Image Processing Applications (Research Note).	Euro-Par	2000	DBLP DOI BibTeX RDF
20	Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi	PEAS-III: An ASIP Design Environment.	ICCD	2000	DBLP DOI BibTeX RDF
20	Jean-Gabriel Cousin, Olivier Sentieys, Daniel Chillet	Multi-algorithm ASIP synthesis and power estimation for DSP applications.	ISCAS	2000	DBLP DOI BibTeX RDF
20	I-Horng Jeng, Feipei Lai, Yuh-Dar Tseng	FACE: Fine-tuned Architecture Codesign Environment for ASIP Development.	Des. Autom. Embed. Syst.	1999	DBLP DOI BibTeX RDF
20	Kayhan Küçükçakar	An ASIP design methodology for embedded systems.	CODES	1999	DBLP DOI BibTeX RDF
20	Michael Gschwind	Instruction set selection for ASIP design.	CODES	1999	DBLP DOI BibTeX RDF
20	Margarida F. Jacome, Gustavo de Veciana	Lower bound on latency for VLIW ASIP datapaths.	ICCAD	1999	DBLP DOI BibTeX RDF
20	Hoon Choi, Ju Hwan Yi, Jong-Yeol Lee, In-Cheol Park, Chong-Min Kyung	Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software.	DAC	1999	DBLP DOI BibTeX RDF
20	Alauddin Yousif Alomary	A hardware/software codesign partitioner for ASIP design.	ICECS	1996	DBLP DOI BibTeX RDF
20	Christian Veith, Klaus Buchenrieder, Andreas Pyttel	Mapping statechart models onto an FPGA-based ASIP architecture.	EURO-DAC	1996	DBLP DOI BibTeX RDF
20	Rainer Leupers, Peter Marwedel	Instruction-Set Modeling for ASIP Code Generation.	VLSI Design	1996	DBLP DOI BibTeX RDF
20	Clifford Liem, Trevor C. May, Pierre G. Paulin	Instruction-Set Matching and Selection for DSP and ASIP Code Generation.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
20	Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi	An ASIP instruction set optimization algorithm with functional module sharing constraint.	ICCAD	1993	DBLP DOI BibTeX RDF
18	Andreas Loos, Michael Schmidt 0004, Dietmar Fey, Jens Grobel	Dynamically Programmable Image Processor for Compact Vision Systems.	CIT	2010	DBLP DOI BibTeX RDF	Embedded image processors, dynamically programmable ASIP
18	Per Karlström, Wenbiao Zhou, Dake Liu	Operation Classification for Control Path Synthetization with NoGAP.	ITNG	2010	DBLP DOI BibTeX RDF	Control path, CAD, Pipelining, ADL, ASIP, RTL
18	David Novo, Min Li 0001, Robert Fasthuber, Praveen Raghavan, Francky Catthoor	Exploiting finite precision information to guide data-flow mapping.	DAC	2010	DBLP DOI BibTeX RDF	finite precision, mapping efficiency, ASIP