Search results for "DLL"

Hits ?▲	Authors	Title	Venue	Year	Link
19	Dongmin Yoon, Dennis Sylvester, David T. Blaauw	A 5.58nW 32.768kHz DLL-assisted XO for real-time clocks in wireless sensing applications.	ISSCC	2012	DBLP DOI BibTeX RDF
19	Sangyong Park, Sungmoon Park, Joonhong Park, Donghyun Baek	Design of 13.56 MHz ASK transmitter for near field communication using a DLL architecture.	ISCAS	2012	DBLP DOI BibTeX RDF
19	Min-Han Hsieh, Bing-Feng Lin, Yu-Shun Wang, Hao-Huei Chang, Charlie Chung-Ping Chen	A 2 - 8 GHz multi-phase distributed DLL using phase insertion in 90 nm.	ISCAS	2012	DBLP DOI BibTeX RDF
19	Shuai Chen, Hao Li, Kai Jia, Yue Wang, Xiaobing Shi, Feng Zhang 0014	A fast-lock-in wide-range harmonic-free all-digital DLL with a complementary delay line.	ISCAS	2012	DBLP DOI BibTeX RDF
19	Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour	A DLL-based injection-locked frequency synthesizer for WiMedia UWB.	ISCAS	2012	DBLP DOI BibTeX RDF
19	Hung-Wen Lin, Hsin-Lin Hu, Wu-Wei Lin	A DLL-based FSK demodulator for 5.8GHz DSRC/ETC RF receiver.	ISOCC	2012	DBLP DOI BibTeX RDF
19	Haizheng Guo, Tad A. Kwasniewski	A DLL-based fractional-N frequency synthesizer with a programmable injection clock.	CCECE	2012	DBLP DOI BibTeX RDF
19	Young-Sang Kim, Seon-Kyoo Lee, Hong-June Park, Jae-Yoon Sim	A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
19	Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Suki Kim	A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
19	Hyung-Joon Chi, Young-Ho Choi, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park, Jong-Jin Lim, Pil-Sung Kang, Bu-Yeol Lee, Jin-Cheol Hong, Hee-Sub Lee	A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL.	IEEE Trans. Circuits Syst. II Express Briefs	2011	DBLP DOI BibTeX RDF
19	Mohammad Gholami, Gholamreza Ardeshir, Hojat Ghonoodi	A novel architecture for low voltage-low power DLL-based frequency multipliers.	IEICE Electron. Express	2011	DBLP DOI BibTeX RDF
19	Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei	Area efficient phase calibration of a 1.6 GHz multiphase DLL.	CICC	2011	DBLP DOI BibTeX RDF
19	Sungchun Jang, Heesoo Song, Seokmin Ye, Deog-Kyoon Jeong	A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit.	ISSCC	2011	DBLP DOI BibTeX RDF
19	Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, Wei Hwang	Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation.	ISLPED	2011	DBLP BibTeX RDF
19	Seungwook Paek, Jiehwan Oh, Sang-Hye Chung, Lee-Sup Kim	Area-efficient dynamic thermal management unit using MDLL with shared DLL scheme for many-core processors.	ISCAS	2011	DBLP DOI BibTeX RDF
19	Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Yi-Chi Wu, Bing-Feng Lin, Hsien-Chen Chiu, Charlie Chung-Ping Chen	A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique.	ISCAS	2011	DBLP DOI BibTeX RDF
19	Bin He, Tie-Jun Lu, Zong-Min Wang, Tie L. Zhang	A Wide-Range Edge-Combining DLL with a Charge Pump for Low Spur.	DASC	2011	DBLP DOI BibTeX RDF
19	Jong-Chern Lee, Sin-Hyun Jin, Dae-Suk Kim, Young Jun Ku, Chul Kim, Byung-Kwon Park, Hong-Gyeom Kim, Seong-Jun Ahn, Jaejin Lee, Sung-Joo Hong	A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM.	A-SSCC	2011	DBLP DOI BibTeX RDF
19	San-Jeow Cheng, Lin Qiu, Yuanjin Zheng, Chun-Huat Heng	50-250 MHz ΔΣ DLL for Clock Synchronization.	IEEE J. Solid State Circuits	2010	DBLP DOI BibTeX RDF
19	Sunghwa Ok, Kyunghoon Chung, Jabeom Koo, Chulwoo Kim	An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
19	Bo Ye	A wide-range all digital DLL for multiphase clock generation.	Microelectron. J.	2010	DBLP DOI BibTeX RDF
19	Kyungho Ryu, Dong Hun Jung, Seong-Ook Jung	A DLL based clock generator for low-power mobile SoCs.	IEEE Trans. Consumer Electron.	2010	DBLP DOI BibTeX RDF
19	Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung	A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface.	IEEE Trans. Consumer Electron.	2010	DBLP DOI BibTeX RDF
19	Lei Wang, Leibo Liu, Hongyi Chen	An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL.	IEEE Trans. Circuits Syst. II Express Briefs	2010	DBLP DOI BibTeX RDF
19	Fang-Ren Liao, Shey-Shi Lu	A Programmable Edge-Combining DLL With a Current-Splitting Charge Pump for Spur Suppression.	IEEE Trans. Circuits Syst. II Express Briefs	2010	DBLP DOI BibTeX RDF
19	Marco Zanuso, Paolo Madoglio, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita	Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
19	J. Berdajs, Zoran Bosnic	Extending applications using an advanced approach to DLL injection and API hooking.	Softw. Pract. Exp.	2010	DBLP DOI BibTeX RDF
19	Duo Sheng, Ching-Che Chung, Chen-Yi Lee	Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications.	IEICE Electron. Express	2010	DBLP DOI BibTeX RDF
19	Tae-Ho Kim, Sang-Ho Kim, Jin-Ku Kang	A DLL-based Clock Data Recovery with a modified input format.	IEICE Electron. Express	2010	DBLP DOI BibTeX RDF
19	Ding-Guo Lin, Bing-Hsun Lu, Herming Chiueh	An 100MHz to 1.6GHz DLL-based clock generator using a feedback-switching detector.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
19	Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, Kuo-Hsing Cheng	A 3 GHz DLL-based clock generator with stuck locking protection.	ICECS	2010	DBLP DOI BibTeX RDF
19	Heechai Kang, Kyungho Ryu, Donghwan Lee, Won Lee, SuHo Kim, JongRyun Choi, Seong-Ook Jung	Process variation tolerant all-digital multiphase DLL for DDR3 interface.	CICC	2010	DBLP DOI BibTeX RDF
19	Andrew Begel, Thomas Zimmermann 0001	Keeping up with your friends: function Foo, library Bar.DLL, and work item 24.	Web2SE@ICSE	2010	DBLP DOI BibTeX RDF
19	Sang-Ho Kim, Hyung-Min Park, Tae-Ho Kim, Jin-Ku Kang, Jin-Ho Kim, Jae-Youl Lee, Yoon-Kyung Choi, Myunghee Lee	A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOS.	SoCC	2010	DBLP DOI BibTeX RDF
19	Dongsuk Shin, Joo-Hwan Cho, Young-Jung Choi, Byong-Tae Chung	Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster.	SoCC	2010	DBLP DOI BibTeX RDF
19	Mohammad Gholami, Mohammad Sharifkhani, Saeed Saeedi	Modeling of DLL-based frequency multiplier in time and frequency domain with Matlab Simulink.	APCCAS	2010	DBLP DOI BibTeX RDF
19	Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Chulwoo Kim	A 7 ps Jitter 0.053 mm2 Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
19	Behzad Mesgarzadeh, Atila Alvandpour	A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
19	Byung-Guk Kim, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Soo-In Cho	A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
19	Keng-Jan Hsiao, Tai-Cheng Lee	An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
19	Cheng Jia, Linda Milor	A DLL Design for Testing I/O Setup and Hold Times.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
19	Owen Casha, Ivan Grech, Franck Badets, Dominique Morche, Joseph Micallef	Analysis of the Spur Characteristics of Edge-Combining DLL-Based Frequency Multipliers.	IEEE Trans. Circuits Syst. II Express Briefs	2009	DBLP DOI BibTeX RDF
19	Jabeom Koo, Sunghwa Ok, Chulwoo Kim	A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock.	IEEE Trans. Circuits Syst. II Express Briefs	2009	DBLP DOI BibTeX RDF
19	Nagaraj Channarayapatna Shivaramaiah, Andrew G. Dempster	A Novel Extended Tracking Range DLL for AltBOC Signals.	VTC Fall	2009	DBLP DOI BibTeX RDF
19	Xueyi Yu, Woogeun Rhee, Zhihua Wang 0001, Jung-Bae Lee, Changhyun Kim	A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation.	ISSCC	2009	DBLP DOI BibTeX RDF
19	Kyu-Hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman	A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS.	ISSCC	2009	DBLP DOI BibTeX RDF
19	Kyoungho Woo, Scott E. Meninger, Thucydides Xanthopoulos, Ethan Crain, Dongwan Ha, Donhee Ham	Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring.	ISSCC	2009	DBLP DOI BibTeX RDF
19	Lei Wang, Leibo Liu, Hongyi Chen	A Fast-locking and Wide-range Reversible SAR DLL.	ISCAS	2009	DBLP DOI BibTeX RDF
19	Xianggen Wang, Dengguo Feng, Purui Su	Reconstructing a Packed DLL Binary for Static Analysis.	ISPEC	2009	DBLP DOI BibTeX RDF
19	Yi-Ming Chang, Ming-Hung Chang, Wei Hwang	A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm.	SoCC	2009	DBLP DOI BibTeX RDF
19	Feng Lin, Roman A. Royer, Brian Johnson, Brent Keeth	A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
19	Sander L. J. Gierkink	Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
19	Keng-Jan Hsiao, Tai-Cheng Lee	The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
19	Samuel R. Buss, Jan Hoffmann 0002, Jan Johannsen	Resolution Trees with Lemmas: Resolution Refinements that Characterize DLL Algorithms with Clause Learning	CoRR	2008	DBLP BibTeX RDF
19	Samuel R. Buss, Jan Hoffmann 0002, Jan Johannsen	Resolution Trees with Lemmas: Resolution Refinements that Characterize DLL Algorithms with Clause Learning.	Log. Methods Comput. Sci.	2008	DBLP DOI BibTeX RDF
19	Chuan-Kang Liang, Rong-Jyi Yang, Shen-Iuan Liu	An All-Digital Fast-Locking Programmable DLL-Based Clock Generator.	IEEE Trans. Circuits Syst. I Regul. Pap.	2008	DBLP DOI BibTeX RDF
19	Fayez Mohamood, Mrinmoy Ghosh, Hsien-Hsin S. Lee	DLL-conscious instruction fetch optimization for SMT processors.	J. Syst. Archit.	2008	DBLP DOI BibTeX RDF
19	Chih-Hsing Lin, Ching-Te Chiu	A 2.64GHz wide range low power DLL-based frequency multiplier with CML circuits using adaptive body bias.	ICECS	2008	DBLP DOI BibTeX RDF
19	Kuo-Hsing Cheng, Chia-Wei Su, Meng-Jhe Wu, Yu-Ling Chang	A wide-range DLL-based clock generator with phase error calibration.	ICECS	2008	DBLP DOI BibTeX RDF
19	Behzad Mesgarzadeh, Atila Alvandpour	A 2-GHz 7-mW digital DLL-based frequency multiplier in 90-nm CMOS.	ESSCIRC	2008	DBLP DOI BibTeX RDF
19	Dongsuk Shin, Won-Joo Yun, Hyun-Woo Lee, Young-Jung Choi, Suki Kim, Chulwoo Kim	A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme.	ESSCIRC	2008	DBLP DOI BibTeX RDF
19	Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic	A 15 MHz - 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS.	ESSCIRC	2008	DBLP DOI BibTeX RDF
19	Sunghwa Ok, Jungmoon Kim, Gilwon Yoon, Hyunho Chu, Jaegeun Oh, Seon Wook Kim, Chulwoo Kim	A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor.	CICC	2008	DBLP DOI BibTeX RDF
19	Sander Gierkink	A 1V 15.6mW 1-2GHz -119dBc/Hz @ 200kHz clock multiplying DLL.	CICC	2008	DBLP DOI BibTeX RDF
19	Sander Gierkink	An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL.	ISSCC	2008	DBLP DOI BibTeX RDF
19	Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Shin-Deok Kang, Ji-Yeon Yang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim 0001, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyang-Hwa Choi, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Ye Seok Yang	A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.	ISSCC	2008	DBLP DOI BibTeX RDF
19	Keng-Jan Hsiao, Tai-Cheng Lee	A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation.	ISSCC	2008	DBLP DOI BibTeX RDF
19	Ro-Min Weng, Chun-Yu Liu, Yun-Chih Lu	A low jitter DLL-based pulsewidth control loop with wide duty cycle adjustment.	APCCAS	2008	DBLP DOI BibTeX RDF
19	Ki-Won Lee, Joo-Hwan Cho, Byoung-Jin Choi, Geun-Il Lee, Ho-Don Jung, Woo-Young Lee, Ki-Chon Park, Yongsuk Joo, Jaehoon Cha, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn	A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
19	Prabir C. Maulik, Douglas A. Mercer	A DLL-Based Programmable Clock Multiplier in 0.18-µm CMOS With -70 dBc Reference Spur.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
19	P. P. Sahu	Improvement of jitter transfer characteristics of a 9.95328Gb/s data recovery DLL using saw filter.	Comput. Electr. Eng.	2007	DBLP DOI BibTeX RDF
19	Matilde Sánchez Fernández, Miguel Aguilera-Forero, Ana García Armada	Performance Analysis and Parameter Optimization of DLL and MEDLL in Fading Multipath Environments for Next Generation Navigation Receivers.	IEEE Trans. Consumer Electron.	2007	DBLP DOI BibTeX RDF
19	Chao-Chyun Chen, Jung-Yu Chang, Shen-Iuan Liu	A DLL-Based Variable-Phase Clock Buffer.	IEEE Trans. Circuits Syst. II Express Briefs	2007	DBLP DOI BibTeX RDF
19	Chi-Nan Chuang, Shen-Iuan Liu	A 0.5-5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump.	IEEE Trans. Circuits Syst. II Express Briefs	2007	DBLP DOI BibTeX RDF
19	Peng Chu, Yanlong Zhang, Zhiping Wen 0001, Lixin Yu	A Novel Digital DLL and Its Implement on the FPGA.	IMECS	2007	DBLP BibTeX RDF
19	Stephen K. Sunter, Aubin Roy	Purely Digital BIST for Any PLL or DLL.	ETS	2007	DBLP DOI BibTeX RDF
19	Jun-Hyun Bae, Jin-Ho Seo, Hwan-Seok Yeo, Jae-Whui Kim, Jae-Yoon Sim, Hong-June Park	An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface.	CICC	2007	DBLP DOI BibTeX RDF
19	Byung-Guk Kim, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Soo-In Cho	A DLL with Jitter-Reduction Techniques for DRAM Interfaces.	ISSCC	2007	DBLP DOI BibTeX RDF
19	Young-Sang Kim, Seung-Jin Park, Yong-Sub Kim, Dong-Bi Jang, Seh-Woong Jeong, Hong-June Park, Jae-Yoon Sim	A 40-to-800MHz Locking Multi-Phase DLL.	ISSCC	2007	DBLP DOI BibTeX RDF
19	Chi-Nan Chuang, Shen-Iuan Liu	A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology.	ISSCC	2007	DBLP DOI BibTeX RDF
19	Tai-Cheng Lee, Keng-Jan Hsiao	The design and analysis of a DLL-based frequency synthesizer for UWB application.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
19	Nikolaus Klemmer, Emad Hegazi	A DLL-biased, 14-bit DS analog-to-digital converter for GSM/GPRS/EDGE handsets.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
19	Daehyun Chung, Chunghyun Ryu, Hyungsoo Kim, Choonheung Lee, Jinhan Kim, Kicheol Bae, Jiheon Yu, Hoi-Jun Yoo, Joungho Kim	Chip-package hybrid clock distribution network and DLL for low jitter clock delivery.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
19	Jin-Han Kim, Young-Ho Kwak, Moo-young Kim, Soo-Won Kim, Chulwoo Kim	A 120-MHz-1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
19	Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski	A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
19	Pau Closas, Carles Fernández-Prades, Juan A. Fernández-Rubio	Bayesian Dll for Multipath Mitigation in Navigation Systems Using Particle Filters.	ICASSP (4)	2006	DBLP DOI BibTeX RDF
19	Enrico Giunchiglia, Marco Maratea	Solving Optimization Problems with DLL.	ECAI	2006	DBLP BibTeX RDF
19	Amber Han-Yuan Tan, Gu-Yeon Wei	Phase Mismatch Detection and Compensation for PLL/DLL Based Multi-Phase Clock Generator.	CICC	2006	DBLP DOI BibTeX RDF
19	Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski	An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur.	CICC	2006	DBLP DOI BibTeX RDF
19	Prabir C. Maulik, Douglas A. Mercer	A 150MHz-400MHz DLL-Based Programmable Clock Multiplier with -7OdBc Reference Spur in 0.18um CMOS.	CICC	2006	DBLP DOI BibTeX RDF
19	Amber Han-Yuan Tan, Gu-Yeon Wei	Adaptive-Bandwidth Mixing PLL/DLL Based Multi-Phase Clock Generator for Optimal Jitter Performance.	CICC	2006	DBLP DOI BibTeX RDF
19	Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho, Yasuyuki Doi, Makoto Hattori	A 0.03mm2 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface.	ISSCC	2006	DBLP DOI BibTeX RDF
19	Dong-Uk Lee, Hyun-Woo Lee, Ki Chang Kwean, Young-Kyoung Choi, Hyong Uk Moon, Seung-Wook Kwack, Shin-Deok Kang, Kwan-Weon Kim, Yong Ju Kim, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn, Joong Sik Kih	A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL.	ISSCC	2006	DBLP DOI BibTeX RDF
19	Behzad Mesgarzadeh, Atila Alvandpour	A 24-mW 0.02-mm2 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS.	SoCC	2006	DBLP DOI BibTeX RDF
19	Abdulkerim L. Coban, Mustafa H. Koroglu, Kashif A. Ahmed	A 2.5-3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
19	Seung-Jun Bae, Hyung-Joon Chi, Young-Soo Sohn, Hong-June Park	A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
19	Seok Kang, Beomsup Kim	A DLL-Based Frequency Synthesizer with Selective Reuse of a Delay Cell Scheme for 2.4 GHz ISM Band.	IEICE Trans. Electron.	2005	DBLP DOI BibTeX RDF
19	Kuo-Hsing Cheng, Yu-Lung Lo	A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs.	ESSCIRC	2005	DBLP DOI BibTeX RDF
19	Byung-Guk Kim, Kwang-Il Oh, Lee-Sup Kim, Dae-Woo Lee	A 500MHz DLL with second order duty cycle corrector for low jitter.	CICC	2005	DBLP DOI BibTeX RDF
19	Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun	Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application.	CICC	2005	DBLP DOI BibTeX RDF