| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Craig D. Ulmer, Adrian Javelo |
Floating-Point Unit Reuse in an FPGA Implementation of a Ray-Triangle Intersection Algorithm.  |
ERSA  |
2006 |
DBLP BibTeX RDF |
|
| 1 | Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano |
A Parametric Study of Scalable Interconnects on FPGAs. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Joshua Noseworthy, Miriam Leeser |
Efficient Use of Communications Between an FPGAs Embedded Processor and its Reconfigurable Logic. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Dirk Koch, Matthiaas Koerber, Jürgen Teich |
Searching RC5-Keys with Distributed Reconfigurable Computing. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Chun Hok Ho, Ka Fai Cedric Yiu, Jiaquan Huo, Sven Nordholm, Wayne Luk |
Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Minoru Watanabe, Fuminori Kobayashi |
Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Alireza Sarvi, Jenny Fan, Reto Stamm |
A Dual Configuration BIST-Based Modular Diagnostic Methodology for Embedded Cores in FPGAs. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Fei Wang 0009, Jack S. N. Jean |
Architectural Support for Runtime 2D Partial Reconfiguration. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Heng Tan, Ronald F. DeMara, Anuja Jayraj Thakkar, Abdel Ejnioui, Jason Sattler |
Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Giovanni Agosta, Francesco Bruschi, Marco D. Santambrogio, Donatella Sciuto |
Synthesis of Object Oriented Models on Reconfigurable Hardware. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Chuan He, Guan Qin, Mi Lu, Wei Zhao 0001 |
Group-Alignment based Accurate Floating-Point Summation on FPGAs. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Chris Rowen |
Using configurable processors for high-efficiency multiple-processor systems. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Cao Liang, Jing Ma 0006, Xinming Huang 0001 |
An FPGA based Co-Design Architecture for MIMO Lattice Decoders. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Sebastian Lange, Martin Middendorf |
Cache Architectures for Reconfigurable Hardware. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Paul M. Heysters |
Coarse-Grained Reconfigurable Computing for Power Aware Applications. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdogan |
Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC). |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Xuejun Liang, Qutaibah M. Malluhi |
Combinatorial Optimization in Mapping Generalized Template Matching onto Reconfigurable Computers. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Yvan Eustache, Jean-Philippe Diguet, Milad El Khodary |
RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart Camera. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki J. Murakami, Hamid Noori |
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Vincent Nollet, Prabhat Avasare, Diederik Verkest, Henk Corporaal |
Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Gerard K. Rauwerda, Gerard J. M. Smit, Casper R. W. van Benthem, Paul M. Heysters |
Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Ryan Glabb, Laurent Imbert, Graham A. Jullien, Arnaud Tisserand, Nicolas Veyrat-Charvillon |
Multi-Mode Operator for SHA-2 Hash Functions. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Vinay Sriram, David Kearney |
An Area Time Efficient Field Programmable Mersenne Twister Uniform Random Number Generator. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Maya B. Gokhale, Christopher D. Rickett, Justin L. Tripp, Chung Hsu, Ronald Scrofano |
Promises and Pitfalls of Reconfigurable Supercomputing. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Herwin Chan, Patrick Schaumont, Ingrid Verbauwhede |
Process Isolation for Reconfigurable Hardware. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik |
A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Minoru Watanabe, Fuminori Kobayashi |
Logic Synthesis and Place-and-Route Environment for ORGAs. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Steven Smith |
Dynamic Scheduling and Resource Management in Heterogeneous Computing Environments with Reconfigurable Hardware. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Janardhan Singaraju, John A. Chandy |
A Generic Lookup Cache Architecture for Network Processing Applications. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Mitchell J. Myjak, Jonathan Larson, José G. Delgado-Frias |
Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Marcel D. van de Burgwal, Gerard J. M. Smit, Gerard K. Rauwerda, Paul M. Heysters |
Hydra: An Energy-efficient and Reconfigurable Network Interface. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santambrogio, Donatella Sciuto |
SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Vinay Sriram, David Kearney |
A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Brian Holland, James Greco, Ian A. Troxel, Gabe Barfield, Vikas Aggarwal, Alan D. George |
Compile- and Run-Time Services for Distributed Hetergeneous Reconfigurable Computing. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Toomas P. Plaks (eds.) |
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2006, Las Vegas, Nevada, USA, June 26-29, 2006 |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Paul M. Heysters |
The Era of Reconfigurable Computing. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Saumil G. Merchant, Gregory D. Peterson, Seong G. Kong |
Intrinsic Embedded Hardware Evolution of Block-based Neural Networks. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Yu Bi, Gregory D. Peterson, G. Lee Warren, Robert J. Harrison |
Hardware Acceleration of Parallel Lagged-Fibonacci Pseudo Random Number Generation. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Chris Rowen |
The Reinvention of the Microprocessor. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi |
Differential Reconfiguration Architecture suitable for a Holographic Memory. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit |
A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Jeoong Sung Park, Hong-Jip Jung, Viktor K. Prasanna |
Efficient FPGA-based Implementations of the MIMO-OFDM Physical Layer. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Frank Hannig, Jürgen Teich |
Output Serialization for FPGA-based and Coarse-grained Processor Arrays. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Chris Sullivan |
What's the Future of C-Based Programmable SoC design? |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Youngsoo Kim, Dongsoo Kim, Daesun Park, Sungjo Kim |
A Non-LIinear Function Generator Using BRM. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä |
A Compact MD5 and SHA-1 Co-Implementation Utilizing Algorithm Similarities. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Steven A. Guccione |
Microprocessors: The New LUT. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Chen Chang, John Wawrzynek, Pierre-Yves Droz, Robert W. Brodersen |
The Design And Application Of A High-End Reconfigurable Computing System. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Ronald Scrofano, Gokul Govindu, Viktor K. Prasanna |
A Library of Parameterizable Floating-Point Cores for FPGAs and Their Application to Scientific Computing. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Janak Porwal, Sachin B. Patkar |
Algorithms For Scheduling Of Data Transfer Across FPGAs In A Grid. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Toomas P. Plaks (eds.) |
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2005, Las Vegas, Nevada, USA, June 27-30, 2005 |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Zain-ul-Abdin, Bertil Svensson |
Compiling Stream-Language Applications to a Reconfigurable Array Processor. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Ali Akoglu, Sethuraman Panchanathan |
Application Specific Reconfigurable Architecture Design. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Robert P. Colwell |
Where Intel's Microprocessor Architecture is Going. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Jingzhao Ou, Viktor K. Prasanna |
Rapid Arithmetic Level Simulation Based Energy Estimation for Hardware/Software Co-Design Using FPGAs. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Jing Ma 0006, Xinming Huang 0001 |
A SoPC Architecture of MIMO Sphere Decoder for Mobile Communications. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit |
A Multi-Pattern Scheduling Algorithm. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Zexin Pan, Juanjo Noguera, B. Earl Wells |
Improved Microarchitecture Support for Dynamic Task Scheduling on Reconfigurable Architectures. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Antonio Gentile, Salvatore Segreto, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile, Vincenzo Vullo |
CliffoSor, an Innovative FPGA-based Architecture for Geometric Algebra. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Brandon Thurmon, James M. McCollum, Gregory D. Peterson, Chris D. Cox, Nagiza F. Samatova, Gary S. Sayler, Michael L. Simpson |
Accelerating Exact Stochastic Simulation Using Reconfigurable Computing. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Wayne Luk, Sherif Yusuf, Morris Sloman, Geoffrey Brown, Emil C. Lupu, Naranker Dulay |
A Combined Hardware-Software Architecture for Network Flow. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Dror E. Maydan |
Configurable Processors and the Evolution of System-on-Chip Design. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Gerard K. Rauwerda, Gerard J. M. Smit, Werner Brugger |
Implementing an Adaptive Viterbi Algorithm in Coarse-Grained Reconfigurable Hardware. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Wim J. C. Melis, Kieron Turkington, Alexander Whitton, Wayne Luk, Peter Y. K. Cheung, Paul Metzgen |
Cell Based Motion Estimators for Reconfigurable Platforms. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo |
Flexible Core Reallocation for Virtex II Structures. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Sungjoon Jung, Tag Gon Kim |
An Operation and Interconnection Sharing Algorithm for Partially Reconfigurable Architectures. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna |
Area-Efficient Evaluation of a Class of Arithmetic Expressions Using Deeply Pipelined Floating-Point Cores. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Ryan A. DeVille, Ian A. Troxel, Alan D. George |
Performance Monitoring for Run-time Management of Reconfigurable Devices. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe |
Reconfigurable 1-Bit Processor Array with Reduced Wirng Area. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Fei Wang 0009, Jack S. N. Jean, Shuxia Sun |
Aspect Ratio Effects on Reconfigurable Computing. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Shaoyu Liu, Gregory D. Peterson, Seong G. Kong |
A Hardware Implementation of a Dynamically Adjustable Block-based Neural Network. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Heng Tan, Ronald F. DeMara |
A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Chuan He, Wei Zhao 0001, Mi Lu |
FPGA-Based High-Order Finite Difference Algorithm for 2D Acoustic Wave Propagation Problems. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Stefan Ihmor, Florian Dittmann 0001 |
Optimizing Interface Implementation Costs Using Runtime Reconfigurable Systems. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Charlé R. Rupp |
Reconfigurable Instruction Set Computing for Embedded Processing. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Wenrui Gong, Yan Meng, Gang Wang 0015, Ryan Kastner, Timothy Sherwood |
Data Partitioning and Optimizations for Reconfigurable Architectures. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Xuejun Liang, Jeffrey S. Vetter, Melissa C. Smith, Arthur S. Bland |
Balancing FPGA Resource Utilities. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Otsebele E. Nare, Charles T. Johnson-Bey |
A Reconfigurable Antialiasing Filter Design Using Multi-Abstraction Design Exploration Approach. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Gerard J. M. Smit, Gerard K. Rauwerda |
Reconfigurable Architectures for Adaptable Mobile Systems. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich |
Defragmenting the Module Layout of a Partially Reconfigurable Device. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Caaliph Andriamisaina, Catherine Dezan, Christophe Jégo, Bernard Pottier |
Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Abdel Ejnioui, Ronald F. DeMara |
Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Sanjay V. Rajopadhye, Kolin Paul |
A 1.5-D Architecture for Back-Propagation Training. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Donald W. Bouldin |
Enabling Killer Applications of Reconfigurable Systems: ERSA Keynote and Introduction. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Kenneth B. Kent, Zhao Yong, Jacqueline E. Rice, Troy Ronda |
Instance-Specific Versus Parameter-Specific Circuit Generation. |
ERSA |
2005 |
DBLP BibTeX RDF |
|
| 1 | Spencer Isaacson, Doran Wilde |
The Task-Resource Matrix: Control for a Distributed Reconfigurable Multi-Processor Hardware RTOS. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Tero Rissa, Wayne Luk, Peter Y. K. Cheung |
Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Jawad Khan, Balasubramanian Sethuraman, Ranga Vemuri |
A Power-Performance Trade-off Methodology for Portable Reconfigurable Platforms. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Gokul Govindu, Viktor K. Prasanna, Vikash Daga, Sridhar Gangadharpalli, V. Sridhar |
Efficient Floating-point Based Block LU Decomposition on FPGAs. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Toomas P. Plaks (eds.) |
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04, June 21-24, 2004, Las Vegas, Nevada, USA |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Nam Pham Ngoc, Gauthier Lafruit, Jean-Yves Mignolet, Geert Deconinck, Rudy Lauwereins |
QOS Aware HW/SW Partitioning on Run-time Reconfigurable Multimedia Platforms. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Heiko Kalte, Markus Koester, Boris Kettelhoit, Mario Porrmann, Ulrich Rückert 0001 |
A Comparative Study on System Approaches for Partially Reconfigurable Architectures. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Chris Dick, Fred Harris 0001 |
On the Use of FPGAs for OFDM Signal Processing. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Stephan Gatzka, Christian Hochberger |
Distinguished Paper: A New General Model for Adaptive Processors. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Duncan A. Buell, James P. Davis, Gang Quan, Sreesa Akella, Siddhaveerasharan Devarkal, P. Kancharla, Allen Michalski, Heather A. Wake |
Experiences with a Reconfigurable Computer. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Tim Todman, José Gabriel F. Coutinho, Wayne Luk |
Customisable Hardware Compilation. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Jawad Khan, Jayanthi Rajagopalan, Renqiu Huang, Ranga Vemuri |
A Portable Face Recognition System Using Reconfigurable Hardware. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Shinichi Koyama, Tomonori Izumi, Yukihiro Nakamura |
An Adaptive Load Distribution Model and Design on Self-Reconfigurable Logic Device. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Paul M. Heysters, Gerard J. M. Smit, Egbert Molenkamp |
Energy-Efficiency of the MONTIUM Reconfigurable Tile Processor. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
| 1 | Gerard J. M. Smit, Michèl A. J. Rosien, Yuanqing Guo, Paul M. Heysters |
Overview of the Tool-flow for the Montium Processor Tile. |
ERSA |
2004 |
DBLP BibTeX RDF |
|
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