Search results for "EURO-DAC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Alain Greiner, Frédéric Pétrot	Using C to write portable CMOS VLSI module generators.	EURO-DAC	1994	DBLP DOI BibTeX RDF	C
1	Hervé Mathias, Josette Berger-Toussan, Frédéric Gaffiot, L. Hébrard, Gilles Jacquemod, Michel Le Helley	Automatic layout generation for CMOS analog transistors.	EURO-DAC	1994	DBLP BibTeX RDF
1	Krzysztof Bilinski, Erik L. Dagless, Jonathan M. Saul, Marian Adamski	Parallel controller synthesis from a Petri net specification.	EURO-DAC	1994	DBLP BibTeX RDF
1	Reimund Wittmann, Bedrich J. Hosticka, Michael Schanz, Werner Schardein, Stefan Kern, Reinhold Vahrmann	Application-independent hierarchical synthesis methodology for analogue circuits.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Arno Kunzmann	Test pattern generation hardware motivated by pseudo-exhaustive test techniques.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Felix Nicoli, Laurence Pierre	Formal verification of behavioral VHDL specifications: a case study.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Jean-Louis Blanchard, Jean-Michel Morelle	Overall thermal simulation of electronic equipment.	EURO-DAC	1994	DBLP BibTeX RDF
1	Markus Theißinger, Ronald D. Hindmarsh	Layout optimization of planar CMOS cells regarding width-to-height trade-off.	EURO-DAC	1994	DBLP BibTeX RDF
1	Catherine Bayol, Bernard Soulas, Dominique Borrione, Fulvio Corno, Paolo Prinetto	A process algebra interpretation of a verification oriented overlanguage of VHDL.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
1	Alexander Y. Tetelbaum	CAD education and science in Ukraine after Perestroika.	EURO-DAC	1994	DBLP BibTeX RDF
1	Stefan Öing, Werner John	Design support of printed circuit boards concerning radiation and irradiation effects (EMI): using an extended EMC-Workbench.	EURO-DAC	1994	DBLP BibTeX RDF
1	Chris J. Rousse, Alison J. Carter	The use of single and multiple seed architectures with a natural based micro-architecture exploration algorithm.	EURO-DAC	1994	DBLP BibTeX RDF
1	Daniel Clavelier, Bernard Hennion, Christopher Nilson	SYNOPA: an automated synthesizer for CMOS operational amplifiers.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Paolo Prinetto, Fulvio Corno, Matteo Sonza Reorda	An experimental analysis of the effectiveness of the circular self-test path technique.	EURO-DAC	1994	DBLP BibTeX RDF
1	Luc Burgun, N. Dictus, Alain Greiner, E. Prado Lopes, C. Sarwary	Multilevel logic optimization of very high complexity circuits.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Ronald Herrmann, Hergen Pargmann	Computing binary decision diagrams for VHDL data types.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Xun Xiong, Edna Barros, Wolfgang Rosenstiel	A method for partitioning UNITY language in hardware and software.	EURO-DAC	1994	DBLP BibTeX RDF
1	Andrzej Krasniewski, Leszek B. Wronski	Tests for path delay faults vs. tests for gate delay faults: how different they are.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Shashidhar Thakur, D. F. Wong 0001, S. Muthukrishnan 0001	Algorithms for a switch module routing problem.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Smita Bakshi, Daniel D. Gajski	A component selection algorithm for high-performance pipelines.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	A. J. van der Hoeven, K. Olav ten Bosch, Rene van Leuken 0001, Pieter van der Wolf	A flexible access control mechanism for CAD frameworks.	EURO-DAC	1994	DBLP DOI BibTeX RDF	UNIX
1	Edgar Holmann, Ivan R. Linscott, G. Leonard Tyler	Reliability study of combinatorial circuits.	EURO-DAC	1994	DBLP BibTeX RDF
1	Ali Shahid, Muhammad S. T. Benten, Sadiq M. Sait	GSA: scheduling and allocation using genetic algorithm.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Zahir Moosa, Michael Brown, Douglas Edwards	An appreciation of simulated annealing to maze routing.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Werner Rissiek, O. Rethmeier, Heike Holzheuer	Parallel algorithms for the simulation of lossy transmission lines.	EURO-DAC	1994	DBLP BibTeX RDF
1	Christian D. Nielsen	Evaluation of function blocks for asynchronous design.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Félix Moreno, Juan M. Meneses	A new knowledge-based design manager assistant for CAD frameworks.	EURO-DAC	1994	DBLP BibTeX RDF
1	C. Y. Roger Chen, Mohammed Aloqeely	A new technique for exploiting regularity in data path synthesis.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Marc Wendling, Wolfgang Rosenstiel	A hardware environment for prototyping and partitioning based on multiple FPGAs.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Ti-Yen Yen, Wayne H. Wolf, Albert E. Casavant, Alex Ishii	Efficient algorithms for interface timing verification.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Edwin A. Harcourt, Jon Mauney, Todd A. Cook	Formal specification and simulation of instruction-level parallelism.	EURO-DAC	1994	DBLP DOI BibTeX RDF	RISC
1	David B. Bernstein, Werner van Almsick, Wilfried Daehn	Distributed simulation for structural VHDL netlists.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Birger Landwehr, Peter Marwedel, Rainer Dömer	OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Gianpiero Cabodi, Paolo Camurati, Stefano Quer	Symbolic exploration of large circuits with enhanced forward/backward traversals.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Peter Feldmann, Roland W. Freund	Efficient linear circuit analysis by Padé approximation via the Lanczos process.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Winfried Hahn, Andreas Hagerer, C. Herrmann	Compiled-code-based simulation with timing verification.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Peter Luksch 0001	A portable and extendible testbed for distributed logic simulation.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Peter Marwedel, Rainer Leupers	Instruction set extraction from programmable structures.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Kaushik Roy 0001, Sharat Prasad	Logic synthesis for reliability - an early start to controlling electromigration and hot carrier effects.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Jie Gong, Daniel D. Gajski, Alex Nicolau	A performance evaluator for parameterized ASIC architectures.	EURO-DAC	1994	DBLP BibTeX RDF
1	Jindrich Zejda, Eduard Cerny	Gate-level timing verification using waveform narrowing.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Maurizio Valle, Daniele D. Caviglia, Marco Cornero, Giovanni Nateri, Luciano Briozzo	A VHDL-based design methodology: the design experience of a high performance ASIC chip.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Loïc Vandeventer, Jean François Santucci	Algorithms for behavioral test pattern generation from VHDL circuit descriptions containing loop language constructs.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Nick Filer, Michael Brown, Zahir Moosa	Integrating CAD tools into a framework environment using a flexible and adaptable procedural interface.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Bruce K. Holmer	A tool for processor instruction set design.	EURO-DAC	1994	DBLP DOI BibTeX RDF	Prolog
1	Luciano Lavagno, Antonio Lioy, Michael Kishinevsky	Testing redundant asynchronous circuits by variable phase splitting.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Michael Brown, Nick Filer, Zahir Moosa	The use of semantic information for control of a complex routing tool.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Matthias Tröscher, Hans Hartmann, Georg Klein, Andreas Plettner	TRICAP - a three dimensional capacitance solver for arbitrarily shaped conductors on printed circuit boards and VLSI interconnections.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Bill Lin 0001, Chantal Ykman-Couvreur, Peter Vanbekbergen	A general state graph transformation framework for asynchronous synthesis.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Victor V. Denisenko	MOS VLSI circuit simulation by hardware accelerator using semi-natural models.	EURO-DAC	1994	DBLP BibTeX RDF
1	Luis Sánchez Fernández 0001, Peter T. Breuer, Carlos Delgado Kloos	Proof theory and a validation condition generator for VHDL.	EURO-DAC	1994	DBLP BibTeX RDF	Prolog, VHDL
1	Frank Vahid, Daniel D. Gajski, Jie Gong	A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Gert Döhmen	Petri nets as intermediate representation between VHDL and symbolic transition systems.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
1	Chung-Wen Albert Tsao, Andrew B. Kahng	Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	S. Forno, Stephen Rochel	Advanced simulation and modeling techniques for hardware quality verification of digital systems.	EURO-DAC	1994	DBLP BibTeX RDF
1	Klaus Buchenrieder, Christian Veith	A prototyping environment for control-oriented HW/SW systems using state-charts, activity-charts and FPGA's.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Loganath Ramachandran, Daniel D. Gajski, Sanjiv Narayan, Frank Vahid, Peter Fung	100-hour design cycle: a test case.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Karl Fuchs, Michael Pabst, Torsten Rössel	RESIST: a recursive test pattern generation algorithm for path delay faults.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Henrik Esbensen	A macro-cell global router based on two genetic algorithms.	EURO-DAC	1994	DBLP BibTeX RDF
1	Kerry S. Lowe, P. Glenn Gulak	A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Axel Jantsch, Peeter Ellervee, Ahmed Hemani, Johnny Öberg, Hannu Tenhunen	Hardware/software partitioning and minimizing memory interface traffic.	EURO-DAC	1994	DBLP BibTeX RDF	C++, VHDL
1	Matthias Mutz	An automatically verified generalized multifunction arithmetic pipeline.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Rafael Peset Llopis	Exact path sensitization in timing analysis.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Karen Hale	Automotive databus simulation using VHDL.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
1	Salvador Mir, Nick Filer	Re-engineering hardware specifications by exploiting design semantics.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Kevin O'Brien, Serge Maginot	Non-reversible VHDL source-source encryption.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
1	Walling R. Cyre, Jim Armstrong, M. Manek-Honcharik, Alexander J. Honcharik	Generating VHDL models from natural language descriptions.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Stefan Tamme	Rapid prototyping for DSP circuits using high level design tools.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
1	Roman Kuznar, Baldomir Zajc, Franc Brglez	A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Wolfgang Ecker, Manfred Glesner, Andreas Vombach	Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
1	Peter H. Schneider, Kurt Antreich, Ulf Schlichtmann	A new power estimation technique with application to decomposition of Boolean functions for low power.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	A. Both, B. Biermann, R. Lerch, Yiannos Manoli, K. Sievert	Hardware-software-codesign of application specific microcontrollers with the ASM environment.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Sudhakar Muddu, Andrew B. Kahng	Optimal equivalent circuits for interconnect delay calculations using moments.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Ramayya Kumar, Sofiène Tahar	Formal verification of pipeline conflicts in RISC processors.	EURO-DAC	1994	DBLP DOI BibTeX RDF	RISC
1	Wolfgang Müller 0003, Egon Börger, Uwe Glässer	The semantics of behavioral VHDL '93 descriptions.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
1	Rolf Drechsler	BiTeS: a BDD based test pattern generator for strong robust path delay faults.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Peter Gutberlet, Wolfgang Rosenstiel	Timing preserving interface transformations for the synthesis of behavioral VHDL.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Jean Mermet (eds.)	Proceedings EURO-DAC'94, European Design Automation Conference, Grenoble, France, September 19-22, 1994	EURO-DAC	1994	DBLP BibTeX RDF
1	Xinli Gu, Krzysztof Kuchcinski, Zebo Peng	Testability analysis and improvement from VHDL behavioral specifications.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Norbert Wehn, Jörg Biesenack, Peter Duzy, T. Langmaier, Michael Münch, Michael Pilsl, Steffen Rumler	Scheduling of behavioral VHDL by retiming techniques.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Frank Vahid, Daniel D. Gajski, Sanjiv Narayan	A transformation for integrating VHDL behavioral specification with synthesis and software generation.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Krzysztof Bilinski, Erik L. Dagless, Jonathan Saul, Janusz Szajna	An efficient verification algorithm for parallel controllers.	EURO-DAC	1994	DBLP BibTeX RDF
1	Hans Eveking	(V)HDL-based verification of heterogeneous synchronous/asynchronous systems.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Srilata Raman, C. L. Liu 0001, Larry G. Jones	A delay driven FPGA placement algorithm.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	James B. Burr, Allen M. Peterson, Gerard K. Yeh, Kallol Kumar Bagchi	OPERAS in a DSP CAD environment.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Arlet Ottens, Henk Corporaal, Wilco Van Hoogstraeten	A new flexible VHDL simulator.	EURO-DAC	1994	DBLP DOI BibTeX RDF	C++, VHDL
1	E. Griese, J. Schrage, M. Vogt	Fast simulation method for the detection of reflection - and crosstalk effects during the design of complex printed circuit boards.	EURO-DAC	1994	DBLP BibTeX RDF
1	Donatella Sciuto, Stefano Antoniazzi, Alessandro Balboni, William Fornaciari	The role of VHDL within the TOSCA hardware/software codesign framework.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
1	Andrej Magdolen, Jana Bezakova, Elena Gramatová, Mária Fischerová	REGGEN-Test pattern generation on register transfer level.	EURO-DAC	1993	DBLP DOI BibTeX RDF
1	Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Jun Sato, Nobuyuki Hikichi, Masaharu Imai	PEAS-I: A hardware/software co-design system for ASIPs.	EURO-DAC	1993	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis.	EURO-DAC	1993	DBLP DOI BibTeX RDF
1	Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal	Logic systems for path delay test generation.	EURO-DAC	1993	DBLP DOI BibTeX RDF
1	Hazem ElTahawy, Dominique Rodriguez, Serge Garcia Sabiro, Jean-José Mayol	VHDeLDO: A new mixed mode simulation.	EURO-DAC	1993	DBLP DOI BibTeX RDF
1	Gregory Schulte, Peter Tong, Stefan Rusu, Stuart Taylor	TONIC: A timing database for VLSI design.	EURO-DAC	1993	DBLP DOI BibTeX RDF
1	Michael Gasteier, Norbert Wehn, Manfred Glesner	Synthesis of complex VHDL operators.	EURO-DAC	1993	DBLP DOI BibTeX RDF
1	Olav Schettler, Ansgar Bredenfeld	BEPPO: A data model for design representation.	EURO-DAC	1993	DBLP DOI BibTeX RDF
1	Vladimir A. Shepelev, Alexander V. Vlasov	Implementation of the conception of flexible integration within the CADS framework.	EURO-DAC	1993	DBLP DOI BibTeX RDF
1	John Berrie, Andrew Slade	A practical approach to EMC for printed circuit board (PCB) and multichip module (MCM) design.	EURO-DAC	1993	DBLP DOI BibTeX RDF
1	Yu-Liang Wu, Malgorzata Marek-Sadowska	Graph based analysis of FPGA routing.	EURO-DAC	1993	DBLP DOI BibTeX RDF
1	Andrew A. Duncan, David C. Hendry	DSP datapath synthesis eliminating global interconnect.	EURO-DAC	1993	DBLP DOI BibTeX RDF

Publications at "EURO-DAC"( http://dblp.L3S.de/Venues/EURO-DAC )