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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 3186 publication records. Showing 3186 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Linqiao Liu, Stephen Brown |
Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures.  |
FPL  |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Gökhan Akgün, Diana Göhringer |
Power-Aware Real-Time Operating Systems on Reconfigurable Architectures. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Xifan Tang, Ganesh Gore, Grant Brown, Pierre-Emmanuel Gaillardon |
Taping out an FPGA in 24 hours with OpenFPGA: The SOFA Project. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Jens Rettkowski, Diana Göhringer |
Wormhole Computing in Networks-on-Chip. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk |
Demonstrating custom SIMD instruction development for a RISC-V softcore. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jürgen Teich |
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Fritjof Steinert, Justin Knapheide, Benno Stabernack |
Demonstration of a Distributed Accelerator Framework for Energy-efficient ML Processing. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Nathaniel Peura, Yuan Meng, Sanmukh R. Kuppannagari, Viktor K. Prasanna |
FGYM: Toolkit for Benchmarking FPGA based Reinforcement Learning Algorithms. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Philipp S. Käsgen, Mohamed Messelka, Markus Weinhardt |
HiPReP: High-Performance Reconfigurable Processor - Architecture and Compiler. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonas Ney, Dominik Marek Loroch, Vladimir Rybalkin, Nico Weber, Jens Krüger 0004, Norbert Wehn |
HALF: Holistic Auto Machine Learning for FPGAs. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Emmanouil Kavvousanos, Vassilis Paliouras |
Optimizing Deep Learning Decoders for FPGA Implementation. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianyi Cheng, John Wickerson, George A. Constantinides |
Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Minghua Shen, Nong Xiao |
Load Balance-Centric Distributed Parallel Routing for Large-Scale FPGAs. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Ameer M. S. Abdelhadi, He Li 0008 |
Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian Meng, Shreyas Kolala Venkataramanaiah, Chuteng Zhou, Patrick Hansen, Paul N. Whatmough, Jae-sun Seo |
FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeffrey Chen, Sehwan Hong, Warrick He, Jinyeong Moon, Sang-Woo Jun |
Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Cornelia Wulf, Michael Willig, Diana Göhringer |
A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Sathish Panchapakesan, Zhenman Fang, Jian Li 0059 |
SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Duvindu Piyasena, Siew-Kei Lam, Meiqing Wu |
Accelerating Continual Learning on Edge FPGA. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc Perelló Bacardit, Behzad Salami 0001 |
Reduced-voltage OmpSs@FPGA: A Demonstration. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Arzhang Rafii, Welson Sun, Paul Chow |
Pharos: a Multi-FPGA Performance Monitor. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikhil Pratap Ghanathe, Vivek Seshadri, Rahul Sharma 0001, Steve Wilton, Aayan Kumar |
MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunyou Su, Hao Liang, Wei Zhang 0012, Kun Zhao, Baole Ai, Wenting Shen, Zeke Wang |
Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Prajith Ramakrishnan Geethakumari, Ioannis Sourdis |
A Specialized Memory Hierarchy for Stream Aggregation. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Gökhan Akgün, Muhammad Ali 0010, Diana Göhringer |
Power-Aware Computing Systems on FPGAs: A Survey. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Duc-Minh Ngo, Andriy Temko, Colin C. Murphy, Emanuel M. Popovici |
FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoT. |
FPL |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Julien Mazuet, Michel Narozny, Catherine Dezan, Jean-Philippe Diguet |
A Seamless DFT/FFT Self-Adaptive Architecture for Embedded Radar Applications. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Kulkarni 0002, Monica Chiosa, Thomas B. Preußer, Kaan Kara, David Sidler, Gustavo Alonso |
HyperLogLog Sketch Acceleration on FPGA. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuan La, Kaspar Matas, Khoa Dang Pham, Dirk Koch |
Securing FPGA Accelerators at the Electrical Level for Multi-tenant Platforms. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Yaman Umuroglu, Yash Akhauri, Nicholas James Fraser, Michaela Blott |
LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Marie Nguyen, Nathan Serafin, James C. Hoe |
Partial Reconfiguration for Design Optimization. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Nuno Paulino 0001, João Canas Ferreira, João Bispo, João M. P. Cardoso |
Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Arjun Ramaswami, Tobias Kenter, Thomas D. Kühne, Christian Plessl |
Efficient Ab-Initio Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGAs. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Yang, Yunkun Liao, Jianping Shi, Yun Liang 0001, Naifeng Jing, Li Jiang 0002 |
A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Richard Dorrance, Andrey Belogolovy, Hechen Wang, Xue Zhang |
A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Flora Coleman, Behnaz Rezvani, Sachin Sachin, William Diehl |
Side Channel Resistance at a Cost: A Comparison of ARX-Based Authenticated Encryption. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaan Kara, Christoph Hagleitner, Dionysios Diamantopoulos, Dimitris Syrivelis, Gustavo Alonso |
High Bandwidth Memory on FPGAs: A Data Analytics Perspective. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Joseph Melber, James C. Hoe |
A Service-Oriented Memory Architecture for FPGA Computing. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Emre Karabulut, Aydin Aysu |
RANTT: A RISC-V Architecture Extension for the Number Theoretic Transform. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Niansong Zhang, Xiang Chen 0007, Nachiket Kapre |
RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Kristiyan Manev, Dirk Koch |
Resource Elastic Database Acceleration. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Dina G. Mahmoud, Wei Hu 0008, Mirjana Stojilovic |
X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Yanqi Liu, Giuseppe Calderoni, Ruth Iris Bahar |
Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | João Carlos Resende, Ricardo J. R. Maçãs, Ricardo Chaves |
Mask Scrambling Against SCA on Reconfigurable TBOX-Based AES. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos Charalampos Papadopoulos, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Dionisios N. Pnevmatikatos |
A Configurable TLB Hierarchy for the RISC-V Architecture. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaewon Lee, Hanning Chen, Jeffrey S. Young 0001, Hyesoon Kim |
RISC-V FPGA Platform Toward ROS-Based Robotics Application. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Tanner Gaskin, Hayden Cook, Wesley Stirk, Robert Lucas, Jeffrey Goeders, Brad L. Hutchings |
Using Novel Configuration Techniques for Accelerated FPGA Aging. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde |
A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Shashwat Khandelwal, Ziaul Choudhury, Shashwat Shrivastava, Suresh Purini |
Accelerating Local Laplacian Filters on FPGAs. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Guilherme Korol, Michael Guilherme Jordan, Marcelo Brandalero, Michael Hübner 0001, Mateus Beck Rutzig, Antonio Carlos Schneider Beck |
MCEA: A Resource-Aware Multicore CGRA Architecture for the Edge. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Sajjad Rostami Sani, Farheen Fatima Khan, Anas Razzaq, Andy Gean Ye |
Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Kahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton |
Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Gagandeep Singh 0002, Dionysios Diamantopoulos, Christoph Hagleitner, Juan Gómez-Luna, Sander Stuijk, Onur Mutlu, Henk Corporaal |
NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | George Provelengios, Daniel E. Holcomb, Russell Tessier |
Power Wasting Circuits for Cloud FPGA Attacks. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Nikolic 0001, Grace Zgheib, Paolo Ienne |
Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Ryosuke Kuramochi, Hiroki Nakahara |
An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Dionysios Diamantopoulos, Burkhard Ringlein, Mitra Purandare, Gagandeep Singh 0002, Christoph Hagleitner |
Agile Autotuning of a Transprecision Tensor Accelerator Overlay for TVM Compiler Stack. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Gabriella D'Andrea, Luigi Pomante |
Design for ReConfigurability: An Electronic System Level Methodology to Exploit Reconfigurable Platforms. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Naoki Fujieda |
On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAs. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Nele Mentens, Leonel Sousa, Pedro Trancoso, Miquel Pericàs, Ioannis Sourdis (eds.) |
30th International Conference on Field-Programmable Logic and Applications, FPL 2020, Gothenburg, Sweden, August 31 - September 4, 2020 |
FPL |
2020 |
DBLP BibTeX RDF |
|
| 1 | Philippos Papaphilippou, Chris Brooks, Wayne Luk |
An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Farah Abid, Darshana Jayasinghe, Sompasong Somsavaddy, Sri Parameswaran |
LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi 0001, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai |
A High-Performance Out-of-Order Soft Processor Without Register Renaming. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Pierre-Francois Wolfe, Rushi Patel, Robert Munafo, Mayank Varia, Martin C. Herbordt |
Secret Sharing MPC on FPGAs in the Datacenter. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheolyong Bae, Oscar Gustafsson |
High-Speed Chromatic Dispersion Compensation Filtering in FPGAs for Coherent Optical Communication. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Erhan Baturay Onural, Ismail Emir Yuksel, Behzad Salami 0001 |
Demonstrating Reduced-Voltage FPGA-Based Neural Network Acceleration for Power-Efficiency. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Justin Knapheide, Benno Stabernack, Maximilian Kuhnke |
A High Throughput MobileNetV2 FPGA Implementation Based on a Flexible Architecture for Depthwise Separable Convolution. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Linjun Qiao, Guojie Luo, Wentai Zhang 0001, Ming Jiang 0001 |
FPGA Acceleration of Ray-Based Iterative Algorithm for 3D Low-Dose CT Reconstruction. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Abbas Haghi, Lluc Alvarez, Jordà Polo, Dionysios Diamantopoulos, Christoph Hagleitner, Miquel Moretó |
A Hardware/Software Co-Design of K-mer Counting Using a CAPI-Enabled FPGA. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Diederik Adriaan Vink, Aditya Rajagopal, Stylianos I. Venieris, Christos-Savvas Bouganis |
Caffe Barista: Brewing Caffe with FPGAs in the Training Loop. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Ryusuke Nebashi, Naoki Banno, Makoto Miyamura, Xu Bai, Kazunori Funahashi, Koichiro Okamoto, Noriyuki Iguchi, Hideaki Numata, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada |
A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Benjamin Hettwer, Kallyan Das, Sebastien Leger, Stefan Gehrer, Tim Güneysu |
Lightweight Side-Channel Protection using Dynamic Clock Randomization. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Frans Skarman, Oscar Gustafsson, Daniel Jung 0002, Mattias Krysander |
Acceleration of Simulation Models Through Automatic Conversion to FPGA Hardware. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Nick Brown 0002 |
Weighing Up the New Kid on the Block: Impressions of using Vitis for HPC Software Development. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurshaant Malik, Ian Elmor Lang, Rodolfo Pellizzoni, Nachiket Kapre |
Learn the Switches: Evolving FPGA NoCs with Stall-Free and Backpressure Based Routers. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas B. Preußer, Monica Chiosa, Alexander Weiss, Gustavo Alonso |
Using DSP Slices as Content-Addressable Update Queues. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaspar Mätas, Dirk Koch |
Transparent Integration of a Dynamic FPGA Database Acceleration System. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | João Paulo Cardoso de Lima, Marcelo Brandalero, Luigi Carro |
Endurance-Aware RRAM-Based Reconfigurable Architecture using TCAM Arrays. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Duvindu Piyasena, Miyuru Thathsara, Sathursan Kanagarajah, Siew Kei Lam, Meiqing Wu |
Dynamically Growing Neural Network Architecture for Lifelong Deep Learning on the Edge. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Kati Tervo, Samawat Malik, Topi Leppänen, Pekka Jääskeläinen |
TTA-SIMD Soft Core Processors. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Milad Bahadori, Kimmo Järvinen 0001 |
Compact and Programmable yet High-Performance SoC Architecture for Cryptographic Pairings. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Nadesh Ramanathan, George A. Constantinides, John Wickerson |
Precise Pointer Analysis in High-Level Synthesis. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuan La, Kaspar Matas, Joseph Powell, Khoa Dang Pham, Dirk Koch |
Demo: A Closer Look at Malicious Bitstreams. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Jieru Zhao, Tingyuan Liang, Liang Feng 0001, Wenchao Ding 0001, Sharad Sinha, Wei Zhang 0012, Shaojie Shen |
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Shashwat Shrivastava, Ziaul Choudhury, Shashwat Khandelwal, Suresh Purini |
FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Ang Li, Ting-Jung Chang, David Wentzlaff |
Automated Design of FPGAs Facilitated by Cycle-Free Routing. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Dani Maarouf, Ahmed Shamli, Timothy Martin, Gary Gréwal, Shawki Areibi |
A Deep-Learning Framework for Predicting Congestion During FPGA Placement. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Atharva Gondhalekar, Wu-Chun Feng |
Exploring FPGA Optimizations in OpenCL for Breadth-First Search on Sparse Graph Datasets. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Yan 0005, Fatemeh Tehranipoor, Xuan Zhang 0001, John A. Chandy |
FLASH: FPGA Locality-Aware Sensitive Hash for Nearest Neighbor Search and Clustering Application. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Ryan A. Cooke, Suhaib A. Fahmy |
Characterizing Latency Overheads in the Deployment of FPGA Accelerators. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Khoa Dang Pham, Anuj Vaishnav, Joseph Powell, Dirk Koch |
A Self-Compilation Flow Demo on FOS - The FPGA Operating System. |
FPL |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto |
Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. |
FPL |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Wijtvliet, Jos Huisken, Luc Waeijen, Henk Corporaal |
Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency. |
FPL |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Anuj Vaishnav, Khoa Dang Pham, Kristiyan Manev, Dirk Koch |
The FOS (FPGA Operating System) Demo. |
FPL |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Seyedeh Sharareh Mirzargar, Mirjana Stojilovic |
Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey. |
FPL |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Takuya Kojima, Naoki Ando, Yusuke Matsushita 0001, Hideharu Amano |
Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA. |
FPL |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Hale, Brad L. Hutchings |
Preallocating Resources for Distributed Memory Based FPGA Debug. |
FPL |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ioannis Sourdis, Christos-Savvas Bouganis, Carlos Álvarez 0001, Leonel Antonio Toledo Díaz, Pedro Valero-Lara, Xavier Martorell (eds.) |
29th International Conference on Field Programmable Logic and Applications, FPL 2019, Barcelona, Spain, September 8-12, 2019 |
FPL |
2019 |
DBLP BibTeX RDF |
|
| 1 | Rashmi S. Agrawal 0001, Lake Bu, Alan Ehret, Michel A. Kinsy |
Open-Source FPGA Implementation of Post-Quantum Cryptographic Hardware Primitives. |
FPL |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Hadjis, Kunle Olukotun |
TensorFlow to Cloud FPGAs: Tradeoffs for Accelerating Deep Neural Networks. |
FPL |
2019 |
DBLP DOI BibTeX RDF |
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