Search results for "Fan-in"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Hamed F. Dadgour, Kaustav Banerjee	A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
14	Rahul Singh, AhReum Kim, Suhwan Kim	Footer voltage feedforward domino technique for wide fan-in dynamic logic.	SoCC	2010	DBLP DOI BibTeX RDF
14	Jinhui Wang, Na Gong, Wuchen Wu, Ligang Hou	Fan-in sensitive low power dynamic circuits performance statistical characterization.	SoCC	2010	DBLP DOI BibTeX RDF
14	Zohar Shay Karnin, Partha Mukhopadhyay, Amir Shpilka, Ilya Volkovich	Deterministic identity testing of depth-4 multilinear circuits with bounded top fan-in.	STOC	2010	DBLP DOI BibTeX RDF
14	Zohar Shay Karnin, Partha Mukhopadhyay, Amir Shpilka, Ilya Volkovich	Deterministic identity testing of depth 4 multilinear circuits with bounded top fan-in.	Electron. Colloquium Comput. Complex.	2009	DBLP BibTeX RDF
14	Farhad Haj Ali Asgari, Majid Ahmadi, Q. M. Jonathan Wu	Low power high performance keeper technique for high fan-in dynamic gates.	ECCTD	2009	DBLP DOI BibTeX RDF
14	Jingjuan Liao, Zizhen Pang	Surface Parameters Retrieval from Alluvial Fan in Ejina Area of Inner Mongolia using Multi-polarization SAR Data.	IGARSS (3)	2009	DBLP DOI BibTeX RDF
14	Zohar Shay Karnin, Amir Shpilka	Reconstruction of Generalized Depth-3 Arithmetic Circuits with Bounded Top Fan-in.	CCC	2009	DBLP DOI BibTeX RDF
14	Charbel J. Akl, Magdy A. Bayoumi	Single-Phase SP-Domino: A Limited-Switching Dynamic Circuit Technique for Low-Power Wide Fan-in Logic Gates.	IEEE Trans. Circuits Syst. II Express Briefs	2008	DBLP DOI BibTeX RDF
14	Roberto Naldi, Lorenzo Marconi 0001, Andrea Sala	Modelling and control of a miniature ducted-fan in fast forward flight.	ACC	2008	DBLP DOI BibTeX RDF
14	Massimo Alioto, Gaetano Palumbo, Melita Pennisi	Analysis of the impact of process variations on static logic circuits versus fan-in.	ICECS	2008	DBLP DOI BibTeX RDF
14	Danfeng Zhang, Yao Guo 0001, Xiangqun Chen	Automated Aspect Recommendation through Clustering-Based Fan-in Analysis.	ASE	2008	DBLP DOI BibTeX RDF
14	Arkadev Chattopadhyay	Discrepancy and the power of bottom fan-in in depth-three circuits.	Electron. Colloquium Comput. Complex.	2007	DBLP BibTeX RDF
14	Zohar Shay Karnin, Amir Shpilka	Black Box Polynomial Identity Testing of Depth-3 Arithmetic Circuits with Bounded Top Fan-in.	Electron. Colloquium Comput. Complex.	2007	DBLP BibTeX RDF
14	Massimo Alioto, Gaetano Palumbo	Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers.	IEEE Trans. Circuits Syst. II Express Briefs	2007	DBLP DOI BibTeX RDF
14	Walid Ibrahim, Valeriu Beiu	Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming!	ASAP	2007	DBLP DOI BibTeX RDF
14	Marius Marin, Arie van Deursen, Leon Moonen	Identifying Crosscutting Concerns Using Fan-in Analysis	CoRR	2006	DBLP BibTeX RDF
14	Michael J. Franklin, Shawn R. Jeffery, Sailesh Krishnamurthy, Frederick Reiss 0001, Shariq Rizvi, Eugene Wu 0002, Owen Cooper, Anil Edakkunni, Wei Hong 0001	Design Considerations for High Fan-In Systems: The HiFi Approach.	CIDR	2005	DBLP BibTeX RDF
14	Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style.	IEEE Trans. Circuits Syst. I Regul. Pap.	2004	DBLP DOI BibTeX RDF
14	Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou	Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming.	ASP-DAC	2004	DBLP DOI BibTeX RDF
14	Owen Cooper, Anil Edakkunni, Michael J. Franklin, Wei Hong 0001, Shawn R. Jeffery, Sailesh Krishnamurthy, Frederick Reiss 0001, Shariq Rizvi, Eugene Wu 0002	HiFi: A Unified Architecture for High Fan-in Systems.	VLDB	2004	DBLP BibTeX RDF
14	Jan Johannsen	Depth Lower Bounds for Monotone Semi-Unbounded Fan-in Circuits.	RAIRO Theor. Informatics Appl.	2001	DBLP DOI BibTeX RDF
14	Ali Jadbabaie, John Hauser	Control of the Caltech ducted fan in forward flight: a receding horizon-LPV approach.	ACC	2001	DBLP DOI BibTeX RDF
14	Massimo Alioto, Gaetano Palumbo	Optimized design of high fan-in multiplexers using switches with driving capability.	ICECS	2001	DBLP DOI BibTeX RDF
14	Peter Auer, Stephen Kwek, Wolfgang Maass 0001, Manfred K. Warmuth	Learning of Depth Two Neural Networks with Constant Fan-in at the Hidden Nodes	Electron. Colloquium Comput. Complex.	2000	DBLP BibTeX RDF
14	Massimo Alioto, Gaetano Palumbo	Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates.	PATMOS	2000	DBLP BibTeX RDF
14	R. Galindo, Angel Herrera, Juan Carlos Martinez	Methodology on low-order robust controllers. Application to a tandem fan in a platform.	ACC	2000	DBLP DOI BibTeX RDF
14	Rakesh K. Sinha	Simulation of PRAMs with Scan Primitives by Unbounded Fan-In Circuits.	Inf. Process. Lett.	1998	DBLP DOI BibTeX RDF
14	Liming Cai, Jianer Chen, Johan Håstad	Circuit Bottom Fan-In and Computational Power.	SIAM J. Comput.	1998	DBLP DOI BibTeX RDF
14	György Turán, Farrokh Vatan	On the Computation of Boolean Functions by Analog Circuits of Bounded Fan-In.	J. Comput. Syst. Sci.	1997	DBLP DOI BibTeX RDF
14	Hettihe P. Dharmasena, Ramachandran Vaidyanathan	An Optimal Multiple Bus Network for Fan-in Algorithms.	ICPP	1997	DBLP DOI BibTeX RDF
14	Lawrence T. Clark, Gregory F. Taylor	High fan-in circuit design.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
14	Vlado Dancík	Complexity of Boolean Functions Over Bases with Unbounded Fan-In Gates.	Inf. Process. Lett.	1996	DBLP DOI BibTeX RDF
14	Wee Sun Lee, Peter L. Bartlett, Robert C. Williamson	Efficient agnostic learning of neural networks with bounded fan-in.	IEEE Trans. Inf. Theory	1996	DBLP DOI BibTeX RDF
14	Peter Auer, Stephen Kwek, Wolfgang Maass 0001, Manfred K. Warmuth	Learning of Depth Two Neural Networks with Constant Fan-In at the Hidden Nodes (Extended Abstract).	COLT	1996	DBLP DOI BibTeX RDF
14	Ramachandran Vaidyanathan, Anand Padmanabhan	Bus-Based Networks for Fan-In and Uniform Hypercube Algorithms.	Parallel Comput.	1995	DBLP DOI BibTeX RDF
14	Matthias Krause 0001, Stephan Waack	Variation Ranks of Communication Matrices and Lower Bounds for Depth-Two Circuits Having Nearly Symmetric Gates with Unbounded Fan-In.	Math. Syst. Theory	1995	DBLP BibTeX RDF
14	Rolf Niedermeier, Peter Rossmanith	Unambiguous Auxiliary Pushdown Automata and Semi-unbounded Fan-in Circuits	Inf. Comput.	1995	DBLP DOI BibTeX RDF
14	Hisanori Fujisawa, Fumiyo Kawafuji, Tomoyasu Kitaura, Tetsuro Kage	A precise event-driven circuit simulator based on predicted fan-in voltages.	ED&TC	1995	DBLP DOI BibTeX RDF
14	Anna Gál	Semi-Unbounded Fan-In Circuits: Boolean vs. Arithmetic.	SCT	1995	DBLP DOI BibTeX RDF
14	Eric Allender, Ulrich Hertrampf	Depth Reduction for Circuits of Unbounded Fan-In	Inf. Comput.	1994	DBLP DOI BibTeX RDF
14	Ingo Wegener	The Complexity of the Parity Function in Unbounded Fan-In, Unbounded Depth Circuits.	Theor. Comput. Sci.	1991	DBLP DOI BibTeX RDF
14	Cleve Ashcraft, Stanley C. Eisenstat, Joseph W. H. Liu	A Fan-In Algorithm for Distributed Sparse Numerical Factorization.	SIAM J. Sci. Comput.	1990	DBLP DOI BibTeX RDF
14	Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Tuhar Shah	Minimization of multioutput TANT networks for unlimited fan-in network model.	ICCD	1990	DBLP DOI BibTeX RDF
14	Carla Neaderhouser Purdy, George B. Purdy	Integer Division in Linear Time with Bounded Fan-In.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF
14	James F. Lynch	A Depth- Size Tradeoff for Boolean Circuits with Unbounded Fan- In.	SCT	1986	DBLP DOI BibTeX RDF
14	Juraj Hromkovic	Linear Lower Bounds on Unbounded Fan-In Boolean Circuits.	Inf. Process. Lett.	1985	DBLP DOI BibTeX RDF
14	Ashok K. Chandra, Steven Fortune, Richard J. Lipton	Unbounded Fan-In Circuits and Associative Functions.	J. Comput. Syst. Sci.	1985	DBLP DOI BibTeX RDF
14	Ashok K. Chandra, Steven Fortune, Richard J. Lipton	Unbounded Fan-in Circuits and Associative Functions	STOC	1983	DBLP DOI BibTeX RDF
14	Ashok K. Chandra, Larry J. Stockmeyer, Uzi Vishkin	A Complexity Theory for Unbounded Fan-In Parallelism	FOCS	1982	DBLP DOI BibTeX RDF
14	Franco P. Preparata, David E. Muller, Amnon Barak	Reduction of Depth of Boolean Networks with a Fan-In Constraint.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF
14	Amnon Barak	On the Parallel Evaluation of Division-Free Arithmetic Expressions with Fan-In of Three.	Inf. Process. Lett.	1976	DBLP DOI BibTeX RDF
14	K. Chakrabarti, Otto Kolp	Fan-In Constrained Tree Networks of Flexibe Cells.	IEEE Trans. Computers	1974	DBLP DOI BibTeX RDF
14	Donald L. Dietmeyer, Yueh-Hsung Su	Logic Design Automation of Fan-In Limited NAND Networks.	IEEE Trans. Computers	1969	DBLP DOI BibTeX RDF
14	G. L. Hicks, Arthur J. Bernstein	On the minimum stage realization of switching functions using logic gates with limited fan-in	SWCT	1964	DBLP DOI BibTeX RDF
9	Jan Arpe, Bodo Manthey	Approximability of Minimum AND-Circuits.	Algorithmica	2009	DBLP DOI BibTeX RDF	Approximation algorithms, Circuit design, Inapproximability
9	Navendu Jain, Praveen Yalagandula, Michael Dahlin, Yin Zhang	Self-Tuning, Bandwidth-Aware Monitoring for Dynamic Data Streams.	ICDE	2009	DBLP DOI BibTeX RDF
9	Hirotada Kobayashi, François Le Gall, Harumichi Nishimura, Martin Rötteler	General Scheme for Perfect Quantum Network Coding with Free Classical Communication.	ICALP (1)	2009	DBLP DOI BibTeX RDF
9	Vijay Vasudevan, Amar Phanishayee, Hiral Shah, Elie Krevat, David G. Andersen, Gregory R. Ganger, Garth A. Gibson, Brian Mueller	Safe and effective fine-grained TCP retransmissions for datacenter communication.	SIGCOMM	2009	DBLP DOI BibTeX RDF	datacenter networks, incast, performance, throughput
9	Dana Angluin, James Aspnes, Jiang Chen, Lev Reyzin	Learning large-alphabet and analog circuits with value injection queries.	Mach. Learn.	2008	DBLP DOI BibTeX RDF	Value injection queries, Learning circuits, Query learning
9	Hosung Kim, John Lillis	A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
9	Anna Bernasconi 0001, Valentina Ciriani, Rolf Drechsler, Tiziano Villa	Logic Minimization and Testability of 2-SPP Networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
9	Snorre Aunet, Bengt Oelmann, Per Andreas Norseng, Yngvar Berg	Real-Time Reconfigurable Subthreshold CMOS Perceptron.	IEEE Trans. Neural Networks	2008	DBLP DOI BibTeX RDF
9	Zhifang Zhang, Mulan Liu, Yeow Meng Chee, San Ling, Huaxiong Wang	Strongly Multiplicative and 3-Multiplicative Linear Secret Sharing Schemes.	ASIACRYPT	2008	DBLP DOI BibTeX RDF	strongly multiplicative linear secret sharing scheme, secure multi-party computation, monotone span program
9	Vladimir V. Podolskii	A Uniform Lower Bound on Weights of Perceptrons.	CSR	2008	DBLP DOI BibTeX RDF
9	Amir Shpilka, Ilya Volkovich	Read-once polynomial identity testing.	STOC	2008	DBLP DOI BibTeX RDF	bounded depth circuits, identity testing, read-once formulas, reconstruction, arithmetic circuits
9	Dan Gutfreund, Guy N. Rothblum	The Complexity of Local List Decoding.	APPROX-RANDOM	2008	DBLP DOI BibTeX RDF	list-decodable codes, constant-depth circuits, locally-decodable codes
9	Jon Alfredsson, Snorre Aunet	Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply.	PATMOS	2007	DBLP DOI BibTeX RDF
9	Valeriu Beiu, Walid Ibrahim, Sanja Lazarova-Molnar	What von Neumann Did Not Say About Multiplexing Beyond Gate Failures - The Gory Details.	IWANN	2007	DBLP DOI BibTeX RDF
9	Luc Longpré, Pierre McKenzie	The Complexity of Solitaire.	MFCS	2007	DBLP DOI BibTeX RDF
9	Vladimir V. Podolskii	Perceptrons of Large Weight.	CSR	2007	DBLP DOI BibTeX RDF
9	Peiyi Zhao, Jason McNeely, Magdy A. Bayoumi, Pradeep Kumar Golconda, Weidong Kuang	A Low Power Domino with Differential-Controlled-Keeper.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Dana Angluin, James Aspnes, Jiang Chen, Lev Reyzin	Learning Large-Alphabet and Analog Circuits with Value Injection Queries.	COLT	2007	DBLP DOI BibTeX RDF
9	Liliana Cojocaru	Branching Programs, Grammar Systems and the NC1 Class.	SYNASC	2007	DBLP DOI BibTeX RDF
9	Rajesh Vasa, Jean-Guy Schneider, Oscar Nierstrasz	The Inevitable Stability of Software Change.	ICSM	2007	DBLP DOI BibTeX RDF
9	Emanuele Viola	On Approximate Majority and Probabilistic Time.	CCC	2007	DBLP DOI BibTeX RDF
9	Ajay Kumar Verma, Philip Brisk, Paolo Ienne	Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits.	DAC	2007	DBLP DOI BibTeX RDF
9	Hamed F. Dadgour, Kaustav Banerjee	Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications.	DAC	2007	DBLP DOI BibTeX RDF
9	Zhiyu Liu, Volkan Kursun	High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold Voltages.	ISVLSI	2006	DBLP DOI BibTeX RDF
9	Anna Bernasconi 0001, Valentina Ciriani, Rolf Drechsler, Tiziano Villa	Efficient minimization of fully testable 2-SPP networks.	DATE	2006	DBLP DOI BibTeX RDF
9	Arkadev Chattopadhyay, Navin Goyal, Pavel Pudlák, Denis Thérien	Lower bounds for circuits with MOD_m gates.	FOCS	2006	DBLP DOI BibTeX RDF
9	Kazuo Iwama, Hiroki Morizumi	Reductions for Monotone Boolean Circuits.	MFCS	2006	DBLP DOI BibTeX RDF
9	Jeroen A. J. Leijten, Menno Lindwer	Multiprocessing Template for Media Applications.	ISM	2006	DBLP DOI BibTeX RDF
9	Hing-mo Lam, Chi-Ying Tsui	High performance single clock cycle CMOS comparator.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Bo Fu, Paul Ampadu	Techniques for robust energy efficient subthreshold domino CMOS circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang	A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Bahman Kheradmand Boroujeni, Fatemeh Aezinia, Ali Afzali-Kusha	High performance circuit techniques for dynamic OR gates.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Jan Arpe, Bodo Manthey	Approximability of Minimum AND-Circuits.	SWAT	2006	DBLP DOI BibTeX RDF
9	Zhiyu Liu, Volkan Kursun	Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages.	ISQED	2006	DBLP DOI BibTeX RDF	Low Voltage Swing, Gate Oxide Leakage, Domino Logic, Subthreshold Leakage, Dual Threshold Voltage
9	Christoph Behle, Klaus-Jörn Lange	FO[<]-Uniformity.	CCC	2006	DBLP DOI BibTeX RDF
9	Hans Vandierendonck, Koenraad De Bosschere	XOR-Based Hash Functions.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	XOR-based hash function, conflict-free mapping, column space, skewed-associative cache, interbank dispersion, null space
9	Yu Yu, Jussipekka Leiwo, A. Benjamin Premkumar	An Improved Secure Two-Party Computation Protocol.	CISC	2005	DBLP DOI BibTeX RDF
9	Abdelwahab Hamou-Lhadj, Edna Braun, Daniel Amyot, Timothy Lethbridge	Recovering Behavioral Design Models from Execution Traces.	CSMR	2005	DBLP DOI BibTeX RDF
9	Peter R. Pietzuch, Jeffrey Shneidman, Jonathan Ledlie, Matt Welsh, Margo I. Seltzer, Mema Roussopoulos	Evaluating DHT-Based Service Placement for Stream-Based Overlays.	IPTPS	2005	DBLP DOI BibTeX RDF
9	Myint Wai Phyu, Wang Ling Goh, Kiat Seng Yeo	A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
9	Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou	Fast, Parallel Two-Rail Code Checker with Enhanced Testability.	IOLTS	2005	DBLP DOI BibTeX RDF
9	David C. Shepherd, Jeffrey Palm, Lori L. Pollock, Mark Chu-Carroll	Timna: a framework for automatically combining aspect mining analyses.	ASE	2005	DBLP DOI BibTeX RDF	machine learning, reverse engineering, program analysis, aspect mining
9	Amos Beimel, Enav Weinreb	Monotone Circuits for Weighted Threshold Functions.	CCC	2005	DBLP DOI BibTeX RDF
9	Li Ding 0002, Pinaki Mazumder	On circuit techniques to improve noise immunity of CMOS dynamic logic.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
9	Hubie Chen	Arithmetic Constant-Depth Circuit Complexity Classes.	MFCS	2003	DBLP DOI BibTeX RDF