Search results for "GALS"

Hits ?▲	Authors	Title	Venue	Year	Link
20	Tanja Auge, Moritz Hanzig, Andreas Heuer 0001	ProSA Pipeline: Provenance Conquers the Chase.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Joonas Kesäniemi, Mikko Koho, Eero Hyvönen	Using Wikibase for Managing Cultural Heritage Linked Open Data Based on CIDOC CRM.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Emilio M. Sanfilippo, Richard Freedman	Ontology for Analytic Claims in Music.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Witold Litwin	Stored and Inherited Relations with PKN Foreign Keys.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Mariella Bonomo	Knowledge Extraction from Biological and Social Graphs.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Rahul Sharma 0011, Minakshi Kaushik, Sijo Arakkal Peious, Markus Bertl, Ankit Vidyarthi, Ashwani Kumar, Dirk Draheim	Detecting Simpson's Paradox: A Step Towards Fairness in Machine Learning.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Meriem Kherbouche, Yossra Zghal, Bálint Molnár, András Benczúr	The Use of M2P in Business Process Improvement and Optimization.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Foutse Yuehgoh, Sonia Djebali, Nicolas Travers	A Multiplex Network Framework Based Recommendation Systems for Technology Intelligence.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Sara Taki, Cédric Eichler, Benjamin Nguyen	It's Too Noisy in Here: Using Projection to Improve Differential Privacy on RDF Graphs.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Erica Faggiani, Stefano Faralli 0001, Paola Velardi	Neural Word Sense Disambiguation to Prune a Large Knowledge Graph of the Italian Cultural Heritage.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Chiara Bachechi	Digital Twins for Urban Mobility.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Wadie Skaf, Tomás Horváth	Denoising Architecture for Unsupervised Anomaly Detection in Time-Series.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Luana Bulla, Maria Chiara Frangipane, Maria Letizia Mancinelli, Ludovica Marinucci, Misael Mongiovì, Margherita Porena, Valentina Presutti, Chiara Veninata	Developing and Aligning a Detailed Controlled Vocabulary for Artwork.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Simone Monaco, Daniele Apiletti	Experimental Comparison of Theory-Guided Deep Learning Algorithms.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Antônio Diogo Forte Martins, José Maria Monteiro, Javam C. Machado	Understanding Misinformation About COVID-19 in WhatsApp Messages.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Théo Abgrall	Formalization of Data Integration Transformations.	ADBIS (Short Papers)	2022	DBLP DOI BibTeX RDF
20	Davide Bertozzi, Gabriele Miorandi, Alberto Ghiribaldi, Wayne P. Burleson, Greg Sadowski, Kshitij Bhardwaj, Weiwei Jiang 0002, Steven M. Nowick	Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems.	IEEE Micro	2021	DBLP DOI BibTeX RDF
20	Iaçanã I. Weber, Leonardo Londero de Oliveira, Everton Carara, Fernando Gehm Moraes	Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication.	SBCCI	2020	DBLP DOI BibTeX RDF
20	Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee	A GALS design based on multi-frequency clocking for digital switching noise reduction.	Integr.	2019	DBLP DOI BibTeX RDF
20	Zoya Dyka, Ievgen Kabin, Dan Klann, Frank Vater, Peter Langendörfer	Caution: GALS-ification as a Means against SCA Attacks.	EWDTS	2019	DBLP DOI BibTeX RDF
20	Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany	A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET.	ASYNC	2019	DBLP DOI BibTeX RDF
20	João Almeida, Filipe Moutinho, Rogério Campos-Rebelo	Asynchronous Interfaces for IOPT-Flow to Support GALS Systems.	IECON	2019	DBLP DOI BibTeX RDF
20	Lina Marsso, Radu Mateescu 0001, Ioannis Parissis, Wendelin Serwe	Asynchronous Testing of Synchronous Components in GALS Systems.	IFM	2019	DBLP DOI BibTeX RDF
20	Weiyi Zhang 0003, Zoran Salcic, Avinash Malik	Towards Formal Modeling and Analysis of SystemJ GALS Systems using Coloured Petri Nets.	INDIN	2019	DBLP DOI BibTeX RDF
20	Seyed Mohamad Taghi Adl, Siamak Mohammadi	A high performance dual clock elastic FIFO network interface for GALS NoC.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
20	A. Karthikeyan, P. Senthil Kumar 0005	GALS implementation of randomly prioritized buffer-less routing architecture for 3D NoC.	Clust. Comput.	2018	DBLP DOI BibTeX RDF
20	Francesco Barchi, Gianvito Urgese, Andrea Acquaviva, Enrico Macii	Directed Graph Placement for SNN Simulation into a multi-core GALS Architecture.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
20	Martin Perner, Ulrich Schmid 0001	Self-Stabilizing High-Speed Communication in Multi-Synchronous GALS Architectures.	IOLTS	2018	DBLP DOI BibTeX RDF
20	Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee	A GALS Design with Opposite-Phase Local Clock Assignment for Power Supply Noise Reduction.	APCCAS	2018	DBLP DOI BibTeX RDF
20	Frank P. Burns, Danil Sokolov, Alex Yakovlev	A Structured Visual Approach to GALS Modeling and Verification of Communication Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
20	Patrick Russell, Jens Döge, Christoph Hoppe, Thomas B. Preußer, Peter Reichel, Peter Schneider	Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC.	DDECS	2017	DBLP DOI BibTeX RDF
20	Milan Babic, Milos Krstic	A substrate noise reduction methodology based on power domain separation of GALS subcomponents.	PATMOS	2017	DBLP DOI BibTeX RDF
20	Johannes Ax, Nils Kucza, Marten Vohrmann, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert 0001	Comparing Synchronous, Mesochronous and Asynchronous NoCs for GALS Based MPSoCs.	MCSoC	2017	DBLP DOI BibTeX RDF
20	Milos Krstic, Eckhard Grass, Xin Fan 0003	Asynchronous and GALS Design -Overview and Perspectives.	NGCAS	2017	DBLP DOI BibTeX RDF
20	Davide Bertozzi, Gabriele Miorandi, Mahdi Tala, Steven M. Nowick	Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Networks-on-Chip.	NGCAS	2017	DBLP DOI BibTeX RDF
20	Evangelia Kasapaki, Martin Schoeberl, Rasmus Bo Sørensen, Christoph Thomas Muller, Kees Goossens, Jens Sparsø	Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
20	HeeJong Park 0001, Zhenmin Li, Avinash Malik, Zoran A. Salcic	Times Square - Marriage of Real-Time and Logical-Time in GALS and Synchronous Languages.	J. Signal Process. Syst.	2016	DBLP DOI BibTeX RDF
20	Fatma Jebali, Frédéric Lang, Radu Mateescu 0001	Formal modelling and verification of GALS systems using GRL and CADP.	Formal Aspects Comput.	2016	DBLP DOI BibTeX RDF
20	Divya Akella Kamakshi, Matthew Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, Benton H. Calhoun	Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks.	ASYNC	2016	DBLP DOI BibTeX RDF
20	Milan Babic, Steffen Zeidler 0001, Milos Krstic	GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits.	ASYNC	2016	DBLP DOI BibTeX RDF
20	Eduardo Lussari, Duarte Lopes de Oliveira, Lester de Abreu Faria, Orlando Verducci Jr.	Software-Defined Radio design based on GALS architecture for FPGAs.	SBCCI	2016	DBLP DOI BibTeX RDF
20	Waqas Gul, Syed Rafay Hasan, Osman Hasan, Faiq Khalid Lodhi, Falah R. Awwad	Synchronously triggered GALS design templates leveraging QDI asynchronous interfaces.	ISCAS	2016	DBLP DOI BibTeX RDF
20	Johnson Fernandes, Maciej Koutny, Lukasz Mikulski, Marta Pietkiewicz-Koutny, Danil Sokolov, Alex Yakovlev	Persistent and Nonviolent Steps and the Design of GALS Systems.	Fundam. Informaticae	2015	DBLP DOI BibTeX RDF
20	Kazem Cheshmi, Siamak Mohammadi, Daniel Versick, Djamshid Tavangarian, Jelena Trajkovic	A Clustered GALS NoC Architecture with Communication-Aware Mapping.	PDP	2015	DBLP DOI BibTeX RDF
20	Milan Babic, Xin Fan 0003, Milos Krstic	Frequency-domain modeling of ground bounce and substrate noise for synchronous and GALS systems.	PATMOS	2015	DBLP DOI BibTeX RDF
20	Frank P. Burns, Danil Sokolov, Alexandre Yakovlev	GALS synthesis and verification for xMAS models.	DATE	2015	DBLP BibTeX RDF
20	Ben Keller, Matthew Fojtik, Brucek Khailany	A Pausible Bisynchronous FIFO for GALS Systems.	ASYNC	2015	DBLP DOI BibTeX RDF
20	Evangelia Kasapaki, Jens Sparsø	The Argo NOC: Combining TDM and GALS.	ECCTD	2015	DBLP DOI BibTeX RDF
20	Andrew Nelson 0001, Kees Goossens	Distributed power management of real-time applications on a GALS multiprocessor SOC.	EMSOFT	2015	DBLP DOI BibTeX RDF
20	Sean James Salisbury	Gals NoC.		2015	RDF
20	Ivan Miro Panades, Edith Beigné, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Anca Molnos, Farhat Thabet, Benoît Tain, Karim Ben Chehida, Sylvain Engels, Robin Wilson, Didier Fuin	A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
20	Filipe Moutinho, Luís Gomes 0001	Asynchronous-Channels Within Petri Net-Based GALS Distributed Embedded Systems Modeling.	IEEE Trans. Ind. Informatics	2014	DBLP DOI BibTeX RDF
20	Mohammad H. Foroozannejad, Matin Hashemi, Alireza Mahini, Bevan M. Baas, Soheil Ghiasi	Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
20	Robert Najvirt, Andreas Steininger	Equivalence of clock gating and synchronization with applicability to GALS communication.	PATMOS	2014	DBLP DOI BibTeX RDF
20	Xin Fan 0003, Steffen Peter, Milos Krstic	GALS design of ECC against side-channel attacks - A comparative study.	PATMOS	2014	DBLP DOI BibTeX RDF
20	Danil Sokolov, Alex Yakovlev	GALS Partitioning by Behavioural Decoupling Expressed in Petri Nets.	ASYNC	2014	DBLP DOI BibTeX RDF
20	Luciano Loder, Adão Antônio de Souza Jr., Marcelo Schiavon Fay, Rafael Soares	Towards a Framework to Perform DPA Attack on GALS Pipeline Architectures.	SBCCI	2014	DBLP DOI BibTeX RDF
20	Wei-Tsun Sun, Zoran A. Salcic, Alain Girault, Avinash Malik	libDGALS: A library-based approach to design dynamic GALS systems.	SIES	2014	DBLP DOI BibTeX RDF
20	HeeJong Park 0001, Avinash Malik, Zoran A. Salcic	Times square - marriage of real-time and logical-time in GALS and synchronous languages.	RTCSA	2014	DBLP DOI BibTeX RDF
20	Hirokatsu Shirahama, Akira Mochizuki, Yuma Watanabe, Takahiro Hanyu	Energy-aware current-mode inter-chip link for a dependable GALS NoC platform.	ISCAS	2014	DBLP DOI BibTeX RDF
20	Pooria M. Yaghini, Ashkan Eghbal, Nader Bagherzadeh	A GALS Router for Asynchronous Network-on-Chip.	MES	2014	DBLP DOI BibTeX RDF
20	Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang	Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips.	APCCAS	2014	DBLP DOI BibTeX RDF
20	Xin Fan	GALS design methodology based on pausible clocking. (PDF / PS)		2014	RDF
20	Marco Cannizzaro	Robust and efficient globally-asynchronous locally-synchronous GALS digital design.		2014	RDF
20	Sebastian Höppner, Holger Eisenreich, Stephan Henker, Dennis Walter, Georg Ellguth, René Schüffny	A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
20	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels.	J. Comput. Syst. Sci.	2013	DBLP DOI BibTeX RDF
20	Aminollah Mahabadi, S. M. Zahedi, Ahmad Khonsari	Reliable energy-aware application mapping and voltage-frequency island partitioning for GALS-based NoC.	J. Comput. Syst. Sci.	2013	DBLP DOI BibTeX RDF
20	Zoran Salcic, Avinash Malik	GALS-HMP: A heterogeneous multiprocessor for embedded applications.	ACM Trans. Embed. Comput. Syst.	2013	DBLP DOI BibTeX RDF
20	Johnson Fernandes, Maciej Koutny, Marta Pietkiewicz-Koutny, Danil Sokolov, Alex Yakovlev	Step Persistence in the Design of GALS Systems.	Petri Nets	2013	DBLP DOI BibTeX RDF
20	Alex Yakovlev, Pascal Vivet, Marc Renaudin	Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools.	DATE	2013	DBLP DOI BibTeX RDF
20	Alberto Ghiribaldi, Davide Bertozzi, Steven M. Nowick	A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems.	DATE	2013	DBLP DOI BibTeX RDF
20	Xin Fan 0003, Oliver Schrape, Miroslav Marinkovic, Peter Dahnert, Milos Krstic, Eckhard Grass	GALS Design for Spectral Peak Attenuation of Switching Current.	ASYNC	2013	DBLP DOI BibTeX RDF
20	Jakob Lechner, Varadan Savulimedu Veeravalli	Modular Redundancy in a GALS System Using Asynchronous Recovery Links.	ASYNC	2013	DBLP DOI BibTeX RDF
20	Mohammad H. Foroozannejad, Brent Bohnenstiehl, Soheil Ghiasi	BAMSE: A balanced mapping space exploration algorithm for GALS-based manycore platforms.	ASP-DAC	2013	DBLP DOI BibTeX RDF
20	Sylvain Durand, Suzanne Lesecq, Edith Beigné, Diego Puschini	Event-based DVFS control in GALS-ANoC MPSoCs.	ACC	2013	DBLP DOI BibTeX RDF
20	Edith Beigné, Ivan Miro-Panades, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Farhat Thabet, Benoît Tain, K. Benchehida, Sylvain Engels, Robin Wilson, Didier Fuin	A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC.	ESSCIRC	2013	DBLP DOI BibTeX RDF
20	Neeraj Pradhan, Roopak Dubey, K. Madhava Krishna, Shubhajit Roy Chowdhury	Low Power Two-Tier GALS Architecture for Multi Robot Collision Avoidance.	AIR	2013	DBLP DOI BibTeX RDF
20	Kazem Cheshmi, Mohammadreza Soltaniyeh, Siamak Mohammadi, Jelena Trajkovic	Quota setting router architecture for quality of service in GALS NoC.	RSP	2013	DBLP DOI BibTeX RDF
20	Jude Angelo Ambrose, Isuru Nawinne, Sri Parameswaran	Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs.	ISCAS	2013	DBLP DOI BibTeX RDF
20	Anita Tino, Gul N. Khan, Fei Yuan 0005	Hardware realization of GALS based cortical column systems.	AHS	2013	DBLP DOI BibTeX RDF
20	Filipe Moutinho, Luís Gomes 0001	Augmenting High-Level Petri Nets to Support GALS Distributed Embedded Systems Specification.	DoCEIS	2013	DBLP DOI BibTeX RDF
20	Kwen-Siong Chong, Kok-Leong Chang, Bah-Hwee Gwee, Joseph S. Chang	Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
20	Milos Krstic, Xin Fan 0003, Eckhard Grass, Luca Benini, Mohammad Reza Kakoee, Christoph Heer, Birgit Sanders, Alessandro Strano, Davide Bertozzi	Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience.	Int. J. Embed. Real Time Commun. Syst.	2012	DBLP DOI BibTeX RDF
20	Avinash Malik, Alain Girault, Zoran Salcic	Formal Semantics, Compilation and Execution of the GALS Programming Language DSystemJ.	IEEE Trans. Parallel Distributed Syst.	2012	DBLP DOI BibTeX RDF
20	Carles Hernández 0001, Antoni Roca 0001, Federico Silla, José Flich, José Duato	On the Impact of Within-Die Process Variation in GALS-Based NoC Performance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2012	DBLP DOI BibTeX RDF
20	Hala A. Farouk, Mahmoud T. El-Hadidi, Ahmed A. El Farag	GALS-based LPSP: Performance Analysis of a Novel Architecture for Low Power High Performance Security Processors.	Int. J. Netw. Comput.	2012	DBLP BibTeX RDF
20	Xin Fan 0003, Milos Krstic, Eckhard Grass, Birgit Sanders, Christoph Heer	Exploring pausible clocking based GALS design for 40-nm system integration.	DATE	2012	DBLP DOI BibTeX RDF
20	Xin Fan 0003, Milos Krstic, Eckhard Grass	Performance Analysis of GALS Datalink Based on Pausible Clocking.	ASYNC	2012	DBLP DOI BibTeX RDF
20	Manoj Kumar Yadav, Mario R. Casu, Maurizio Zamboni	DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems.	ASYNC	2012	DBLP DOI BibTeX RDF
20	Muhammad Nadeem, Morteza Biglari-Abhari, Zoran Salcic	JOP-plus - A processor for efficient execution of java programs extended with GALS concurrency.	ASP-DAC	2012	DBLP DOI BibTeX RDF
20	Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, Ulf Schlichtmann	Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
20	Filipe Moutinho, Luís Gomes 0001, Anikó Costa, José Pimenta	Asynchronous wrappers configuration within GALS systems specified by Petri nets.	ISIE	2012	DBLP DOI BibTeX RDF
20	Jakob Lechner	Designing Robust GALS Circuits with Triple Modular Redundancy.	EDCC	2012	DBLP DOI BibTeX RDF
20	Thorsten Jungeblut, Johannes Ax, Mario Porrmann, Ulrich Rückert 0001	A TCMS-based architecture for GALS NoCs.	ISCAS	2012	DBLP DOI BibTeX RDF
20	Debora Matos, Cezar Reinbrecht, Gianluca Palermo, Jonathan Martinelli, Altamiro Amadeu Susin, Cristina Silvano, Luigi Carro	Floorplan-aware hierarchical NoC topology with GALS interfaces.	ISCAS	2012	DBLP DOI BibTeX RDF
20	Filipe Moutinho, Luís Gomes 0001	Asynchronous-Channels and Time-Domains Extending Petri Nets for GALS Systems.	DoCEIS	2012	DBLP DOI BibTeX RDF
20	Jean-Michel Chabloz, Ahmed Hemani	Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links.	VLSI Design	2012	DBLP DOI BibTeX RDF
20	Dongkun Shin, Woojoong Kim, Soontae Kwon, Tae Hee Han	Communication-aware VFI partitioning for GALS-based networks-on-chip.	Des. Autom. Embed. Syst.	2011	DBLP DOI BibTeX RDF
20	Alessandro Strano, Carles Hernández 0001, Federico Silla, Davide Bertozzi	Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design.	Int. J. Embed. Real Time Commun. Syst.	2011	DBLP DOI BibTeX RDF
20	Michael N. Horak, Steven M. Nowick, Matthew Carlberg, Uzi Vishkin	A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF