Search results for "NANOARCH"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Peng Ouyang, Shouyi Yin, Chunxiao Xing, Leibo Liu, Shaojun Wei	Energy management on DVS based coarse-grained reconfigurable platform.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Bo Yang, Emanuel M. Popovici, Michael Alan Quille, Andreas Amann, Sorin Cotofana	A supply voltage-dependent variation aware reliability evaluation model.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Mahyar Shahsavari, Pierre Falez, Pierre Boulet	Combining a volatile and nonvolatile memristor in artificial synapse to improve learning in Spiking Neural Networks.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Qian Shi, Zhaohao Wang, Yuqian Gao, Liang Chang 0002, Wang Kang 0001, Youguang Zhang, Weisheng Zhao	A spin Hall effect-based multi-level cell for MRAM.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	He Zhang 0011, Wang Kang 0001, Tingting Pang, Weifeng Lv, Youguang Zhang, Weisheng Zhao	Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	You Wang 0002, Hao Cai, Lirida A. B. Naviner, Jacques-Olivier Klein, Jianlei Yang 0001, Weisheng Zhao	A novel circuit design of true random number generator using magnetic tunnel junction.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Hoang Anh Du Nguyen, Lei Xie 0005, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels	Synthesizing HDL to memristor technology: A generic framework.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Yingyezhe Jin, Yu Liu 0028, Peng Li 0001	SSO-LSM: A Sparse and Self-Organizing architecture for Liquid State Machine based neural processors.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Meshal Alawein, Hossein Fariborzi	Improved circuit model for all-spin logic.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Leibin Ni, Hantao Huang, Hao Yu 0001	A memristor network with coupled oscillator and crossbar towards L2-norm based machine learning.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Fengyu Qian, Yanping Gong, Guoxian Huang, Kiarash Ahi, Mehdi Anwar, Lei Wang 0003	A memristor-based compressive sensing architecture.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Eleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarù, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon, Giovanni De Micheli	Inversion optimization in Majority-Inverter Graphs.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Xiaoyang Wang 0006, Chao Zhang 0007, Xian Zhang 0001, Guangyu Sun 0003	np-ECC: Nonadjacent position error correction code for racetrack memory.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Jiajun Shi, Mingyu Li, Santosh Khasanvis, Mostafizur Rahman, Csaba Andras Moritz	Routability in 3D IC design: Monolithic 3D vs. Skybridge 3D CMOS.	NANOARCH	2016	DBLP DOI BibTeX RDF
1		Mosaic: A scheme of mapping non-volatile Boolean logic on memristor crossbar.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Weiqi Zhang, Chao Zhang 0007, Guangyu Sun 0003	Accelerate context switch by racetrack-SRAM hybrid cells.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Laurie E. Calvet, Joseph S. Friedman, Damien Querlioz, Pierre Bessière, Jacques Droulez	Sleep stage classification with stochastic Bayesian inference.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Soroush Khaleghi, Paolo Vinella, Soumya Banerjee 0004, Wenjing Rao	An STT-MRAM based strong PUF.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Deming Zhang, Lang Zeng, Youguang Zhang, Weisheng Zhao, Jacques-Olivier Klein	Stochastic spintronic device based synapses and spiking neurons for neuromorphic computation.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Hsin-Pai Cheng, Wei Wen, Chang Song 0001, Beiye Liu, Hai Li 0001, Yiran Chen 0001	Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Linbin Chen, Fabrizio Lombardi, Jie Han 0001, Weiqiang Liu 0001	A fully parallel approximate CORDIC design.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Alexandre Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau, Jean-Michel Portal	Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures.	NANOARCH	2016	DBLP DOI BibTeX RDF
1		MECRO: A local processing computer architecture based on memristor crossbar.	NANOARCH	2016	DBLP DOI BibTeX RDF
1	Honglan Jiang, Cong Liu 0015, Naman Maheshwari, Fabrizio Lombardi, Jie Han 0001	A comparative evaluation of approximate multipliers.	NANOARCH	2016	DBLP DOI BibTeX RDF
1		IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016, Beijing, China, July 18-20, 2016	NANOARCH	2016	DBLP BibTeX RDF
1	Erya Deng, You Wang 0002, Zhaohao Wang, Jacques-Olivier Klein, Bernard Dieny, Guillaume Prenat, Weisheng Zhao	Robust magnetic full-adder with voltage sensing 2T/2MTJ cell.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Erik P. DeBenedictis, Jeanine E. Cook, Mark Hoemmen, Tzevetan S. Metodi	Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (OAS+PIMS).	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Zhixi Yang, Jie Han 0001, Fabrizio Lombardi	Transmission gate-based approximate adders for inexact computing.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Colin Pardue, Madhavan Swaminathan, John Bosco Balaguru	Lossy frequency selective surfaces for gas sensing using ZnO films.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Walt Woods, Mohammad Mahmoud A. Taha, S. J. Dat Tran, Jens Bürger 0002, Christof Teuscher	Memristor panic - A survey of different device models in crossbar architectures.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Melika Payvand, Luke Theogarajan	Exploiting local connectivity of CMOL architecture for highly parallel orientation selective neuromorphic chips.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Lei Xie 0005, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels	Interconnect networks for memristor crossbar.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Christopher H. Bennett, Djaafar Chabi, Theo Cabaret, Bruno Jousselme, Vincent Derycke, Damien Querlioz, Jacques-Olivier Klein	Supervised learning with organic memristor devices and prospects for neural crossbar arrays.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Hoang Anh Du Nguyen, Lei Xie 0005, Mottaqiallah Taouil, Razvan Nane, Said Hamdioui, Koen Bertels	Computation-in-memory based parallel adder.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Aaron Germuth, Alex Aravind	From kekule cells to molecular switches.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Santosh Khasanvis, Mingyu Li, Mostafizur Rahman, Mohammad Salehi Fashami, Ayan Kumar Biswas, Jayasimha Atulasimha, Supriyo Bandyopadhyay, Csaba Andras Moritz	Physically equivalent magneto-electric nanoarchitecture for probabilistic reasoning.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Ke Chen 0018, Fabrizio Lombardi, Jie Han 0001	Matrix multiplication by an inexact systolic array.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Patrick Sheridan, Wei D. Lu	Defect consideratons for robust sparse coding using memristor arrays.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Mohsen Imani, Shruti Patil, Tajana Simunic Rosing	Hierarchical design of robust and low data dependent FinFET based SRAM array.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Miguel Angel Lastras-Montaño, Amirali Ghofrani, Kwang-Ting Cheng	Architecting energy efficient crossbar-based memristive random-access memories.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Mohammad Mahmoud A. Taha, Wim J. C. Melis	Analogue auto-associative memory using a multi-valued memristive memory cell.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Peyman Pouyan, Esteve Amat, Antonio Rubio 0001	Analysis and design of an adaptive proactive reconfiguration approach for memristive crossbar memories.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Shaloo Rakheja	Fundamental limits of energy dissipation in spintronic interconnects using optical spin pumping.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Ali Alsuwaiyan, Kartik Mohanram	MFNW: A Flip-N-Write architecture for multi-level cell non-volatile memories.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Azam Seyedi, Vasileios Karakostas, Stefan Cosemans, Adrián Cristal, Mario Nemirovsky, Osman S. Unsal	NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Winston Haaswijk, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli	NEM relay design with biconditional binary decision diagrams.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Joseph S. Friedman, Damien Querlioz, Alan V. Sahakian	Magnetoresistance implications for complementary magnetic tunnel junction logic (CMAT).	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis	Fast march tests for defects in resistive memory.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Jiajun Shi, Mingyu Li, Mostafizur Rahman, Santosh Khasanvis, Csaba Andras Moritz	Architecting NP-Dynamic Skybridge.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Elham Zamanidoost, Michael Klachko, Dmitri B. Strukov, Irina Kataeva	Low area overhead in-situ training approach for memristor-based classifier.	NANOARCH	2015	DBLP DOI BibTeX RDF
1		Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015, Boston, MA, USA, July 8-10, 2015	NANOARCH	2015	DBLP BibTeX RDF
1	Raqibul Hasan, Chris Yakopcic, Tarek M. Taha	Ex-situ training of dense memristor crossbar for neuromorphic applications.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Pablo Royer, Fernando García-Redondo, Marisa López-Vallejo	Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Bi Wu, Yuanqing Cheng, Ying Wang 0001, Aida Todri-Sanial, Guangyu Sun 0003, Lionel Torres, Weisheng Zhao	An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Onur Tunali, Mustafa Alton	Defect tolerance in diode, FET, and four-terminal switch based nano-crossbar arrays.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Yasunao Katayama, Toshiyuki Yamane, Daiju Nakano, Ryosho Nakane, Gouhei Tanaka	Wave-based device scaling concept for brain-like energy efficiency and integration.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Daniele Garbin, Elisa Vianello, Olivier Bichler, M. Azzaz, Quentin Rafhay, Philippe Candelier, Christian Gamrat, Gérard Ghibaudo, Barbara De Salvo, Luca Perniola	On the impact of OxRAM-based synapses variability on convolutional neural networks performance.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Santosh Khasanvis, Mostafizur Rahman, Mingyu Li, Jiajun Shi, Csaba Andras Moritz	Architecting connectivity for fine-grained 3-D vertically integrated circuits.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Jens Bürger 0002, Alireza Goudarzi, Darko Stefanovic, Christof Teuscher	Hierarchical composition of memristive networks for real-time computing.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu	A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Alvaro Velasquez, Sumit Kumar Jha 0001	Automated synthesis of crossbars for nanoscale computing using formal methods.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Qi An, Li Su, Jacques-Olivier Klein, Sébastien Le Beux, Ian O'Connor, Weisheng Zhao	Full-adder circuit design based on all-spin logic device.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Mostafizur Rahman, Santosh Khasanvis, Jiajun Shi, Mingyu Li, Csaba Andras Moritz	Architecting 3-D integrated circuit fabric with intrinsic thermal management features.	NANOARCH	2015	DBLP DOI BibTeX RDF
1	Sumit Dutta, Vladimir Stojanovic	Floating-point unit design with nano-electro-mechanical (NEM) relays.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Santosh Khasanvis, Mostafizur Rahman, Sankara Narayanan Rajapandian, Csaba Andras Moritz	Wave-based multi-valued computation framework.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Catherine Dezan, Sara Zermani	Stochastic reliability evaluation of Sea-of-Tiles based on Double Gate controllable-polarity FETs.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Alexander N. Tait, Paul R. Prucnal	Applications of wavelength-fan-in for high-performance distributed processing systems.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Pilin Junsangsri, Fabrizio Lombardi, Jie Han 0001	A memristor-based TCAM (Ternary Content Addressable Memory) cell.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Odysseas Zografos, Praveen Raghavan, Luca Gaetano Amarù, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Diederik Verkest, Aaron Thean	System-level assessment and area evaluation of Spin Wave logic circuits.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Mostafizur Rahman, Mingyu Li, Jiajun Shi, Santosh Khasanvis, Csaba Andras Moritz	A new Tunnel-FET based RAM concept for ultra-low power applications.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Jana Tittmann, Sascha Hermann, Stefan E. Schulz, Anibal Pacheco-Sanchez, Martin Claus, Michael Schröter	Hysteresis-free carbon nanotube field-effect transistors without passivation.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Ali Zahir, Syed Azhar Ali Zaidi, Azzurra Pulimeno, Mariagrazia Graziano, Danilo Demarchi, Guido Masera, Gianluca Piccinini	Molecular transistor circuits: From device model to circuit simulation.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	David Roclin, Olivier Bichler, Christian Gamrat, Jacques-Olivier Klein	Sneak paths effects in CBRAM memristive devices arrays for spiking neural networks.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Mihai Lefter, Marius Enachescu, George Razvan Voicu, Sorin Dan Cotofana	Energy effective 3D stacked hybrid NEMFET-CMOS caches.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Djaafar Chabi, Zhaohao Wang, Weisheng Zhao, Jacques-Olivier Klein	On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Alireza Goudarzi, Matthew R. Lakin, Darko Stefanovic, Christof Teuscher	A model for variation- and fault-tolerant digital logic using self-assembled nanowire architectures.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Walt Woods, Jens Bürger 0002, Christof Teuscher	On the influence of synaptic weight states in a locally competitive algorithm for memristive hardware.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Davide Giri, Marco Vacca, Giovanni Causapruno, Wenjing Rao, Mariagrazia Graziano, Maurizio Zamboni	A standard cell approach for MagnetoElastic NML circuits.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Mehdi Kabir, Stuart A. Wolf, Jiwei Lu	Spin torque nano oscillators as key building blocks for the Systems-on-Chip of the future.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu	Analog-to-stochastic converter using magnetic-tunnel junction devices.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Jinghua Yang, Niranjan Kulkarni, Shimeng Yu, Sarma B. K. Vrudhula	Integration of threshold logic gates with RRAM devices for energy efficient and robust operation.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Ravi Patel 0001, Eby G. Friedman	Sub-crosspoint RRAM decoding for improved area efficiency.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	David Colliaux, Pierre Bessière, Jacques Droulez	Robust sequence storage in bistable oscillators.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Nesrine Ben Romdhane, Weisheng Zhao, Yue Zhang 0010, Jacques-Olivier Klein, Z. R. Wang, Dafine Ravelosona	Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Ciprian Teodorov, Loïc Lagadec	Virtual prototyping of R2D NASIC based FPGA.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	David B. Dgien, Poovaiah M. Palangappa, Nathan Altay Hunter, Jiayin Li, Kartik Mohanram	Compression architecture for bit-write reduction in non-volatile memory technologies.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Jacques-Olivier Klein, Csaba Andras Moritz, Sorin Cotofana (eds.)	IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014, Paris, France, July 8-10, 2014	NANOARCH	2014	DBLP BibTeX RDF
1	Melika Payvand, Justin Rofeh, Avantika Sodhi, Luke Theogarajan	A CMOS-memristive self-learning neural network for pattern classification applications.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Pilin Junsangsri, Fabrizio Lombardi, Jie Han 0001	HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Honghui Sun, Liang Fang, Yao Wang 0002, Yaqing Chi, Rulin Liu	A low contact resistance graphene field effect transistor with single-layer-channel and multi-layer-contact.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Nusrat Jahan Lisa, Hafiz Md. Hasan Babu	Minimization of a reversible quantum 2n-to-n BCD priority encoder.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Wanlong Chen, Xiao Yang 0006, Frank Zhigang Wang	Memristor content addressable memory.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Kejie Huang, Rong Zhao, Yong Lian 0001	STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Magnus Själander, Nina Shariati Nilsson, Stefanos Kaxiras	A tunable cache for approximate computing.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Jens Bürger 0002, Christof Teuscher	Volatile memristive devices as short-term memory in a neuromorphic learning architecture.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Miguel Diez-Garcia, Adrien F. Vincent, Nicolas Izard, Damien Querlioz	Monte Carlo simulations of carbon nanotube networks for optoelectronic applications.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Nandakishor Yadav, Shikha Jain, Manisha Pattanaik, G. K. Sharma 0001	NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Majid Yazdani, Giovanni De Micheli	Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Nickvash Kani, Azad Naeemi	Pipeline design in spintronic circuits.	NANOARCH	2014	DBLP DOI BibTeX RDF
1	Zhijie Chen, Lu Zhang, Xiuyuan Bi, Hai Li 0001	A pseudo-weighted sensing scheme for memristor based cross-point memory.	NANOARCH	2013	DBLP DOI BibTeX RDF

Publications at "NANOARCH"( http://dblp.L3S.de/Venues/NANOARCH )