Search results for "NOCS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jinho Lee, Kiyoung Choi	A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections.	NOCS	2013	DBLP DOI BibTeX RDF
1	Sean Franey, Mikko H. Lipasti	Accelerating atomic operations on GPGPUs.	NOCS	2013	DBLP DOI BibTeX RDF
1	Celine Azar, Stéphane Chevobbe, Yves Lhuillier, Jean-Philippe Diguet	SNet, a flexible, scalable network paradigm for manycore architectures.	NOCS	2013	DBLP DOI BibTeX RDF
1	Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture.	NOCS	2013	DBLP DOI BibTeX RDF
1	Li Zhou, Avinash Karanth Kodi	PROBE: Prediction-based optical bandwidth scaling for energy-efficient NoCs.	NOCS	2013	DBLP DOI BibTeX RDF
1	Amit Verma, Pritpal S. Multani, Daniel Mueller-Gritschneder, Vladimir Todorov, Ulf Schlichtmann	A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs.	NOCS	2013	DBLP DOI BibTeX RDF
1	Syed Minhaj Hassan, Sudhakar Yalamanchili	Centralized buffer router: A low latency, low power router for high radix NOCs.	NOCS	2013	DBLP DOI BibTeX RDF
1	Marcus Eggenberger, Martin Radetzki	Scalable parallel simulation of networks on chip.	NOCS	2013	DBLP DOI BibTeX RDF
1	Erfan Azarkhish, Igor Loi, Luca Benini	3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters.	NOCS	2013	DBLP DOI BibTeX RDF
1	Javier de San Pedro, Nikita Nikitin, Jordi Cortadella, Jordi Petit	Physical planning for the architectural exploration of large-scale chip multiprocessors.	NOCS	2013	DBLP DOI BibTeX RDF
1	Xueqian Zhao, Zhonghai Lu	Per-flow delay bound analysis based on a formalized microarchitectural model.	NOCS	2013	DBLP DOI BibTeX RDF
1		2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Tempe, AZ, USA, April 21-24, 2013	NOCS	2013	DBLP BibTeX RDF
1	Bo Zhao 0007, Youtao Zhang, Jun Yang 0002	A speculative arbiter design to enable high-frequency many-VC router in NoCs.	NOCS	2013	DBLP DOI BibTeX RDF
1	Yean-Ru Chen, Zi-Rong Wangt, Pao-Ann Hsiung, Sao-Jie Chen, Meng-Hsun Tsai	Backward probing deadlock detection for networks-on-chip.	NOCS	2013	DBLP DOI BibTeX RDF
1	Dominic DiTomaso, Avinash Karanth Kodi, David W. Matolak, Savas Kaya, Soumyasanta Laha, William Rayess	Energy-efficient adaptive wireless NoCs architecture.	NOCS	2013	DBLP DOI BibTeX RDF
1	Erik Fischer, Gerhard P. Fettweis	An accurate and scalable analytic model for round-robin arbitration in network-on-chip.	NOCS	2013	DBLP DOI BibTeX RDF
1	Mukund Ramakrishna, Paul V. Gratz, Alexander Sprintson	GCA: Global congestion awareness for load balance in Networks-on-Chip.	NOCS	2013	DBLP DOI BibTeX RDF
1	Ran Manevich, Israel Cidon, Avinoam Kolodny	Dynamic traffic distribution among hierarchy levels in hierarchical Networks-on-Chip (NoCs).	NOCS	2013	DBLP DOI BibTeX RDF
1	Shomit Das, Georgios Manetas, Kenneth S. Stevens, Roberto Suaya	Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm.	NOCS	2013	DBLP DOI BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Hannu Tenhunen	Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip.	NOCS	2013	DBLP DOI BibTeX RDF
1	Xiaohang Wang 0001, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi	On self-tuning networks-on-chip for dynamic network-flow dominance adaptation.	NOCS	2013	DBLP DOI BibTeX RDF
1	Chris Fallin, Greg Nazario, Xiangyao Yu, Kevin Kai-Wei Chang, Rachata Ausavarungnirun, Onur Mutlu	MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect.	NOCS	2012	DBLP DOI BibTeX RDF
1	Stavros Volos, Ciprian Seiculescu, Boris Grot, Naser Khosro Pour, Babak Falsafi, Giovanni De Micheli	CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers.	NOCS	2012	DBLP DOI BibTeX RDF
1	Snaider Carrillo, Jim Harkin, L. J. McDaid, Sandeep Pande, Seamus Cawley, Brian McGinley, Fearghal Morgan	Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations.	NOCS	2012	DBLP DOI BibTeX RDF
1	Javier Navaridas, Behram Khan, Salman Khan 0002, Paolo Faraboschi, Mikel Luján	Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation.	NOCS	2012	DBLP DOI BibTeX RDF
1	Paul Bogdan, Radu Marculescu, Siddharth Jain, Rafael Tornero Gavilá	An Optimal Control Approach to Power Management for Multi-Voltage and Frequency Islands Multiprocessor Platforms under Highly Variable Workloads.	NOCS	2012	DBLP DOI BibTeX RDF
1	Dan Zhao, Ruizhe Wu	Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip.	NOCS	2012	DBLP DOI BibTeX RDF
1	Georgios Tsiligiannis, Laurence Pierre	A Mixed Verification Strategy Tailored for Networks on Chip.	NOCS	2012	DBLP DOI BibTeX RDF
1	Gul N. Khan, Anita Tino	Synthesis of NoC Interconnects for Custom MPSoC Architectures.	NOCS	2012	DBLP DOI BibTeX RDF
1	Qiaoyan Yu, José Cano 0001, José Flich, Paul Ampadu	Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip.	NOCS	2012	DBLP DOI BibTeX RDF
1	Xi Chen, Zheng Xu 0006, Hyungjun Kim, Paul Gratz, Jiang Hu, Michael Kishinevsky, Ümit Y. Ogras	In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches.	NOCS	2012	DBLP DOI BibTeX RDF
1	Luca Ramini, Davide Bertozzi, Luca P. Carloni	Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints.	NOCS	2012	DBLP DOI BibTeX RDF
1	Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Khalid Latif 0002, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid Architectures.	NOCS	2012	DBLP DOI BibTeX RDF
1	Ahmed Abousamra, Rami G. Melhem, Alex K. Jones	Déjà Vu Switching for Multiplane NoCs.	NOCS	2012	DBLP DOI BibTeX RDF
1	Zhonghai Lu, Yi Wang	Dynamic Flow Regulation for IP Integration on Network-on-Chip.	NOCS	2012	DBLP DOI BibTeX RDF
1	Robert Hesse, Jeff Nicholls, Natalie D. Enright Jerger	Fine-Grained Bandwidth Adaptivity in Networks-on-Chip Using Bidirectional Channels.	NOCS	2012	DBLP DOI BibTeX RDF
1	Hyunjun Jang, Baik Song An, Nikhil Kulkarni, Ki Hwan Yum, Eun Jung Kim 0001	A Hybrid Buffer Design with STT-MRAM for On-Chip Interconnects.	NOCS	2012	DBLP DOI BibTeX RDF
1	Changlin Chen, Ye Lu 0003, Sorin Dan Cotofana	A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip.	NOCS	2012	DBLP DOI BibTeX RDF
1	Chen Sun 0003, Chia-Hsin Owen Chen, George Kurian, Lan Wei, Jason E. Miller, Anant Agarwal, Li-Shiuan Peh, Vladimir Stojanovic	DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling.	NOCS	2012	DBLP DOI BibTeX RDF
1	Martin Schoeberl, Florian Brandner, Jens Sparsø, Evangelia Kasapaki	A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems.	NOCS	2012	DBLP DOI BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Fahimeh Farahnakian, Juha Plosila, Pasi Liljeberg, Maurizio Palesi, Hannu Tenhunen	HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks.	NOCS	2012	DBLP DOI BibTeX RDF
1	Pierre Schamberger, Zhonghai Lu, Xianyang Jiang, Meikang Qiu	Modeling and Power Evaluation of On-Chip Router Components in Spintronics.	NOCS	2012	DBLP DOI BibTeX RDF
1	Yao Wang 0008, G. Edward Suh	Efficient Timing Channel Protection for On-Chip Networks.	NOCS	2012	DBLP DOI BibTeX RDF
1		2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Copenhagen, Denmark, 9-11 May, 2012	NOCS	2012	DBLP BibTeX RDF
1	Pablo Abad Fidalgo, Pablo Prieto, Lucia G. Menezo, Adrian Colaso, Valentin Puente, José-Ángel Gregorio	TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers.	NOCS	2012	DBLP DOI BibTeX RDF
1	Mario Lodde, José Flich, Manuel E. Acacio	Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support.	NOCS	2012	DBLP DOI BibTeX RDF
1	Nikita Nikitin, Javier de San Pedro, Josep Carmona 0001, Jordi Cortadella	Analytical Performance Modeling of Hierarchical Interconnect Fabrics.	NOCS	2012	DBLP DOI BibTeX RDF
1	Radu David, Paul Bogdan, Radu Marculescu, Ümit Y. Ogras	Dynamic power management of voltage-frequency island partitioned Networks-on-Chip using Intel's Single-chip Cloud Computer.	NOCS	2011	DBLP DOI BibTeX RDF
1	James W. Hanlon	The XMOS XK-XMP-64 development board.	NOCS	2011	DBLP DOI BibTeX RDF
1	Daniel Gebhardt, JunBok You, Kenneth S. Stevens	Link pipelining strategies for an application-specific asynchronous NoC.	NOCS	2011	DBLP DOI BibTeX RDF
1	Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas	Deadlock-free fine-grained thread migration.	NOCS	2011	DBLP DOI BibTeX RDF
1	Radu Marculescu, Michael Kishinevsky, Ran Ginosar, Karam S. Chatha (eds.)	NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011	NOCS	2011	DBLP DOI BibTeX RDF
1	Guopeng Wei, Paul Bogdan, Radu Marculescu	A software framework for trace analysis targeting multicore platforms design.	NOCS	2011	DBLP DOI BibTeX RDF
1	Qiaoyan Yu, Meilin Zhang, Paul Ampadu	A comprehensive Networks-on-Chip simulator for error control explorations.	NOCS	2011	DBLP DOI BibTeX RDF
1	Tom English, Emanuel M. Popovici	Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for Cryptographic accelerators.	NOCS	2011	DBLP DOI BibTeX RDF
1	Amlan Ganguly, Paul Wettin, Kevin Chang 0002, Partha Pratim Pande	Complex network inspired fault-tolerant NoC architectures with wireless links.	NOCS	2011	DBLP DOI BibTeX RDF
1	Ahmed Abousamra, Rami G. Melhem, Alex K. Jones	Two-hop Free-space based optical interconnects for chip multiprocessors.	NOCS	2011	DBLP DOI BibTeX RDF
1	Dan Zhao 0001, Yi Wang 0007, Jian Li 0059, Takamaro Kikkawa	Design of multi-channel wireless NoC to improve on-chip communication capacity!	NOCS	2011	DBLP DOI BibTeX RDF
1	Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny	NoCs simulation framework for OMNeT++.	NOCS	2011	DBLP DOI BibTeX RDF
1	Amlan Ganguly, Partha Kundu, Pradip Bose	Curbing energy cravings in networks: A cross-sectional view across the micro-macro boundary.	NOCS	2011	DBLP DOI BibTeX RDF
1	Amir-Mohammad Rahmani, Pasi Liljeberg, Khalid Latif 0002, Juha Plosila, Kameswar Rao Vaddina, Hannu Tenhunen	Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures.	NOCS	2011	DBLP DOI BibTeX RDF
1	Michael Papamichael, James C. Hoe, Onur Mutlu	FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations.	NOCS	2011	DBLP DOI BibTeX RDF
1	Yu-Hsiang Kao, H. Jonathan Chao	BLOCON: A Bufferless Photonic Clos network-on-chip architecture.	NOCS	2011	DBLP DOI BibTeX RDF
1	Gennette Gill, Sumedh S. Attarde, Geoffray Lacourba, Steven M. Nowick	A low-latency adaptive asynchronous interconnection network using bi-modal router nodes.	NOCS	2011	DBLP DOI BibTeX RDF
1	Somayyeh Koohi, Meisam Abdollahi, Shaahin Hessabi	All-optical wavelength-routed NoC based on a novel hierarchical topology.	NOCS	2011	DBLP DOI BibTeX RDF
1	Zhonghai Lu	Cross clock-domain TDM virtual circuits for networks on chips.	NOCS	2011	DBLP DOI BibTeX RDF
1	Fabien Clermidy, Nicolas Cassiau, N. Coste, Denis Dutoit, M. Fantini, Dimitri Ktenas, Romain Lemaire, L. Stefanizzi	Reconfiguration of a 3GPP-LTE telecommunication application on a 22-core NoC-based system-on-chip.	NOCS	2011	DBLP DOI BibTeX RDF
1	Onur Derin, Deniz Kabakci, Leandro Fiorin	Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors.	NOCS	2011	DBLP DOI BibTeX RDF
1	Nithin Michael, Milen Nikolov, Ao Tang, G. Edward Suh, Christopher Batten	Analysis of application-aware on-chip routing under traffic uncertainty.	NOCS	2011	DBLP DOI BibTeX RDF
1	Christof Teuscher, Cristian Grecu, Ting Lu, Ron Weiss	Challenges and promises of nano and bio communication networks.	NOCS	2011	DBLP DOI BibTeX RDF
1	Hyungjun Kim, Pritha Ghoshal, Boris Grot, Paul V. Gratz, Daniel A. Jiménez	Reducing network-on-chip energy consumption through spatial locality speculation.	NOCS	2011	DBLP DOI BibTeX RDF
1	Giorgos Passas, Manolis Katevenis, Dionisios N. Pnevmatikatos	VLSI micro-architectures for high-radix crossbar schedulers.	NOCS	2011	DBLP DOI BibTeX RDF
1	José Cano 0001, José Flich, José Duato, Marcello Coppola, Riccardo Locatelli	Efficient routing implementation in complex systems-on-chip.	NOCS	2011	DBLP DOI BibTeX RDF
1	Andreas Weichslgartner, Stefan Wildermann, Jürgen Teich	Dynamic decentralized mapping of tree-structured applications on NoC architectures.	NOCS	2011	DBLP DOI BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model.	NOCS	2011	DBLP DOI BibTeX RDF
1	Christopher Nitta, Kevin Macdonald, Matthew K. Farrens, Venkatesh Akella	Inferring packet dependencies to improve trace based simulation of on-chip networks.	NOCS	2011	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano	A vertical bubble flow network using inductive-coupling for 3-D CMPs.	NOCS	2011	DBLP DOI BibTeX RDF
1	Arpit Joshi, Madhu Mutyam	Prevention flow-control for low latency torus networks-on-chip.	NOCS	2011	DBLP DOI BibTeX RDF
1	Florentine Dubois, José Cano 0001, Marcello Coppola, José Flich, Frédéric Pétrot	Spidergon STNoC design flow.	NOCS	2011	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Hamed Sajjadi Kia, Om Prakash Yadav, Jingcao Hu	Energy and reliability oriented mapping for regular Networks-on-Chip.	NOCS	2011	DBLP DOI BibTeX RDF
1	Danyao Wang, Natalie D. Enright Jerger, J. Gregory Steffan	DART: A programmable architecture for NoC simulation on FPGAs.	NOCS	2011	DBLP DOI BibTeX RDF
1	Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, Awet Yemane Weldezion	Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks.	NOCS	2011	DBLP DOI BibTeX RDF
1	Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny	Delay analysis of wormhole based heterogeneous NoC.	NOCS	2011	DBLP DOI BibTeX RDF
1	Qiaoyan Yu, Meilin Zhang, Paul Ampadu	Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration.	NOCS	2011	DBLP DOI BibTeX RDF
1	Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini	A distributed and topology-agnostic approach for on-line NoC testing.	NOCS	2011	DBLP DOI BibTeX RDF
1	Freek Verbeek, Julien Schmaltz	Automatic verification for deadlock in networks-on-chips with adaptive routing and wormhole switching.	NOCS	2011	DBLP DOI BibTeX RDF
1	Najla Alfaraj, Junjie Zhang 0001, Yang Xu 0010, H. Jonathan Chao	HOPE: Hotspot congestion control for Clos network on chip.	NOCS	2011	DBLP DOI BibTeX RDF
1	Samuel Rodrigo, José Flich, Antoni Roca 0001, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato	Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing.	NOCS	2010	DBLP DOI BibTeX RDF	Fault-tolerance, Routing, Networks-on-chip
1	Daniel Gebhardt, JunBok You, Kenneth S. Stevens	Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs.	NOCS	2010	DBLP DOI BibTeX RDF	network, CAD, SoC, topology, asynchronous, floorplan, router, EDA, NoC, GALS
1	Paul Vincent Mejia, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella	Performance Evaluation of a Multicore System with Optically Connected Memory Modules.	NOCS	2010	DBLP DOI BibTeX RDF	OC-DIMM, DWDM, Performance Evaluation, DRAM, Optics
1	David Wolpert 0001, Bo Fu, Paul Ampadu	Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design.	NOCS	2010	DBLP DOI BibTeX RDF	delay borrowing, energy-efficient, interconnect, Temperature, low voltage
1	Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.	NOCS	2010	DBLP DOI BibTeX RDF	low power, Network-on-Chip, router, power gating
1	Alexandre Guerre, Nicolas Ventroux, Raphaël David, Alain Mérigot	Hierarchical Network-on-Chip for Embedded Many-Core Architectures.	NOCS	2010	DBLP DOI BibTeX RDF	hierarchical network on chip, area efficiency
1	Chia-Hsin Owen Chen, Niket Agarwal, Tushar Krishna, Kyung-Hoae Koo, Li-Shiuan Peh, Krishna Saraswat	Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs.	NOCS	2010	DBLP DOI BibTeX RDF
1	Chih-Hao Chao, Kai-Yuan Jheng, Hao-Yu Wang, Jia-Cheng Wu, An-Yeu Wu	Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems.	NOCS	2010	DBLP DOI BibTeX RDF	run-time thermal management, 3D NoC, routing, 3D IC, traffic-aware, throttling, thermal-aware
1	Keren Bergman	Photonic Chip-Scale Interconnection Networks for Performance-Energy Optimized Computing.	NOCS	2010	DBLP DOI BibTeX RDF
1	Yu-Hsiang Kao, Najla Alfaraj, Ming Yang, H. Jonathan Chao	Design of High-Radix Clos Network-on-Chip.	NOCS	2010	DBLP DOI BibTeX RDF
1	Mohamad Sawan	Low-Power Bioelectronics for Massively Parallel Neuromonitoring.	NOCS	2010	DBLP DOI BibTeX RDF
1	Paul Bogdan, Miray Kas, Radu Marculescu, Onur Mutlu	QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processors.	NOCS	2010	DBLP DOI BibTeX RDF	Self-Similar Stochastic Processes, Multi-fractal Analysis, Networks-on-Chip, Chip Multi-Processors
1	Yvain Thonnart, Romain Lemaire, Fabien Clermidy	Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms.	NOCS	2010	DBLP DOI BibTeX RDF	Distributed Systems, Networks-on-Chip

Publications at "NOCS"( http://dblp.L3S.de/Venues/NOCS )