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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 133 occurrences of 87 keywords
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Results
Found 207 publication records. Showing 207 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
14 | Randal E. Bryant |
Formal Verification of Pipelined Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for Construction and Analysis of Systems, 4th International Conference, TACAS '98, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS'98, Lisbon, Portugal, March 28 - April 4, 1998, Proceedings, pp. 1-4, 1998, Springer, 3-540-64356-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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14 | Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy |
A novel framework for logic verification in a synthesis environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1), pp. 20-32, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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14 | Zhuxing Zhao, Zhongcheng Li, Yinghua Min |
Waveform Polynomial Manipulation Using Bdds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 136-141, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
waveform polynomial manipulation, design verification and test, middle size circuits, complexity, data structure, high level synthesis, timing, logic design, combinational circuit, logic synthesis, binary decision diagram, directed acyclic graph, digital circuit, Boolean process |
14 | Rolf Drechsler |
Verification of Multi-Valued Logic Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 10-15, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multi-valued logic networks verification, ordered multi-valued decision diagrams, two-valued circuits, formal verification, heuristics, logic testing, directed graphs, directed acyclic graph, multivalued logic circuits, functional equivalence |
14 | Glenn Jennings |
Symbolic incompletely specified functions for correct evaluation in the presence of indeterminate input values. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 23-31, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
correct evaluation, indeterminate input values, Ordered Ternary Decision Diagram, OTDD, Boolean functions, symbolic computation, symbol manipulation, ternary logic, incompletely specified functions |
14 | Seiichiro Tani, Hiroshi Imai |
A Reordering Operation for an Ordered Binary Decision Diagram and an Extended Framework for Combinatorics of Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISAAC ![In: Algorithms and Computation, 5th International Symposium, ISAAC '94, Beijing, P. R. China, August 25-27, 1994, Proceedings, pp. 575-583, 1994, Springer, 3-540-58325-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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14 | Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga |
Variable ordering algorithms for ordered binary decision diagrams and their evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1), pp. 6-12, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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