Search results for "OBDDs"

Found 207 publication records. Showing 207 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Randal E. Bryant	Formal Verification of Pipelined Processors.	TACAS	1998	DBLP DOI BibTeX RDF
14	Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy	A novel framework for logic verification in a synthesis environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
14	Zhuxing Zhao, Zhongcheng Li, Yinghua Min	Waveform Polynomial Manipulation Using Bdds.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	waveform polynomial manipulation, design verification and test, middle size circuits, complexity, data structure, high level synthesis, timing, logic design, combinational circuit, logic synthesis, binary decision diagram, directed acyclic graph, digital circuit, Boolean process
14	Rolf Drechsler	Verification of Multi-Valued Logic Networks.	ISMVL	1996	DBLP DOI BibTeX RDF	multi-valued logic networks verification, ordered multi-valued decision diagrams, two-valued circuits, formal verification, heuristics, logic testing, directed graphs, directed acyclic graph, multivalued logic circuits, functional equivalence
14	Glenn Jennings	Symbolic incompletely specified functions for correct evaluation in the presence of indeterminate input values.	HICSS (1)	1995	DBLP DOI BibTeX RDF	correct evaluation, indeterminate input values, Ordered Ternary Decision Diagram, OTDD, Boolean functions, symbolic computation, symbol manipulation, ternary logic, incompletely specified functions
14	Seiichiro Tani, Hiroshi Imai	A Reordering Operation for an Ordered Binary Decision Diagram and an Extended Framework for Combinatorics of Graphs.	ISAAC	1994	DBLP DOI BibTeX RDF
14	Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga	Variable ordering algorithms for ordered binary decision diagrams and their evaluation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF

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