Search results for "ReConFig"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Osama G. Attia, Alex Grieve, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno	Accelerating all-pairs shortest path using a message-passing reconfigurable architecture.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Alfonso Rodríguez 0002, Juan Valverde, Eduardo de la Torre	Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs.	ReConFig	2015	DBLP DOI BibTeX RDF
1	C. Jayet-Griffon, Marie-Angela Cornelie, Paolo Maistri, Philippe Elbaz-Vincent, Régis Leveugle	Polynomial multipliers for fully homomorphic encryption on FPGA.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján	Analysis of FPGA and software approaches to simulate unconventional computer architectures.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Siddharth S. Bhargav, Rishvanth K. Prabakar, Young H. Cho	Accurate in-situ runtime measurement of energy per operation of system-on-chip on FPGA.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Zhongyuan Zhao 0004, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao	Resource-saving compile flow for coarse-grained reconfigurable architectures.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Timo Jaeschke, Patrick Imberg, Michael Zapke, Michael Hübner 0001, Nils Pohl	Scalable modular hardware platform for FPGA based industrial radar flowmeters.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Zoltán Endre Rákossy, Axel Acosta-Aponte, Tobias G. Noll, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay	Design and synthesis of reconfigurable control-flow structures for CGRA.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Thaddeus Koehn, Peter Athanas	Buffering strategies for ultra high-throughput stream processing.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Lukas Johannes Jung, Christian Hochberger	Feasibility of high level compiler optimizations in online synthesis.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Sen Ma, Hongyuan Ding, Miaoqing Huang, David Andrews 0001	Archborn: an open source tool for automated generation of chip heterogeneous multiprocessor architectures.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Nikhil Thomas, Andrew Felder, Christophe Bobda	Adaptive controller using runtime partial hardware reconfiguration for unmanned aerial vehicles (UAVs).	ReConFig	2015	DBLP DOI BibTeX RDF
1	Pongstorn Maidee, Alireza Kaviani	Improving FPGA NoC performance using virtual cut-through switching technique.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Hongyuan Ding, Miaoqing Huang	Exploiting hardware abstraction for hybrid parallel computing framework.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Vincent Migliore, Maria Mendez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, Guy Gogniat	Exploration of polynomial multiplication algorithms for homomorphic encryption schemes.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Pei Zhang 0009, Aaron Mills, Joseph Zambreno, Phillip H. Jones	A software configurable and parallelized coprocessor architecture for LQR control.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Jens Rettkowski, Andrew Boutros, Diana Göhringer	Real-time pedestrian detection on a xilinx zynq using the HOG algorithm.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Stefan Gehrer, Sebastien Leger, Georg Sigl	Aging effects on ring-oscillator-based physical unclonable functions on FPGAs.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Juri Schmidt, Ulrich Brüning 0001	openHMC - a configurable open-source hybrid memory cube controller.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Javier Pérez, Aiman Alabdo, Gabriel J. García, Jorge Pomares, Fernando Torres Medina	FPGA-based visual control of robot manipulators using dynamic perceptibility.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Syed Waqar Nabi, Wim Vanderbauwhede	Using type transformations to generate program variants for FPGA design space exploration.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Ajitesh Srivastava, Ren Chen, Viktor K. Prasanna, Charalampos Chelmis	A hybrid design for high performance large-scale sorting on FPGA.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Henitsoa Rakotomalala, Xuan Thuy Ngo, Zakaria Najm, Jean-Luc Danger, Sylvain Guilley	Private circuits II versus fault injection attacks.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Johanna Sepúlveda, Daniel Flórez, Guy Gogniat	Efficient and flexible NoC-based group communication for secure MPSoCs.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Hongyuan Ding, Miaoqing Huang	Achieving energy-efficiency on MPSoCs: performance and power optimizations.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Sven Hager, Daniel Bendyk, Björn Scheuermann 0001	Partial reconfiguration and specialized circuitry for flexible FPGA-based packet processing.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Maxime Lecomte, Jacques J. A. Fournier, Philippe Maurine	Thoroughly analyzing the use of ring oscillators for on-chip hardware trojan detection.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Enrico A. Deiana, Marco Rabozzi, Riccardo Cattaneo, Marco D. Santambrogio	A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Da Tong, Viktor K. Prasanna	High throughput sketch based online heavy change detection on FPGA.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo	Power modelling for saving strategies in coarse grained reconfigurable systems.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Michael Hübner 0001, Maya B. Gokhale, René Cumplido (eds.)	International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, Riviera Maya, Mexico, December 7-9, 2015	ReConFig	2015	DBLP BibTeX RDF
1	Vincent Mirian, Paul Chow	UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAs.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Alexander Boschmann, Andreas Agne, Linus Witschen, Georg Thombansen, Florian Kraus, Marco Platzner	FPGA-based acceleration of high density myoelectric signal processing.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Joshua Mack, Sam Bellestri, Daniel Llamocca	Floating point CORDIC-based architecture for powering computation.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Sang Woo Jun, Chanwoo Chung, Arvind	Large-scale high-dimensional nearest neighbor search using flash memory with in-store processing.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Subhadeep Banik, Andrey Bogdanov, Francesco Regazzoni 0001	Exploring the energy consumption of lightweight blockciphers in FPGA.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Thaddeus Koehn, Matthew Carrick, Peter Athanas	An efficient structure for run-time configuration of synthesis and channelizer filter banks.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Luis Contreras, Sérgio Cruz, José Maurício S. T. Motta, Carlos H. Llanos	FPGA implementation of the EKF algorithm for localization in mobile robotics using a unified hardware module approach.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Ryan Pattison, Christian Fobel, Gary William Grewal, Shawki Areibi	Scalable analytic placement for FPGA on GPGPU.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Javier Alejandro Varela, Christian Brugger, Christian de Schryver, Norbert Wehn, Songyin Tang, Steffen Omland	Exploiting the brownian bridge technique to improve longstaff-schwartz american option pricing on FPGA systems.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Andrew Bean, Nachiket Kapre, Peter Y. K. Cheung	G-DMA: improving memory access performance for hardware accelerated sparse graph computation.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Bruno A. Silva, Alexandre C. B. Delbem, Vanderlei Bonato, Pedro C. Diniz	Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Ekawat Homsirikamol, William Diehl, Ahmed Ferozpuri, Farnoud Farahmand, Malik Umar Sharif, Kris Gaj	A universal hardware API for authenticated ciphers.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Burak Erbagci, Mudit Bhargava, Rachel Dondero, Ken Mai	Deeply hardware-entangled reconfigurable logic and interconnect.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Marc Reichenbach, Tobias Lieske, Steffen Vaas, Konrad Häublein, Dietmar Fey	FAUPU - A design framework for the development of programmable image processing architectures.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Amit Kulkarni 0002, Kizheppatt Vipin, Dirk Stroobandt	MiCAP: a custom reconfiguration controller for dynamic circuit specialization.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano	A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2.	ReConFig	2015	DBLP DOI BibTeX RDF
1	L. Canche Santos, Alejandro Castillo Atoche, J. Vazquez Castillo, Omar Longoria-Gandara, Roberto Carrasco-Alvarez, Jaime Ortegón-Aguilar	An improved hardware design for matrix inverse based on systolic array QR decomposition and piecewise polynomial approximation.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Jose Fernando Zazo, Sergio López-Buedo, Yury Audzevich, Andrew W. Moore 0002	A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Javier Ramos 0002, Jorge E. López de Vergara, Javier Aracil 0001	Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Joost Hoozemans, Jens Johansen, Jeroen van Straten, Anthony Brandon, Stephan Wong	Multiple contexts in a multi-ported VLIW register file implementation.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Shijie Zhou 0001, Charalampos Chelmis, Viktor K. Prasanna	Optimizing memory performance for FPGA implementation of pagerank.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Christopher Blochwitz, Jan Moritz Joseph, Rico Backasch, Thilo Pionteck, Stefan Werner 0002, Dennis Heinrich, Sven Groppe	An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Anthony Brandon, Joost Hoozemans, Jeroen van Straten, Arthur Francisco Lorenzon, Anderson Luiz Sartor, Antonio Carlos Schneider Beck, Stephan Wong	A sparse VLIW instruction encoding scheme compatible with generic binaries.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Riccardo Cattaneo, Gabriele Pallotta, Donatella Sciuto, Marco D. Santambrogio	Explicitly isolating data and computation in high level synthesis: the role of polyhedral framework.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Amit Kulkarni 0002, Robin Bonamy, Dirk Stroobandt	Power measurements and analysis for dynamic circuit specialization.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Andrew Powell 0002, Dennis Silage	Statistical performance of the ARM cortex A9 accelerator coherency port in the xilinx zynq SoC for real-time applications.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Kevin Lee, Peter Athanas	Shape exploration for modules in rapid assembly workflows.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Rico Backasch, Gerald Hempel, Christopher Blochwitz, Stefan Werner 0002, Sven Groppe, Thilo Pionteck	An architectural template for composing application specific datapaths at runtime.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Maya B. Gokhale, Michael Hübner 0001, René Cumplido	Message from chairs.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Hamza Bendaoudi, Qifeng Gan, Farida Cheriet, Houssem Ben Tahar, J. M. Pierre Langlois	A run-length encoding co-processor for retinal image texture analysis.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Carlo Sau, Luca Fanni, Paolo Meloni, Luigi Raffo, Francesca Palumbo	Reconfigurable coprocessors synthesis in the MPEG-RVC domain.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Sam Skalicky, Tejaswini Ananthanarayana, Sonia López, Marcin Lukowiak	Designing customized ISA processors using high level synthesis.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Michal Varchola, Milos Drutarovský, Marek Repka, Pavol Zajac	Side channel attack on multiprecision multiplier used in protected ECDSA implementation.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Viorel Suse, Dan Ionescu	A real-time reconfigurable architecture for face detection.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Carl Ahlberg, Fredrik Ekstrand, Mikael Ekström, Giacomo Spampinato, Lars Asplund	GIMME2 - an embedded system for stereo vision and processing of megapixel images with FPGA-acceleration.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Oskar Mencer	Keynote 1 - From data to information to flow.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Giulia Gnemmi, Mattia Crippa, Gianluca Durelli, Riccardo Cattaneo, Gabriele Pallotta, Marco D. Santambrogio	On how to efficiently accelerate brain network analysis on FPGA-based computing system.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Festus Hategekimana, Adil Tbatou, Christophe Bobda, Charles A. Kamhoua, Kevin A. Kwiat	Hardware isolation technique for IRC-based botnets detection.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Roberto de Lima, José Martínez-Carranza, Alicia Morales-Reyes, René Cumplido	Accelerating the construction of BRIEF descriptors using an FPGA-based architecture.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Hugo A. Andrade, Patricia Derler, John C. Eidson, Ya-Shian Li-Baboud, Aviral Shrivastava, Kevin B. Stanton, Marc Weiss	Towards a reconfigurable distributed testbed to enable advanced research and development of timing and synchronization in cyber-physical systems.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Arif Irwansyah, Omar W. Ibraheem, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert 0001	FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking.	ReConFig	2015	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai	An AWF digital spectrometer for a radio telescope.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Brad White, Brent E. Nelson	Tincr - A custom CAD tool framework for Vivado.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Pei Luo, Yunsi Fei, Xin Fang 0001, A. Adam Ding, Miriam Leeser, David R. Kaeli	Power analysis attack on hardware implementation of MAC-Keccak on FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Jones Yudi Mori, Michael Hübner 0001	A high-level analysis of a multi-core vision processor using SystemC and TLM2.0.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Enrique Mariano Lizarraga, Graciela Corral-Briones	A practical scheme for implementing dynamic spectral precoding in OFDM.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Thomas P. Flatley	Keynote - SpaceCube - A family of reconfigurable hybrid on-board science data processors.	ReConFig	2014	DBLP DOI BibTeX RDF
1	David Uliana, Peter M. Athanas, Krzysztof Kepa	FPGA-based accelerator development for non-engineers.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Ryo Konomura, Koichi Hori	Phenox: Zynq 7000 based quadcopter robot.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Andrea Sanny, Yi-Hua E. Yang, Viktor K. Prasanna	Energy-efficient histogram on FPGA.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Marco Tulio Ramírez-Torres, José S. Murguía Ibarra, Marcela Mejía-Carlos	FPGA implementation of a reconfigurable image encryption system.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Vaibhav R. Gandhi, Yun Rock Qu, Viktor K. Prasanna	High-throughput hash-based online traffic classification engines on FPGA.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Sam Skalicky, Sonia López, Marcin Lukowiak, Christopher A. Wood	Mission control: A performance metric and analysis of control logic for pipelined architectures on FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Markus Happe, Yujiao Huang, Ariane Keller	Dynamic protocol stacks in smart camera networks.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Karim M. A. Ali, Rabie Ben Atitallah, Saïd Hanafi, Jean-Luc Dekeyser	A generic pixel distribution architecture for parallel video processing.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Pei Luo, Yunsi Fei, Liwei Zhang, A. Adam Ding	Side-channel power analysis of different protection schemes against fault attacks on AES.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Alexander Fell, Zoltán Endre Rákossy, Anupam Chattopadhyay	Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Johanna Sepúlveda, Guy Gogniat, Daniel Florez, Jean-Philippe Diguet, César Pedraza, Marius Strum	3D-LeukoNoC: A dynamic NoC protection.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Simon Schulz, Oliver Bringmann 0001, Thomas Schweizer, Wolfgang Rosenstiel	Rotated parallel mapping: A novel approach for mapping data parallel applications on CGRAs.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Viet Vu Duy, Oliver Sander, Timo Sandmann, Steffen Bähr, Jan Heidelberger, Jürgen Becker 0001	Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualization.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Kaveh Aasaraai, Andreas Moshovos	What limits the operating frequency of a soft processor design.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Vladimir Rodriguez, José F. Martínez, Jesús Ariel Carrasco-Ochoa, Manuel Sabino Lazo-Cortés, René Cumplido, Claudia Feregrino Uribe	A hardware architecture for filtering irreducible testors.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Rui Policarpo Duarte, Christos-Savvas Bouganis	Zero-latency datapath error correction framework for over-clocking DSP applications on FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Jan Gray	Keynote - The past and future of FPGA soft processors.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Quang-Hai Khuat, Daniel Chillet, Michael Hübner 0001	Dynamic run-time hardware/software scheduling for 3D reconfigurable SoC.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Benedikt Janßen, Michael Hübner 0001, Timo Jaeschke	An AXI compatible cypress EZ-USB FX3 interface for USB-3.0 SuperSpeed.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Jotham Vaddaboina Manoranjan, Kenneth S. Stevens	An a-FPGA architecture for relative timing based asynchronous designs.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Benoit Chappet de Vangel, César Torres-Huitzil, Bernard Girau	Spiking dynamic neural fields architectures on FPGA.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Amit Kulkarni 0002, Tom Davidson, Karel Heyse, Dirk Stroobandt	Improving reconfiguration speed for dynamic circuit specialization using placement constraints.	ReConFig	2014	DBLP DOI BibTeX RDF

Publications at "ReConFig"( http://dblp.L3S.de/Venues/ReConFig )