|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 526 occurrences of 280 keywords
|
|
|
Results
Found 503 publication records. Showing 503 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Shahnawaz Talpur, Feng Shi 0009, Yizhuo Wang |
Communication Locality Analysis of Triplet-Based Hierarchical Interconnection Network in Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NPC ![In: Network and Parallel Computing, 9th IFIP International Conference, NPC 2012, Gwangju, Korea, September 6-8, 2012. Proceedings, pp. 33-41, 2012, Springer, 978-3-642-35605-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Aparna Mandke Dani, Y. N. Srikant, Bharadwaj Amrutur |
Efficient cache exploration method for a tiled chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: 19th International Conference on High Performance Computing, HiPC 2012, Pune, India, December 18-22, 2012, pp. 1-6, 2012, IEEE Computer Society, 978-1-4673-2372-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Guo Cheng, Luo Chen, Qiu-Yun Wu, Ning Jing |
Parallelization Methods for Edge Extraction Applied to Chip Multiprocessor Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 12th IEEE International Conference on Computer and Information Technology, CIT 2012, Chengdu, Sichuan, China, October 27-29, 2012, pp. 156-162, 2012, IEEE Computer Society, 978-1-4673-4873-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Shufan Yang, Qiang Wu, Xiongren Xiao, Renfa Li, Dominic Hillenbrand |
Fair Access to External Memory for Chip-multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, IPDPS 2012, Shanghai, China, May 21-25, 2012, pp. 300-305, 2012, IEEE Computer Society, 978-1-4673-0974-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Mohammad Ghasemazar, Hadi Goudarzi, Massoud Pedram |
Robust optimization of a Chip Multiprocessor's performance under power and thermal constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 30th International IEEE Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, September 30 - Oct. 3, 2012, pp. 108-114, 2012, IEEE Computer Society, 978-1-4673-3051-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Matthew DeVuyst, Ashish Venkat, Dean M. Tullsen |
Execution migration in a heterogeneous-ISA chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2012, London, UK, March 3-7, 2012, pp. 261-272, 2012, ACM, 978-1-4503-0759-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Pablo Prieto, Valentin Puente, José-Ángel Gregorio |
Multilevel Cache Modeling for Chip-Multiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 10(2), pp. 49-52, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Fakhar Anjam, Muhammad Faisal Nadeem, Stephan Wong |
Targeting code diversity with run-time adjustable issue-slots in a chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pp. 1358-1363, 2011, IEEE, 978-1-61284-208-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Mohammad Ghasemazar, Massoud Pedram |
Variation aware dynamic power management for chip multiprocessor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pp. 473-478, 2011, IEEE, 978-1-61284-208-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Sanghoon Lee 0006, James Tuck 0001 |
Automatic parallelization of fine-grained meta-functions on a chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Proceedings of the CGO 2011, The 9th International Symposium on Code Generation and Optimization, Chamonix, France, April 2-6, 2011, pp. 130-140, 2011, IEEE Computer Society, 978-1-61284-356-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Sanghoon Lee 0006, Devesh Tiwari, Yan Solihin, James Tuck 0001 |
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), February 12-16 2011, San Antonio, Texas, USA, pp. 99-110, 2011, IEEE Computer Society, 978-1-4244-9432-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Malèk Channoufi, Pierre Lecoy, Rabah Attia, Bruno Delacressonniere, S. Garcia |
Toward All Optical Interconnections in Chip Multiprocessor (2). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011, pp. 501-504, 2011, IEEE Computer Society, 978-1-4577-1734-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Vassilios A. Chouliaras, George Lentaris, Dionisios I. Reisis, David Stevens |
Customizing a VLIW Chip Multiprocessor for Motion Estimation Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS Workshops ![In: ARCS 2011 - 24th International Conference on Architecture of Computing Systems 2011, Workshop Proceedings, February 22-23, 2011, Como, Italy., 2011, VDE-Verlag, 978-3-8007-3333-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
16 | Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen |
Explorations of optimal core and cache placements for Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCHIP ![In: 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, pp. 1-6, 2011, IEEE, 978-1-4577-0514-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen |
Optimal memory controller placement for chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2011, part of ESWeek '11 Seventh Embedded Systems Week, Taipei, Taiwan, 9-14 October, 2011, pp. 217-226, 2011, ACM, 978-1-4503-0715-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Jian Wang 0035, Andreas Karlsson, Joar Sohl, Magnus Pettersson, Dake Liu |
A multi-level arbitration and topology free streaming network for chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011, pp. 153-158, 2011, IEEE, 978-1-61284-192-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem |
Cache equalizer: a placement mechanism for chip multiprocessor distributed shared caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, 6th International Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26, 2011. Proceedings, pp. 177-186, 2011, ACM, 978-1-4503-0241-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Limin Han, Deyuan Gao, Xiaoya Fan, Liwen Shi, Jianfeng An |
Global Prefetcher Aggressiveness Control for Chip-Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIS ![In: Seventh International Conference on Computational Intelligence and Security, CIS 2011, Sanya, Hainan, China, December 3-4, 2011, pp. 273-277, 2011, IEEE Computer Society, 978-1-4577-2008-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt |
Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(9), pp. 1376-1380, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Ozcan Ozturk 0001 |
Improving chip multiprocessor reliability through code replication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 36(3), pp. 480-490, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Fei Guo, Yan Solihin, Li Zhao 0002, Ravishankar R. Iyer 0001 |
Quality of service shared cache management in chip multiprocessor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 7(3), pp. 14:1-14:33, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Christof Pitter, Martin Schoeberl |
A real-time Java chip-multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 10(1), pp. 9:1-9:34, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | D. Ramakrishnan, Y. L. Wu, W. B. Jone |
Design and Analysis of Location Caches in a NoC-Based Chip Multiprocessor System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 6(2), pp. 240-262, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Quentin L. Meunier, Frédéric Pétrot, Jean-Louis Roch |
Hardware/software support for adaptive work-stealing in on-chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 56(8), pp. 392-406, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Long Zheng 0001, Mianxiong Dong, Hai Jin 0001, Minyi Guo, Song Guo 0001, Xuping Tu |
The Core Degree Based Tag Reduction on Chip Multiprocessor to Balance Energy Saving and Performance Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NPC ![In: Network and Parallel Computing, IFIP International Conference, NPC 2010, Zhengzhou, China, September 13-15, 2010. Proceedings, pp. 358-372, 2010, Springer, 978-3-642-15671-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | David Stevens, Vassilios A. Chouliaras |
LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2010, 5-7 July 2010, Lixouri Kefalonia, Greece, pp. 122-126, 2010, IEEE Computer Society, 978-0-7695-4076-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen |
Operating System Processor Scheduler Design for Future Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS Workshops ![In: ARCS '10 - 23th International Conference on Architecture of Computing Systens 2010, Workshop Proceedings, February 22-23, 2010, Hannover, Germany, pp. 69-76, 2010, VDE Verlag, 978-3-8007-3222-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
16 | Dan Upton, Kim M. Hazelwood |
Design of a custom VEE core in a chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SASP ![In: IEEE 8th Symposium on Application Specific Processors, SASP 2010, Anaheim, CA, USA, June 13-14, 2010, pp. 97-100, 2010, IEEE Computer Society, 978-1-4244-7952-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Kunle Olukotun |
Chip multiprocessor architecture: A programmability-driven approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 24th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010, Atlanta, Georgia, USA, 19-23 April 2010 - Conference Proceedings, pp. 1, 2010, IEEE. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Konstantinos Krommydas, George Tsoublekas, Christos D. Antonopoulos, Nikolaos Bellas |
Mapping and optimization of the AVS video decoder on a high performance chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2010 IEEE International Conference on Multimedia and Expo, ICME 2010, 19-23 July 2010, Singapore, pp. 896-901, 2010, IEEE Computer Society, 978-1-4244-7491-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedram |
Minimizing energy consumption of a chip multiprocessor through simultaneous core consolidation and DVFS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 49-52, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Danfeng Zhu, Rui Wang 0014, Hui Wang, Depei Qian, Zhongzhi Luan, Tianshu Chu |
A Fair Thread-Aware Memory Scheduling Algorithm for Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP (1) ![In: Algorithms and Architectures for Parallel Processing, 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings. Part I, pp. 174-185, 2010, Springer, 978-3-642-13118-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Jiayin Li, Meikang Qiu, Jianwei Niu 0002, Tianzhou Chen, Yongxin Zhu 0001 |
Real-Time Constrained Task Scheduling in 3D Chip Multiprocessor to Reduce Peak Temperature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, EUC 2010, Hong Kong, China, 11-13 December 2010, pp. 170-176, 2010, IEEE Computer Society, 978-0-7695-4322-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Shaobo Liu, Jingyi Zhang, Qing Wu 0002, Qinru Qiu |
Thermal-aware job allocation and scheduling for three dimensional chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 11th International Symposium on Quality of Electronic Design (ISQED 2010), 22-24 March 2010, San Jose, CA, USA, pp. 390-398, 2010, IEEE, 978-1-4244-6455-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedram |
Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 11th International Symposium on Quality of Electronic Design (ISQED 2010), 22-24 March 2010, San Jose, CA, USA, pp. 362-371, 2010, IEEE, 978-1-4244-6455-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Christophe Bobda, Philipp Mahr, Benjamin Andres, Harold Ishebabi |
Application-driven architecture synthesis of on-chip Multiprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCS ![In: Proceedings of the 2010 International Conference on High Performance Computing & Simulation, HPCS 2010, June 28 - July 2, 2010, Caen, France, pp. 591-598, 2010, IEEE, 978-1-4244-6828-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Magnus Jahre, Marius Grannæs, Lasse Natvig |
DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings, pp. 292-306, 2010, Springer, 978-3-642-11514-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Sebastian Herbert, Diana Marculescu |
Mitigating the Impact of Variability on Chip-Multiprocessor Power and Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 17(10), pp. 1520-1533, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Gabor Madl, Sudeep Pasricha, Nikil D. Dutt, Sherif Abdelwahed |
Cross-abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Informatics ![In: IEEE Trans. Ind. Informatics 5(3), pp. 241-256, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Davy Genbrugge, Lieven Eeckhout |
Chip Multiprocessor Design Space Exploration through Statistical Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 58(12), pp. 1668-1681, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Gilbert Hendry, Shoaib Kamil 0001, Aleksandr Biberman, Johnnie Chan, Benjamin G. Lee, Marghoob Mohiyuddin, Ankit Jain, Keren Bergman, Luca P. Carloni, John Kubiatowicz, Leonid Oliker, John Shalf |
Analysis of photonic networks for a chip multiprocessor using scientific applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings, pp. 104-113, 2009, IEEE Computer Society, 978-1-4244-4142-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Taecheol Oh, Hyunjin Lee, Kiyeon Lee, Sangyeun Cho |
An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, 13-15 May 2009, Tampa, Florida, USA, pp. 181-186, 2009, IEEE Computer Society, 978-0-7695-3684-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Shoumeng Yan, Xiaocheng Zhou, Ying Gao, Hu Chen, Sai Luo, Peinan Zhang, Naveen Cherukuri, Ronny Ronen, Bratin Saha |
Terascale chip multiprocessor memory hierarchy and programming model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: 16th International Conference on High Performance Computing, HiPC 2009, December 16-19, 2009, Kochi, India, Proceedings, pp. 150-159, 2009, IEEE Computer Society, 978-1-4244-4922-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Yue Wu, Lei Xu, Hongbin Yang |
Loop Selection to Boost Thread Level Speculation Parallelism in Chip Multiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT (2) ![In: Ninth IEEE International Conference on Computer and Information Technology, Xiamen, China, CIT 2009, 11-14 October 2009, Proceedings, Volume II, pp. 249-253, 2009, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria |
Variability-aware robust design space exploration of chip multiprocessor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 323-328, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Magnus Jahre, Marius Grannæs, Lasse Natvig |
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: 11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009, 25-27 June 2009, Seoul, Korea, pp. 622-629, 2009, IEEE, 978-0-7695-3738-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | S. Subha |
An Algorithm for Parallel Execution of Loops in Chip Multiprocessor Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARTCom ![In: ARTCom 2009, International Conference on Advances in Recent Technologies in Communication and Computing, Kottayam, Kerala, India, 27-28 October 2009, pp. 85-89, 2009, IEEE Computer Society, 978-0-7695-3845-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Shu-Yen Lin, Chan-Cheng Hsu, An-Yeu Wu |
A Scalable Built-in Self-test/Self-diagnosis Architecture for 2D-Mesh based Chip Multiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 2317-2320, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Kazuaki Ishizaki, Toshio Nakatani, Shahrokh Daijavad |
Analyzing and improving performance scalability of commercial server workloads on a chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IISWC ![In: Proceedings of the 2009 IEEE International Symposium on Workload Characterization, IISWC 2009, October 4-6, 2009, Austin, TX, USA, pp. 217-226, 2009, IEEE Computer Society, 978-1-4244-5156-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Jin Cui, Douglas L. Maskell |
Dynamic thermal-aware scheduling on chip multiprocessor for soft real-time system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 393-396, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic tas, post thermal map, cmp, soft real-time |
16 | Andrew Cassidy, Andreas G. Andreou |
Analytical methods for the design and optimization of chip-multiprocessor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CISS ![In: 43rd Annual Conference on Information Sciences and Systems, CISS 2009, The John Hopkins University, Baltimore, MD, USA, 18-20 March 2009, pp. 482-487, 2009, IEEE, 978-1-4244-2733-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Xin Jin 0003, Alexander D. Rast, Francesco Galluppi, Muhammad Mukaram Khan, Steve B. Furber |
Implementing Learning on the SpiNNaker Universal Neural Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONIP (1) ![In: Neural Information Processing, 16th International Conference, ICONIP 2009, Bangkok, Thailand, December 1-5, 2009, Proceedings, Part I, pp. 425-432, 2009, Springer, 978-3-642-10676-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Dietmar Tutsch, Daniel Lüdtke |
Chip Multiprocessor Traffic Models Providing Consistent Multicast and Spatial Distributions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Simul. ![In: Simul. 84(2-3), pp. 61-73, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Ravi Kiran Karanam, Arun Ravindran, Arindam Mukherjee 0001 |
A stream chip-multiprocessor for bioinformatics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 36(2), pp. 2-9, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Konstantinos Tatas, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, Stephan Wong |
Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Process. Lett. ![In: Parallel Process. Lett. 18(2), pp. 291-306, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara |
Power-Aware Compiler Controllable Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 91-C(4), pp. 432-439, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Russ Joseph |
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8), pp. 1479-1492, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Rui Gong, Kui Dai, Zhiying Wang 0003 |
Transient Fault Recovery on Chip Multiprocessor based on Dual Core Redundancy and Context Saving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICYCS ![In: Proceedings of the 9th International Conference for Young Computer Scientists, ICYCS 2008, Zhang Jia Jie, Hunan, China, November 18-21, 2008, pp. 148-153, 2008, IEEE Computer Society, 978-0-7695-3398-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Christof Pitter, Martin Schoeberl |
Performance evaluation of a java chip-multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIES ![In: IEEE Third International Symposium on Industrial Embedded Systems, SIES 2008, Montpellier / La Grande Motte, France, June 11-13, 2008, pp. 34-42, 2008, IEEE, 978-1-4244-1994-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Abhishek Bhattacharjee, Gilberto Contreras, Margaret Martonosi |
Full-system chip multiprocessor power evaluations using FPGA-based emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 335-340, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Jun Zhang, Xiao-Ya Fan, Song-He Liu |
A Pollution Alleviative L2 Cache Replacement Policy for Chip Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAS ![In: Proceedings of The 2008 IEEE International Conference on Networking, Architecture, and Storage, NAS 2008, June 12-14, 2008, Chongqing, China, pp. 310-316, 2008, IEEE Computer Society, 978-0-7695-3187-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Michael Gschwind |
Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 478-485, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Muhammad Mukaram Khan, David R. Lester, Luis A. Plana, Alexander D. Rast, Xin Jin 0003, Eustace Painkras, Stephen B. Furber |
SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2008, part of the IEEE World Congress on Computational Intelligence, WCCI 2008, Hong Kong, China, June 1-6, 2008, pp. 2849-2856, 2008, IEEE, 978-1-4244-1820-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Rui Gong, Kui Dai, Zhiying Wang 0003 |
Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008, 15-17 December 2008, Taipei, Taiwan, pp. 273-280, 2008, IEEE Computer Society, 978-0-7695-3448-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Masaaki Kondo, Hiroshi Sasaki 0001, Hiroshi Nakamura |
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 35(1), pp. 31-38, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Haakon Dybdahl, Per Stenström, Lasse Natvig |
An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 35(4), pp. 45-52, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Kyriakos Stavrou, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso |
Chip multiprocessor based on data-driven multithreading model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Syst. Archit. ![In: Int. J. High Perform. Syst. Archit. 1(1), pp. 34-43, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert 0001 |
Resource efficiency of the GigaNetIC chip multiprocessor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 53(5-6), pp. 285-299, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara |
Power-Aware Compiler Controllable Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 427, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Christopher LaFrieda, Engin Ipek, José F. Martínez, Rajit Manohar |
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007, 25-28 June 2007, Edinburgh, UK, Proceedings, pp. 317-326, 2007, IEEE Computer Society, 0-7695-2855-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun |
ATLAS: a chip-multiprocessor with transactional memory support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 3-8, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Jisheng Zhao, Matthew Horsnell, Ian Rogers, Andrew Dinn, Chris C. Kirkham, Ian Watson |
Optimizing Chip Multiprocessor Work Distribution Using Dynamic Compilation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2007, Parallel Processing, 13th International Euro-Par Conference, Rennes, France, August 28-31, 2007, Proceedings, pp. 258-267, 2007, Springer, 978-3-540-74465-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Automatic parallelization, dynamic execution, feedback-directed optimization |
16 | Étienne Ogoubi, Abdelhakim Hafid, Marcel Turcotte |
An Isometric on on-Chip Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007, pp. 991-994, 2007, IEEE, 978-1-4244-1377-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Lei Miao 0002, Yong Qi, Di Hou, Yue-hua Dai |
Energy-Aware Scheduling Tasks on Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNC (4) ![In: Third International Conference on Natural Computation, ICNC 2007, Haikou, Hainan, China, 24-27 August 2007, Volume 4, pp. 319-323, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Mikhail Smelyanskiy, Victor W. Lee, Daehyun Kim 0001, Anthony D. Nguyen, Pradeep Dubey |
Scaling performance of interior-point method on large-scale chip multiprocessor system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, SC 2007, November 10-16, 2007, Reno, Nevada, USA, pp. 22, 2007, ACM Press, 978-1-59593-764-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Pei Gu, Uzi Vishkin |
Case study of gate-level logic simulation on an extremely fine-grained chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Embed. Comput. ![In: J. Embed. Comput. 2(2), pp. 181-190, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
16 | Patrick Anthony La Fratta, James M. Baker Jr. |
Exploring power reduction options for a single-chip multiprocessor through system-level modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Embed. Comput. ![In: J. Embed. Comput. 2(2), pp. 235-247, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
16 | Francisco J. Villa, Manuel E. Acacio, José M. García 0001 |
On the Evaluation of Dense Chip-Multiprocessor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006, pp. 21-27, 2006, IEEE, 1-4244-0155-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Haakon Dybdahl, Per Stenström, Lasse Natvig |
An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEDEA@PACT ![In: Proceedings of the 2006 workshop on MEmory performance - DEaling with Applications, systems and architectures, MEDEA '06, Seattle, Washington, USA, September 16-20, 2006, pp. 45-52, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Pengyong Ma, Shuming Chen |
MID: a Novel Coherency Protocol in Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Sixth International Conference on Computer and Information Technology (CIT 2006), 20-22 September 2006, Seoul, Korea, pp. 50, 2006, IEEE Computer Society, 0-7695-2687-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Gregory Buehrer, Yen-Kuang Chen, Srinivasan Parthasarathy 0001, Anthony D. Nguyen, Amol Ghoting, Daehyun Kim 0001 |
Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance and Correctness ![In: Proceedings of the 2006 workshop on Memory System Performance and Correctness, San Jose, California, USA, October 11, 2006, pp. 31-40, 2006, ACM, 1-59593-578-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | David A. Wood 0001 |
Keynote talk challenges in chip multiprocessor memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance and Correctness ![In: Proceedings of the 2006 workshop on Memory System Performance and Correctness, San Jose, California, USA, October 11, 2006, pp. 61, 2006, ACM, 1-59593-578-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Haixia Wang 0001, Dongsheng Wang 0002, Peng Li 0031 |
SRC-based Cache Coherence Protocol in Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCST ![In: Japan-China Joint Workshop on Frontier of Computer Science and Technology, FCST 2006, Fukushima, Japan, 17-18 November, 2006, pp. 60-70, 2006, IEEE Computer Society, 0-7695-2721-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Stefanos Kaxiras, Erik Hagersten |
Modeling Cache Sharing on Chip Multiprocessor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IISWC ![In: Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC 2006, October 25-27, 2006, San Jose, California, USA, pp. 160-171, 2006, IEEE Computer Society, 1-4244-0508-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Michael Ruogu Zhang |
Latency reduction techniques in chip multiprocessor cache systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2006 |
RDF |
|
16 | J. L. Dou |
A compiler cost model for speculative multithreading chip-multiprocessor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2006 |
RDF |
|
16 | Peter Poplavko, Twan Basten, Milan Pastrnak, Jef L. van Meerbergen, Marco Bekooij, Peter H. N. de With |
Extended abstract: estimation times of on-chip multiprocessor stream-oriented applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 11-14 July 2005, Verona, Italy, Proceedings, pp. 250-251, 2005, IEEE Computer Society, 0-7803-9227-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara |
Multigrain parallel processing on compiler cooperative chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 9th Annual Workshop on Interaction between Compilers and Computer Architectures, INTERACT-9 2005, San Francisco, California, USA, February 13, 2005, pp. 11-20, 2005, IEEE Computer Society, 0-7695-2321-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Tom R. Jacobs, José L. Núñez-Yáñez |
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 405-410, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Satoshi Kaneko, Hiroyuki Kondo, Norio Masui, Koichi Ishimi, Teruyuki Itou, Masayuki Satou, Naoto Okumura, Yukari Takata, Hirokazu Takata, Mamoru Sakugawa, Takashi Higuchi, Sugako Ohtani, Kei Sakamoto, Naoshi Ishikawa, Masami Nakajima, Shunichi Iwata, Kiyoshi Hayase, Satoshi Nakano, Sachiko Nakazawa, Kunihiro Yamada, Toru Shimizu |
A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 39(1), pp. 184-193, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Chao-Chin Wu |
Embedding a superscalar processor onto a chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 28(4), pp. 147-156, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Terry Tao Ye, Luca Benini, Giovanni De Micheli |
Packetization and routing analysis of on-chip multiprocessor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 50(2-3), pp. 81-104, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Bradford M. Beckmann, David A. Wood 0001 |
Managing Wire Delay in Large Chip-Multiprocessor Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, pp. 319-330, 2004, IEEE Computer Society, 0-7695-2126-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Saifeddine Berrayana, Etienne Faure, Daniela Genius, Frédéric Pétrot |
Modular On-chip Multiprocessor for Routing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2004 Parallel Processing, 10th International Euro-Par Conference, Pisa, Italy, August 31-September 3, 2004, Proceedings, pp. 846-855, 2004, Springer, 3-540-22924-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan |
Automatic synthesis of system on chip multiprocessor architectures for process networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 60-65, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
application specific multiprocessors, partitioning, Kahn process networks |
16 | Mirko Loghi, Luca Benini, Massimo Poncino |
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 393-396, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Scott F. Smith 0002 |
Performance of a GALS Single-Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA '04, June 21-24, 2004, Las Vegas, Nevada, USA, Volume 1, pp. 449-454, 2004, CSREA Press, 1-892512-23-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
16 | Yuu Tanaka, Toshinori Sato, Takenori Koushiro |
The potential in energy efficiency of a speculative chip-multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2004: Proceedings of the Sixteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, June 27-30, 2004, Barcelona, Spain, pp. 273-274, 2004, ACM, 1-58113-840-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dual pipeline, energy efficiency, speculative multithreading |
16 | Magnus Ekman |
Strategies to Reduce Energy and Resources in Chip Multiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2004 |
RDF |
|
16 | John Nickolls, L. J. Madar III, Scott Johnson, Viresh Rustagi, Ken Unger, Mustafiz Choudhury |
Calisto: A Low-Power Single-Chip Multiprocessor Communications Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 23(2), pp. 29-43, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
Displaying result #201 - #300 of 503 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ >>] |
|