Search results for "chip-multiprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Shahnawaz Talpur, Feng Shi 0009, Yizhuo Wang	Communication Locality Analysis of Triplet-Based Hierarchical Interconnection Network in Chip Multiprocessor.	NPC	2012	DBLP DOI BibTeX RDF
16	Aparna Mandke Dani, Y. N. Srikant, Bharadwaj Amrutur	Efficient cache exploration method for a tiled chip multiprocessor.	HiPC	2012	DBLP DOI BibTeX RDF
16	Guo Cheng, Luo Chen, Qiu-Yun Wu, Ning Jing	Parallelization Methods for Edge Extraction Applied to Chip Multiprocessor Clusters.	CIT	2012	DBLP DOI BibTeX RDF
16	Shufan Yang, Qiang Wu, Xiongren Xiao, Renfa Li, Dominic Hillenbrand	Fair Access to External Memory for Chip-multiprocessor.	IPDPS Workshops	2012	DBLP DOI BibTeX RDF
16	Mohammad Ghasemazar, Hadi Goudarzi, Massoud Pedram	Robust optimization of a Chip Multiprocessor's performance under power and thermal constraints.	ICCD	2012	DBLP DOI BibTeX RDF
16	Matthew DeVuyst, Ashish Venkat, Dean M. Tullsen	Execution migration in a heterogeneous-ISA chip multiprocessor.	ASPLOS	2012	DBLP DOI BibTeX RDF
16	Pablo Prieto, Valentin Puente, José-Ángel Gregorio	Multilevel Cache Modeling for Chip-Multiprocessor Systems.	IEEE Comput. Archit. Lett.	2011	DBLP DOI BibTeX RDF
16	Fakhar Anjam, Muhammad Faisal Nadeem, Stephan Wong	Targeting code diversity with run-time adjustable issue-slots in a chip multiprocessor.	DATE	2011	DBLP DOI BibTeX RDF
16	Mohammad Ghasemazar, Massoud Pedram	Variation aware dynamic power management for chip multiprocessor architectures.	DATE	2011	DBLP DOI BibTeX RDF
16	Sanghoon Lee 0006, James Tuck 0001	Automatic parallelization of fine-grained meta-functions on a chip multiprocessor.	CGO	2011	DBLP DOI BibTeX RDF
16	Sanghoon Lee 0006, Devesh Tiwari, Yan Solihin, James Tuck 0001	HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor.	HPCA	2011	DBLP DOI BibTeX RDF
16	Malèk Channoufi, Pierre Lecoy, Rabah Attia, Bruno Delacressonniere, S. Garcia	Toward All Optical Interconnections in Chip Multiprocessor (2).	ReConFig	2011	DBLP DOI BibTeX RDF
16	Vassilios A. Chouliaras, George Lentaris, Dionisios I. Reisis, David Stevens	Customizing a VLIW Chip Multiprocessor for Motion Estimation Algorithms.	ARCS Workshops	2011	DBLP BibTeX RDF
16	Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen	Explorations of optimal core and cache placements for Chip Multiprocessor.	NORCHIP	2011	DBLP DOI BibTeX RDF
16	Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen	Optimal memory controller placement for chip multiprocessor.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
16	Jian Wang 0035, Andreas Karlsson, Joar Sohl, Magnus Pettersson, Dake Liu	A multi-level arbitration and topology free streaming network for chip multiprocessor.	ASICON	2011	DBLP DOI BibTeX RDF
16	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	Cache equalizer: a placement mechanism for chip multiprocessor distributed shared caches.	HiPEAC	2011	DBLP DOI BibTeX RDF
16	Limin Han, Deyuan Gao, Xiaoya Fan, Liwen Shi, Jianfeng An	Global Prefetcher Aggressiveness Control for Chip-Multiprocessor.	CIS	2011	DBLP DOI BibTeX RDF
16	Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt	Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
16	Ozcan Ozturk 0001	Improving chip multiprocessor reliability through code replication.	Comput. Electr. Eng.	2010	DBLP DOI BibTeX RDF
16	Fei Guo, Yan Solihin, Li Zhao 0002, Ravishankar R. Iyer 0001	Quality of service shared cache management in chip multiprocessor architecture.	ACM Trans. Archit. Code Optim.	2010	DBLP DOI BibTeX RDF
16	Christof Pitter, Martin Schoeberl	A real-time Java chip-multiprocessor.	ACM Trans. Embed. Comput. Syst.	2010	DBLP DOI BibTeX RDF
16	D. Ramakrishnan, Y. L. Wu, W. B. Jone	Design and Analysis of Location Caches in a NoC-Based Chip Multiprocessor System.	J. Low Power Electron.	2010	DBLP DOI BibTeX RDF
16	Quentin L. Meunier, Frédéric Pétrot, Jean-Louis Roch	Hardware/software support for adaptive work-stealing in on-chip multiprocessor.	J. Syst. Archit.	2010	DBLP DOI BibTeX RDF
16	Long Zheng 0001, Mianxiong Dong, Hai Jin 0001, Minyi Guo, Song Guo 0001, Xuping Tu	The Core Degree Based Tag Reduction on Chip Multiprocessor to Balance Energy Saving and Performance Overhead.	NPC	2010	DBLP DOI BibTeX RDF
16	David Stevens, Vassilios A. Chouliaras	LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support.	ISVLSI	2010	DBLP DOI BibTeX RDF
16	Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen	Operating System Processor Scheduler Design for Future Chip Multiprocessor.	ARCS Workshops	2010	DBLP BibTeX RDF
16	Dan Upton, Kim M. Hazelwood	Design of a custom VEE core in a chip multiprocessor.	SASP	2010	DBLP DOI BibTeX RDF
16	Kunle Olukotun	Chip multiprocessor architecture: A programmability-driven approach.	IPDPS	2010	DBLP DOI BibTeX RDF
16	Konstantinos Krommydas, George Tsoublekas, Christos D. Antonopoulos, Nikolaos Bellas	Mapping and optimization of the AVS video decoder on a high performance chip multiprocessor.	ICME	2010	DBLP DOI BibTeX RDF
16	Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedram	Minimizing energy consumption of a chip multiprocessor through simultaneous core consolidation and DVFS.	ISCAS	2010	DBLP DOI BibTeX RDF
16	Danfeng Zhu, Rui Wang 0014, Hui Wang, Depei Qian, Zhongzhi Luan, Tianshu Chu	A Fair Thread-Aware Memory Scheduling Algorithm for Chip Multiprocessor.	ICA3PP (1)	2010	DBLP DOI BibTeX RDF
16	Jiayin Li, Meikang Qiu, Jianwei Niu 0002, Tianzhou Chen, Yongxin Zhu 0001	Real-Time Constrained Task Scheduling in 3D Chip Multiprocessor to Reduce Peak Temperature.	EUC	2010	DBLP DOI BibTeX RDF
16	Shaobo Liu, Jingyi Zhang, Qing Wu 0002, Qinru Qiu	Thermal-aware job allocation and scheduling for three dimensional chip multiprocessor.	ISQED	2010	DBLP DOI BibTeX RDF
16	Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedram	Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint.	ISQED	2010	DBLP DOI BibTeX RDF
16	Christophe Bobda, Philipp Mahr, Benjamin Andres, Harold Ishebabi	Application-driven architecture synthesis of on-chip Multiprocessor systems.	HPCS	2010	DBLP DOI BibTeX RDF
16	Magnus Jahre, Marius Grannæs, Lasse Natvig	DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems.	HiPEAC	2010	DBLP DOI BibTeX RDF
16	Sebastian Herbert, Diana Marculescu	Mitigating the Impact of Variability on Chip-Multiprocessor Power and Performance.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
16	Gabor Madl, Sudeep Pasricha, Nikil D. Dutt, Sherif Abdelwahed	Cross-abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs.	IEEE Trans. Ind. Informatics	2009	DBLP DOI BibTeX RDF
16	Davy Genbrugge, Lieven Eeckhout	Chip Multiprocessor Design Space Exploration through Statistical Simulation.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
16	Gilbert Hendry, Shoaib Kamil 0001, Aleksandr Biberman, Johnnie Chan, Benjamin G. Lee, Marghoob Mohiyuddin, Ankit Jain, Keren Bergman, Luca P. Carloni, John Kubiatowicz, Leonid Oliker, John Shalf	Analysis of photonic networks for a chip multiprocessor using scientific applications.	NOCS	2009	DBLP DOI BibTeX RDF
16	Taecheol Oh, Hyunjin Lee, Kiyeon Lee, Sangyeun Cho	An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor.	ISVLSI	2009	DBLP DOI BibTeX RDF
16	Shoumeng Yan, Xiaocheng Zhou, Ying Gao, Hu Chen, Sai Luo, Peinan Zhang, Naveen Cherukuri, Ronny Ronen, Bratin Saha	Terascale chip multiprocessor memory hierarchy and programming model.	HiPC	2009	DBLP DOI BibTeX RDF
16	Yue Wu, Lei Xu, Hongbin Yang	Loop Selection to Boost Thread Level Speculation Parallelism in Chip Multiprocessor Systems.	CIT (2)	2009	DBLP DOI BibTeX RDF
16	Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria	Variability-aware robust design space exploration of chip multiprocessor architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
16	Magnus Jahre, Marius Grannæs, Lasse Natvig	A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures.	HPCC	2009	DBLP DOI BibTeX RDF
16	S. Subha	An Algorithm for Parallel Execution of Loops in Chip Multiprocessor Caches.	ARTCom	2009	DBLP DOI BibTeX RDF
16	Shu-Yen Lin, Chan-Cheng Hsu, An-Yeu Wu	A Scalable Built-in Self-test/Self-diagnosis Architecture for 2D-Mesh based Chip Multiprocessor Systems.	ISCAS	2009	DBLP DOI BibTeX RDF
16	Kazuaki Ishizaki, Toshio Nakatani, Shahrokh Daijavad	Analyzing and improving performance scalability of commercial server workloads on a chip multiprocessor.	IISWC	2009	DBLP DOI BibTeX RDF
16	Jin Cui, Douglas L. Maskell	Dynamic thermal-aware scheduling on chip multiprocessor for soft real-time system.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dynamic tas, post thermal map, cmp, soft real-time
16	Andrew Cassidy, Andreas G. Andreou	Analytical methods for the design and optimization of chip-multiprocessor architectures.	CISS	2009	DBLP DOI BibTeX RDF
16	Xin Jin 0003, Alexander D. Rast, Francesco Galluppi, Muhammad Mukaram Khan, Steve B. Furber	Implementing Learning on the SpiNNaker Universal Neural Chip Multiprocessor.	ICONIP (1)	2009	DBLP DOI BibTeX RDF
16	Dietmar Tutsch, Daniel Lüdtke	Chip Multiprocessor Traffic Models Providing Consistent Multicast and Spatial Distributions.	Simul.	2008	DBLP DOI BibTeX RDF
16	Ravi Kiran Karanam, Arun Ravindran, Arindam Mukherjee 0001	A stream chip-multiprocessor for bioinformatics.	SIGARCH Comput. Archit. News	2008	DBLP DOI BibTeX RDF
16	Konstantinos Tatas, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, Stephan Wong	Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs.	Parallel Process. Lett.	2008	DBLP DOI BibTeX RDF
16	Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara	Power-Aware Compiler Controllable Chip Multiprocessor.	IEICE Trans. Electron.	2008	DBLP DOI BibTeX RDF
16	Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Russ Joseph	Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
16	Rui Gong, Kui Dai, Zhiying Wang 0003	Transient Fault Recovery on Chip Multiprocessor based on Dual Core Redundancy and Context Saving.	ICYCS	2008	DBLP DOI BibTeX RDF
16	Christof Pitter, Martin Schoeberl	Performance evaluation of a java chip-multiprocessor.	SIES	2008	DBLP DOI BibTeX RDF
16	Abhishek Bhattacharjee, Gilberto Contreras, Margaret Martonosi	Full-system chip multiprocessor power evaluations using FPGA-based emulation.	ISLPED	2008	DBLP DOI BibTeX RDF
16	Jun Zhang, Xiao-Ya Fan, Song-He Liu	A Pollution Alleviative L2 Cache Replacement Policy for Chip Multiprocessor Architecture.	NAS	2008	DBLP DOI BibTeX RDF
16	Michael Gschwind	Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor.	ICCD	2008	DBLP DOI BibTeX RDF
16	Muhammad Mukaram Khan, David R. Lester, Luis A. Plana, Alexander D. Rast, Xin Jin 0003, Eustace Painkras, Stephen B. Furber	SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor.	IJCNN	2008	DBLP DOI BibTeX RDF
16	Rui Gong, Kui Dai, Zhiying Wang 0003	Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy.	PRDC	2008	DBLP DOI BibTeX RDF
16	Masaaki Kondo, Hiroshi Sasaki 0001, Hiroshi Nakamura	Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS.	SIGARCH Comput. Archit. News	2007	DBLP DOI BibTeX RDF
16	Haakon Dybdahl, Per Stenström, Lasse Natvig	An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches.	SIGARCH Comput. Archit. News	2007	DBLP DOI BibTeX RDF
16	Kyriakos Stavrou, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso	Chip multiprocessor based on data-driven multithreading model.	Int. J. High Perform. Syst. Archit.	2007	DBLP DOI BibTeX RDF
16	Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert 0001	Resource efficiency of the GigaNetIC chip multiprocessor architecture.	J. Syst. Archit.	2007	DBLP DOI BibTeX RDF
16	Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara	Power-Aware Compiler Controllable Chip Multiprocessor.	PACT	2007	DBLP DOI BibTeX RDF
16	Christopher LaFrieda, Engin Ipek, José F. Martínez, Rajit Manohar	Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor.	DSN	2007	DBLP DOI BibTeX RDF
16	Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun	ATLAS: a chip-multiprocessor with transactional memory support.	DATE	2007	DBLP DOI BibTeX RDF
16	Jisheng Zhao, Matthew Horsnell, Ian Rogers, Andrew Dinn, Chris C. Kirkham, Ian Watson	Optimizing Chip Multiprocessor Work Distribution Using Dynamic Compilation.	Euro-Par	2007	DBLP DOI BibTeX RDF	Automatic parallelization, dynamic execution, feedback-directed optimization
16	Étienne Ogoubi, Abdelhakim Hafid, Marcel Turcotte	An Isometric on on-Chip Multiprocessor Architecture.	ICECS	2007	DBLP DOI BibTeX RDF
16	Lei Miao 0002, Yong Qi, Di Hou, Yue-hua Dai	Energy-Aware Scheduling Tasks on Chip Multiprocessor.	ICNC (4)	2007	DBLP DOI BibTeX RDF
16	Mikhail Smelyanskiy, Victor W. Lee, Daehyun Kim 0001, Anthony D. Nguyen, Pradeep Dubey	Scaling performance of interior-point method on large-scale chip multiprocessor system.	SC	2007	DBLP DOI BibTeX RDF
16	Pei Gu, Uzi Vishkin	Case study of gate-level logic simulation on an extremely fine-grained chip multiprocessor.	J. Embed. Comput.	2006	DBLP BibTeX RDF
16	Patrick Anthony La Fratta, James M. Baker Jr.	Exploring power reduction options for a single-chip multiprocessor through system-level modeling.	J. Embed. Comput.	2006	DBLP BibTeX RDF
16	Francisco J. Villa, Manuel E. Acacio, José M. García 0001	On the Evaluation of Dense Chip-Multiprocessor Architectures.	ICSAMOS	2006	DBLP DOI BibTeX RDF
16	Haakon Dybdahl, Per Stenström, Lasse Natvig	An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches.	MEDEA@PACT	2006	DBLP DOI BibTeX RDF
16	Pengyong Ma, Shuming Chen	MID: a Novel Coherency Protocol in Chip Multiprocessor.	CIT	2006	DBLP DOI BibTeX RDF
16	Gregory Buehrer, Yen-Kuang Chen, Srinivasan Parthasarathy 0001, Anthony D. Nguyen, Amol Ghoting, Daehyun Kim 0001	Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
16	David A. Wood 0001	Keynote talk challenges in chip multiprocessor memory systems.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
16	Haixia Wang 0001, Dongsheng Wang 0002, Peng Li 0031	SRC-based Cache Coherence Protocol in Chip Multiprocessor.	FCST	2006	DBLP DOI BibTeX RDF
16	Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Stefanos Kaxiras, Erik Hagersten	Modeling Cache Sharing on Chip Multiprocessor Architectures.	IISWC	2006	DBLP DOI BibTeX RDF
16	Michael Ruogu Zhang	Latency reduction techniques in chip multiprocessor cache systems.		2006	RDF
16	J. L. Dou	A compiler cost model for speculative multithreading chip-multiprocessor architectures.		2006	RDF
16	Peter Poplavko, Twan Basten, Milan Pastrnak, Jef L. van Meerbergen, Marco Bekooij, Peter H. N. de With	Extended abstract: estimation times of on-chip multiprocessor stream-oriented applications.	MEMOCODE	2005	DBLP DOI BibTeX RDF
16	Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara	Multigrain parallel processing on compiler cooperative chip multiprocessor.	Interaction between Compilers and Computer Architectures	2005	DBLP DOI BibTeX RDF
16	Tom R. Jacobs, José L. Núñez-Yáñez	A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor.	ASAP	2005	DBLP DOI BibTeX RDF
16	Satoshi Kaneko, Hiroyuki Kondo, Norio Masui, Koichi Ishimi, Teruyuki Itou, Masayuki Satou, Naoto Okumura, Yukari Takata, Hirokazu Takata, Mamoru Sakugawa, Takashi Higuchi, Sugako Ohtani, Kei Sakamoto, Naoshi Ishikawa, Masami Nakajima, Shunichi Iwata, Kiyoshi Hayase, Satoshi Nakano, Sachiko Nakazawa, Kunihiro Yamada, Toru Shimizu	A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
16	Chao-Chin Wu	Embedding a superscalar processor onto a chip multiprocessor.	Microprocess. Microsystems	2004	DBLP DOI BibTeX RDF
16	Terry Tao Ye, Luca Benini, Giovanni De Micheli	Packetization and routing analysis of on-chip multiprocessor networks.	J. Syst. Archit.	2004	DBLP DOI BibTeX RDF
16	Bradford M. Beckmann, David A. Wood 0001	Managing Wire Delay in Large Chip-Multiprocessor Caches.	MICRO	2004	DBLP DOI BibTeX RDF
16	Saifeddine Berrayana, Etienne Faure, Daniela Genius, Frédéric Pétrot	Modular On-chip Multiprocessor for Routing Applications.	Euro-Par	2004	DBLP DOI BibTeX RDF
16	Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan	Automatic synthesis of system on chip multiprocessor architectures for process networks.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	application specific multiprocessors, partitioning, Kahn process networks
16	Mirko Loghi, Luca Benini, Massimo Poncino	Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor.	ICCD	2004	DBLP DOI BibTeX RDF
16	Scott F. Smith 0002	Performance of a GALS Single-Chip Multiprocessor.	PDPTA	2004	DBLP BibTeX RDF
16	Yuu Tanaka, Toshinori Sato, Takenori Koushiro	The potential in energy efficiency of a speculative chip-multiprocessor.	SPAA	2004	DBLP DOI BibTeX RDF	dual pipeline, energy efficiency, speculative multithreading
16	Magnus Ekman	Strategies to Reduce Energy and Resources in Chip Multiprocessor Systems.		2004	RDF
16	John Nickolls, L. J. Madar III, Scott Johnson, Viresh Rustagi, Ken Unger, Mustafiz Choudhury	Calisto: A Low-Power Single-Chip Multiprocessor Communications Platform.	IEEE Micro	2003	DBLP DOI BibTeX RDF