Search results for "cmps"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Nikita Nikitin, Magnus Jahre	Patterned Heterogeneous CMPs: The Case for Regularity-Driven System-Level Synthesis.	ISVLSI	2014	DBLP DOI BibTeX RDF
19	Marta Ortín, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals	Dynamic construction of circuits for reactive traffic in homogeneous CMPs.	DATE	2014	DBLP DOI BibTeX RDF
19	Hao Shen, Qinru Qiu	Contention aware frequency scaling on CMPs with guaranteed quality of service.	DATE	2014	DBLP DOI BibTeX RDF
19	Paolo Grani	From hybrid electro-photonic to all-optical on-chip interconnections for future CMPs.	HPCS	2014	DBLP DOI BibTeX RDF
19	Paolo Grani, Sandro Bartolini	Simultaneous Optical Path-Setup for Reconfigurable Photonic Networks in Tiled CMPs.	HPCC/CSS/ICESS	2014	DBLP DOI BibTeX RDF
19	Ricardo Fernández Pascual, Alberto Ros 0001, Manuel E. Acacio	Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs.	Euro-Par Workshops (2)	2014	DBLP DOI BibTeX RDF
19	Hanhua Chen, Qiong Hu, Hai Jin 0001	Incremental design of scalable wireless interconnection structure for CMPs.	IWQoS	2014	DBLP DOI BibTeX RDF
19	Mehdi Modarressi, Hamid Sarbazi-Azad	A reconfigurable network-on-chip architecture for heterogeneous CMPs in the dark-silicon era.	ASAP	2014	DBLP DOI BibTeX RDF
19	Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Víctor Viñals	Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages.	SBAC-PAD	2014	DBLP DOI BibTeX RDF
19	Poona Bahrebar, Dirk Stroobandt	Characterizing Traffic Locality in 3D NoC-Based CMPs Using a Path-Based Partitioning Method.	Hot Interconnects	2014	DBLP DOI BibTeX RDF
19	Karthik Swaminathan, Huichu Liu, Jack Sampson, Vijaykrishnan Narayanan	An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs.	ISCA	2014	DBLP DOI BibTeX RDF
19	Hyunhee Kim, Jung Ho Ahn, Jihong Kim 0001	Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
19	Javier Lira, Carlos Molina, Ryan N. Rakvic, Antonio González 0001	Replacement techniques for dynamic NUCA cache designs on CMPs.	J. Supercomput.	2013	DBLP DOI BibTeX RDF
19	Ramon Bertran, Marc González 0001, Xavier Martorell, Nacho Navarro, Eduard Ayguadé	A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs.	IEEE Trans. Computers	2013	DBLP DOI BibTeX RDF
19	José L. Abellán, Juan Fernández 0001, Manuel E. Acacio	Design of an efficient communication infrastructure for highly contended locks in many-core CMPs.	J. Parallel Distributed Comput.	2013	DBLP DOI BibTeX RDF
19	Yong Li 0009, Rami G. Melhem, Alex K. Jones	PS-TLB: Leveraging page classification information for fast, scalable and efficient translation for future CMPs.	ACM Trans. Archit. Code Optim.	2013	DBLP DOI BibTeX RDF
19	Guangyu Sun 0003, Eren Kursun, Jude A. Rivers, Yuan Xie 0001	Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory.	ACM J. Emerg. Technol. Comput. Syst.	2013	DBLP DOI BibTeX RDF
19	Mehdi Modarressi, Marjan Asadinia, Hamid Sarbazi-Azad	Using task migration to improve non-contiguous processor allocation in NoC-based CMPs.	J. Syst. Archit.	2013	DBLP DOI BibTeX RDF
19	José L. Abellán, Alberto Ros 0001, Juan Fernández Peinador, Manuel E. Acacio	ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs.	ICSAMOS	2013	DBLP DOI BibTeX RDF
19	Pablo Abad Fidalgo, Pablo Prieto, Lucia G. Menezo, Adrian Colaso, Valentin Puente, José-Ángel Gregorio	Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs.	DSD	2013	DBLP DOI BibTeX RDF
19	Luka B. Daoud, Victor Goulart	High Performance Bitwise OR Based Submesh Allocation for 2D Mesh-Connected CMPs.	DSD	2013	DBLP DOI BibTeX RDF
19	Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang 0020, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano	A case for wireless 3D NoCs for CMPs.	ASP-DAC	2013	DBLP DOI BibTeX RDF
19	Abbas BanaiyanMofrad, Houam Homayoun, Vasileios Kontorinis, Dean M. Tullsen, Nikil D. Dutt	REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs.	IGCC	2013	DBLP DOI BibTeX RDF
19	José L. Abellán, Alberto Ros 0001, Juan Fernández 0001, Manuel E. Acacio	Efficient Dir0B Cache Coherency for Many-Core CMPs.	ICCS	2013	DBLP DOI BibTeX RDF
19	Ahmad Samih, Xiaowei Jiang, Liang Han, Yan Solihin	Flexible Capacity Partitioning in Many-Core Tiled CMPs.	CCGRID	2013	DBLP DOI BibTeX RDF
19	Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu	Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs.	ISLPED	2013	DBLP DOI BibTeX RDF
19	Yu-Ting Chen, Jason Cong, Mohammad Ali Ghodrat, Muhuan Huang, Chunyue Liu, Bingjun Xiao, Yi Zou	Accelerator-rich CMPs: From concept to real hardware.	ICCD	2013	DBLP DOI BibTeX RDF
19	Fang Zheng, Chitra Venkatramani, Rohit Wagle, Karsten Schwan	Cache Topology Aware Mapping of Stream Processing Applications onto CMPs.	ICDCS	2013	DBLP DOI BibTeX RDF
19	Mamata Dalui, Biplab K. Sikdar	Design of directory based cache coherence protocol verification logic in CMPs around TACA.	HPCS	2013	DBLP DOI BibTeX RDF
19	Marta Ortín, Alexandra Ferreron, Jorge Albericio, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals	Characterization and cost-efficient selection of NoC topologies for general purpose CMPs.	INA-OCMC@HiPEAC	2013	DBLP DOI BibTeX RDF
19	John Carpenter, Rami G. Melhem	Deterministic Multiplexing of NoC on Grid CMPs.	Hot Interconnects	2013	DBLP DOI BibTeX RDF
19	José A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt	Utility-based acceleration of multithreaded applications on asymmetric CMPs.	ISCA	2013	DBLP DOI BibTeX RDF
19	Sandro Bartolini, Paolo Grani	Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs.	MES	2013	DBLP DOI BibTeX RDF
19	Mamata Dalui, Keshav Gupta, Biplab K. Sikdar	Directory based cache coherence verification logic in CMPs cache system.	MES	2013	DBLP DOI BibTeX RDF
19	Fei Hong, Aviral Shrivastava, Jongeun Lee	Return Data Interleaving for Multi-Channel Embedded CMPs Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
19	Daniel Sánchez 0004, Juan L. Aragón, José M. García 0001	A fault-tolerant architecture for parallel applications in tiled-CMPs.	J. Supercomput.	2012	DBLP DOI BibTeX RDF
19	Stamatis G. Kavadias, Manolis Katevenis, Michail Zampetakis, Dimitrios S. Nikolopoulos	Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs.	Int. J. Parallel Program.	2012	DBLP DOI BibTeX RDF
19	José L. Abellán, Juan Fernández 0001, Manuel E. Acacio	Efficient Hardware Barrier Synchronization in Many-Core CMPs.	IEEE Trans. Parallel Distributed Syst.	2012	DBLP DOI BibTeX RDF
19	Guangyu Sun 0003, Huazhong Yang, Yuan Xie 0001	Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
19	Kai Ma, Xiaorui Wang	PGCapping: exploiting power gating for power capping and core lifetime balancing in CMPs.	PACT	2012	DBLP DOI BibTeX RDF
19	Karthik T. Sundararajan, Timothy M. Jones 0001, Nigel P. Topham	Energy-efficient cache partitioning for future CMPs.	PACT	2012	DBLP DOI BibTeX RDF
19	Yong Li 0009, Rami G. Melhem, Alex K. Jones	Practically private: enabling high performance CMPs through compiler-assisted data classification.	PACT	2012	DBLP DOI BibTeX RDF
19	Francisco Triviño, José L. Sánchez 0002, Francisco José Alfaro, José Flich	Exploring NoC Virtualization Alternatives in CMPs.	PDP	2012	DBLP DOI BibTeX RDF
19	Sandro Bartolini, Paolo Grani	A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs.	DSD	2012	DBLP DOI BibTeX RDF
19	Karthik T. Sundararajan, Vasileios Porpodas, Timothy M. Jones 0001, Nigel P. Topham, Björn Franke	Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs.	HPCA	2012	DBLP DOI BibTeX RDF
19	Jinglei Wang, Dongsheng Wang 0002, Haixia Wang 0001, Yibo Xue	Dynamic reusability-based replication with network address mapping in CMPs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
19	Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	A multi-Vdd dynamic variable-pipeline on-chip router for CMPs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
19	Josué Feliu, Julio Sahuquillo, Salvador Petit, José Duato	Understanding Cache Hierarchy Contention in CMPs to Improve Job Scheduling.	IPDPS	2012	DBLP DOI BibTeX RDF
19	Jingtong Hu, Qingfeng Zhuge, Chun Jason Xue, Wei-Che Tseng, Edwin Hsing-Mean Sha	Optimizing Data Allocation and Memory Configuration for Non-Volatile Memory Based Hybrid SPM on Embedded CMPs.	IPDPS Workshops	2012	DBLP DOI BibTeX RDF
19	Abbas BanaiyanMofrad, Gustavo Girão, Nikil D. Dutt	A novel NoC-based design for fault-tolerance of last-level caches in CMPs.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
19	Ankit More, Baris Taskin	A locality-aware bi-level mesh-mesh 2d-noc architecture for future thousand core CMPs.	SLIP	2012	DBLP DOI BibTeX RDF
19	Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Chunyue Liu, Glenn Reinman	BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs.	ISLPED	2012	DBLP DOI BibTeX RDF
19	Da Cheng, Sandeep K. Gupta 0001	A systematic methodology to improve yield per area of highly-parallel CMPs.	DFT	2012	DBLP DOI BibTeX RDF
19	Alberto Ros 0001, Ricardo Fernández Pascual, Manuel E. Acacio	Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs.	SBAC-PAD	2012	DBLP DOI BibTeX RDF
19	Mamata Dalui, Biplab K. Sikdar	An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol.	VDAT	2012	DBLP DOI BibTeX RDF
19	Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie 0001, Vijaykrishnan Narayanan, Ravishankar R. Iyer 0001, Chita R. Das	Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs.	DAC	2012	DBLP DOI BibTeX RDF
19	Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman	Architecture support for accelerator-rich CMPs.	DAC	2012	DBLP DOI BibTeX RDF
19	Abbas BanaiyanMofrad	Reliable On-Chip Memory Design for CMPs.	SRDS	2012	DBLP DOI BibTeX RDF
19	Xiaomin Jia, Jiang Jiang, Yongwen Wang, Shubo Qi, Tianlei Zhao, Guitao Fu, Minxuan Zhang	BP-NUCA: Cache Pressure-Aware Migration for High-Performance Caching in CMPs.	Comput. Informatics	2011	DBLP BibTeX RDF
19	Isao Kotera, Kenta Abe, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi	Power-Aware Dynamic Cache Partitioning for CMPs.	Trans. High Perform. Embed. Archit. Compil.	2011	DBLP DOI BibTeX RDF
19	Junli Gu, Yihe Sun, Steven S. Lumetta, Rakesh Kumar 0002	MOPED: Accelerating Data Communication on Future CMPs.	IEEE Micro	2011	DBLP DOI BibTeX RDF	data communication, Multicore architecture, cache hierarchy
19	Christian Fensch, Marcelo Cintra	An Evaluation of an OS-Based Coherence Scheme for Tiled CMPs.	Int. J. Parallel Program.	2011	DBLP DOI BibTeX RDF
19	Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke	StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
19	Carles Hernández 0001, Antoni Roca 0001, José Flich, Federico Silla, José Duato	Characterizing the impact of process variation on 45 nm NoC-based CMPs.	J. Parallel Distributed Comput.	2011	DBLP DOI BibTeX RDF
19	Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería	Filtering directory lookups in CMPs.	Microprocess. Microsystems	2011	DBLP DOI BibTeX RDF
19	Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
19	Daniel Sánchez 0003, Christos Kozyrakis	A few ways can take you a long way: Efficient and highly associative caches with scalable partitioning for many-core CMPs.	Hot Chips Symposium	2011	DBLP DOI BibTeX RDF
19	Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano	A vertical bubble flow network using inductive-coupling for 3-D CMPs.	NOCS	2011	DBLP DOI BibTeX RDF
19	Jianhua Li 0003, Chun Jason Xue, Yinlong Xu	STT-RAM based energy-efficiency hybrid cache for CMPs.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
19	Marjan Asadinia, Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad	Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links.	DATE	2011	DBLP DOI BibTeX RDF
19	Alessandro Bardine, Pierfrancesco Foglia, Francesco Panicucci, Marco Solinas, Julio Sahuquillo	Energy Behaviour of NUCA Caches in CMPs.	DSD	2011	DBLP DOI BibTeX RDF
19	Luka B. Daoud, Mohamed El-Sayed Ragab, Victor Goulart	Faster Processor Allocation Algorithms for Mesh-Connected CMPs.	DSD	2011	DBLP DOI BibTeX RDF
19	Xiaowei Jiang, Asit K. Mishra, Li Zhao 0002, Ravishankar R. Iyer 0001, Zhen Fang, Sadagopan Srinivasan, Srihari Makineni, Paul Brett, Chita R. Das	ACCESS: Smart scheduling for asymmetric cache CMPs.	HPCA	2011	DBLP DOI BibTeX RDF
19	Junli Gu, Steven S. Lumetta, Rakesh Kumar 0002, Yihe Sun	MOPED: Orchestrating interprocess message data on CMPs.	HPCA	2011	DBLP DOI BibTeX RDF
19	Jinglei Wang, Dongsheng Wang 0002, Haixia Wang 0001, Yibo Xue	High performance cache block replication using re-reference probability in CMPs.	HiPC	2011	DBLP DOI BibTeX RDF
19	Andrea Pellegrini, Valeria Bertacco	Cardio: Adaptive CMPs for reliability through dynamic introspective operation.	HLDVT	2011	DBLP DOI BibTeX RDF
19	Young-Sik Eom, Seong Tae Jhang, Chu-Shik Jhon	Throttling capacity sharing in private L2 caches of CMPs.	RACS	2011	DBLP DOI BibTeX RDF
19	Ana Bosque, Víctor Viñals, Pablo Ibáñez, José María Llabería	Filtering Directory Lookups in CMPs with Write-Through Caches.	Euro-Par (1)	2011	DBLP DOI BibTeX RDF
19	Juan M. Cebrian, Juan L. Aragón, Stefanos Kaxiras	Token3D: Reducing Temperature in 3D Die-Stacked CMPs through Cycle-Level Power Control Mechanisms.	Euro-Par (1)	2011	DBLP DOI BibTeX RDF
19	Sadagopan Srinivasan, Ravishankar R. Iyer 0001, Li Zhao 0002, Ramesh Illikkal	HeteroScouts: hardware assist for OS scheduling in heterogeneous CMPs.	SIGMETRICS	2011	DBLP DOI BibTeX RDF
19	José L. Abellán, Juan Fernández 0001, Manuel E. Acacio	GLocks: Efficient Support for Highly-Contended Locks in Many-Core CMPs.	IPDPS	2011	DBLP DOI BibTeX RDF
19	Juan M. Cebrian, Juan L. Aragón, Stefanos Kaxiras	Power Token Balancing: Adapting CMPs to Power Constraints for Parallel Multithreaded Workloads.	IPDPS	2011	DBLP DOI BibTeX RDF
19	Zhen Fang, Li Zhao 0002, Ravishankar R. Iyer 0001, Carlos Flores Fajardo, German Fabila Garcia, Seung Eun Lee, Bin Li 0018, Steve R. King, Xiaowei Jiang, Srihari Makineni	Cost-effectively offering private buffers in SoCs and CMPs.	ICS	2011	DBLP DOI BibTeX RDF
19	Yi Xu, Yu Du, Youtao Zhang, Jun Yang 0002	A composite and scalable cache coherence protocol for large scale CMPs.	ICS	2011	DBLP DOI BibTeX RDF
19	Zhimin Gu, Yinxia Fu, Ninghan Zheng, Jianxun Zhang, Min Cai, Yan Huang 0011, Jie Tang 0003	Improving Performance of the Irregular Data Intensive Application with Small Computation Workload for CMPs.	ICPP Workshops	2011	DBLP DOI BibTeX RDF	CMP, Helper thread, Irregular computing
19	Guangyu Sun 0003, Eren Kursun, Jude A. Rivers, Yuan Xie 0001	Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory.	ICCD	2011	DBLP DOI BibTeX RDF
19	Rance Rodrigues, Israel Koren, Sandip Kundu	An Architecture to Enable Life Cycle Testing in CMPs.	DFT	2011	DBLP DOI BibTeX RDF
19	Carles Hernández 0001, Federico Silla, José Duato	Energy and Performance Efficient Thread Mapping in NoC-Based CMPs under Process Variations.	ICPP	2011	DBLP DOI BibTeX RDF
19	Lluc Alvarez, Ramon Bertran, Marc González 0001, Xavier Martorell, Nacho Navarro, Eduard Ayguadé	Design space exploration for aggressive core replication schemes in CMPs.	HPDC	2011	DBLP DOI BibTeX RDF
19	Mamata Dalui, Biplab K. Sikdar	An Efficient Test Design for Verification of Cache Coherence in CMPs.	DASC	2011	DBLP DOI BibTeX RDF
19	Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das	A case for heterogeneous on-chip interconnects for CMPs.	ISCA	2011	DBLP DOI BibTeX RDF
19	Asit K. Mishra, Xiangyu Dong, Guangyu Sun 0003, Yuan Xie 0001, Narayanan Vijaykrishnan, Chita R. Das	Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.	ISCA	2011	DBLP DOI BibTeX RDF
19	Xiaomin Jia, Pingjing Lu, Caixia Sun, Minxuan Zhang	Dynamic Program Behavior Identification for High Performance CMPs with Private LLCs.	IEICE Trans. Inf. Syst.	2010	DBLP DOI BibTeX RDF
19	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Tiled chip multiprocessor, heterogeneous on-chip interconnection network, cache coherence protocol, energy-efficient architectures, parallel scientific applications
19	Ricardo Fernández Pascual, José M. García 0001, Manuel E. Acacio, José Duato	Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level.	IEEE Trans. Parallel Distributed Syst.	2010	DBLP DOI BibTeX RDF	fault tolerance, interconnection network, cache coherence, transient faults
19	Antonio Flores, Manuel E. Acacio, Juan L. Aragón	Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs.	J. Syst. Archit.	2010	DBLP DOI BibTeX RDF
19	Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.	NOCS	2010	DBLP DOI BibTeX RDF	low power, Network-on-Chip, router, power gating
19	Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex Ramírez	Interleaving granularity on high bandwidth memory architecture for CMPs.	ICSAMOS	2010	DBLP DOI BibTeX RDF
19	Kamil Kedzierski, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero	Power and performance aware reconfigurable cache for CMPs.	IFMT	2010	DBLP DOI BibTeX RDF
19	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects.	PDP	2010	DBLP DOI BibTeX RDF	tiled chip-multiprocessor, heterogeneous on-chip interconnection network, prefetching, energy-efficient architectures, parallel scientific applications