Search results for "coprocessors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Martijn J. Rutten, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Egbert G. T. Jaspers, Evert-Jan D. Pol	Application design trajectory towards reusable coprocessors MPEG case study.	ESTIMedia	2004	DBLP DOI BibTeX RDF
21	Raj Krishnamurthy, Karsten Schwan, Richard West, Marcel-Catalin Rosu	On Network CoProcessors for Scalable, Predictable Media Services.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	Cluster machines, quality of service, real-time systems, embedded systems, operating systems, data streaming, packet scheduling, multimedia services
21	Vassilios A. Chouliaras, José L. Núñez-Yáñez	Scalar coprocessors for accelerating the G723.1 and G729A speech coders.	IEEE Trans. Consumer Electron.	2003	DBLP DOI BibTeX RDF
21	Binu K. Mathew, Al Davis, Ali Ibrahim	Perception Coprocessors for Embedded Systems.	ESTIMedia	2003	DBLP BibTeX RDF
21	Andrew Morton, Wayne M. Loucks	Real-Time Kernel Support for Coprocessors: Empirical Study of an SoPC.	Embedded Systems and Applications	2003	DBLP BibTeX RDF
21	Hao Che, Yong Wang, Zhijun Wang 0001	A rule grouping technique for weight-based TCAM coprocessors [packet classification application].	Hot Interconnects	2003	DBLP DOI BibTeX RDF
21	Sean W. Smith	Outbound Authentication for Programmable Secure Coprocessors.	ESORICS	2002	DBLP DOI BibTeX RDF
21	Sean W. Smith, David Safford	Practical server privacy with secure coprocessors.	IBM Syst. J.	2001	DBLP DOI BibTeX RDF
21	Adam D. Woodbury, Daniel V. Bailey, Christof Paar	Elliptic Curve Cryptography on Smart Cards without Coprocessors.	CARDIS	2000	DBLP BibTeX RDF
21	Harald Simmler, L. Levinson, Reinhard Männer	Multitasking on FPGA Coprocessors.	FPL	2000	DBLP DOI BibTeX RDF
21	Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey	A Reliable LZ Data Compressor on Reconfigurable Coprocessors.	FCCM	2000	DBLP DOI BibTeX RDF
21	Yuan C. Chou, John Paul Shen	Instruction path coprocessors.	ISCA	2000	DBLP DOI BibTeX RDF
21	Chris J. Scheiman, Klaus E. Schauser	Evaluating the Benefits of Communication Coprocessors.	J. Parallel Distributed Comput.	1999	DBLP DOI BibTeX RDF
21	María Dolores Valdés, María José Moure, Enrique Mandado, Angel Salaverría	An Alternative Solution for Reconfigurable Coprocessors Hardware and Interface Synthesis.	FPL	1999	DBLP DOI BibTeX RDF
21	Scott Hauck	Configuration Prefetch for Single Context Reconfigurable Coprocessors.	FPGA	1998	DBLP DOI BibTeX RDF
21	Sean W. Smith, Vernon Austel	Trusting Trusted Hardware: Towards a Formal Model for Programmable Secure Coprocessors.	USENIX Workshop on Electronic Commerce	1998	DBLP BibTeX RDF
21	Helena Handschuh, Pascal Paillier	Smart Card Crypto-Coprocessors for Public-Key Cryptography.	CARDIS	1998	DBLP DOI BibTeX RDF
21	Hagen Ploog, Dirk Timmermann	FPGA-Based Architecture Evaluation of Cryptographic Coprocessors for Smartcards.	FCCM	1998	DBLP DOI BibTeX RDF
21	J. G. Guimarães, Alexandre R. S. Romariz, P. U. A. Ferreira, J. V. Campêlo Jr., Marcio L. Graciano Jr., O. R. Maia Jr., J. Zancanaro, José C. da Costa	A Signal Processing System based upon Monolithic Neural Coprocessors.	SBRN	1998	DBLP DOI BibTeX RDF
21	Alain Pegatoquet, Michel Auguin, Emmanuel Gresset	Improving "performance vs silicon size" tradeoffs using coprocessors: A case study: G.721 on OAK and Pine DSP Cores.	EUSIPCO	1998	DBLP BibTeX RDF
21	A. König	Towards Actual Neural Coprocessors for Heterogeneous Embedded Systems.	ICONIP (1)	1997	DBLP BibTeX RDF
21	Michael J. Schulte, Earl E. Swartzlander Jr.	Variable-precision, interval arithmetic coprocessors.	Reliab. Comput.	1996	DBLP DOI BibTeX RDF
21	Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke	On the viability of FPGA-based integrated coprocessors.	FCCM	1996	DBLP DOI BibTeX RDF
21	Bennet Yee	Secure Coprocessors in Electronic Commerce Applications.	USENIX Workshop on Electronic Commerce	1995	DBLP BibTeX RDF
21	Jyh-Jong Tsay	An Efficient Implemention of Priority Queues Using Fixed-Sized Systolic Coprocessors.	Inf. Process. Lett.	1993	DBLP DOI BibTeX RDF
21	Albert Pierce, Elizabeth Pierce	The application of Forth engines as coprocessors for the Macintosh computer.	FORTH	1991	DBLP DOI BibTeX RDF
21	Thierry Court	Conception d'une famille de coprocesseurs parallèles intégrées pour le traitement d'images. (Design of a range of parallel integrated coprocessors for image processing).		1991	RDF
21	Mark Birman, Allen Samuels, George Chu, Ting Chuk, Larry Hu, John McLeod, John Barnes	Developing the WTL3170/3171 Sparc floating-point coprocessors.	IEEE Micro	1990	DBLP DOI BibTeX RDF
21	Heinrich Müller	Sorting Numbers Using Limited Systolic Coprocessors.	Inf. Process. Lett.	1987	DBLP DOI BibTeX RDF
12	Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume	Bipartite modular multiplication with twice the bit-length of multipliers.	Int. J. Inf. Sec.	2009	DBLP DOI BibTeX RDF	Bipartite modular multiplication, Double-size technique, RSA, Smartcard, Montgomery multiplication, Modular multiplication
12	Christian Böhm 0001, Robert Noll, Claudia Plant, Bianca Wackersreuther, Andrew Zherdin	Data Mining Using Graphics Processing Units.	Trans. Large Scale Data Knowl. Centered Syst.	2009	DBLP DOI BibTeX RDF
12	Christian Böhm 0001, Robert Noll, Claudia Plant, Bianca Wackersreuther	Density-based clustering using graphics processors.	CIKM	2009	DBLP DOI BibTeX RDF	data mining, performance
12	Jason Cong, Karthik Gururaj, Guoling Han	Synthesis of reconfigurable high-performance multicore systems.	FPGA	2009	DBLP DOI BibTeX RDF	coprocessor synthesis, reconfigurable high-performance computing, design space exploration
12	Peter Djalaliev, José Carlos Brustoloni	Secure web-based retrieval of documents with usage controls.	SAC	2009	DBLP DOI BibTeX RDF	trusted platform module (TPM), digital rights management (DRM)
12	Hari Kannan	Ordering decoupled metadata accesses in multiprocessors.	MICRO	2009	DBLP DOI BibTeX RDF
12	Juan Gómez-Luna, José María González-Linares, José I. Benavides, Nicolás Guil	Parallelization of a Video Segmentation Algorithm on CUDA-Enabled Graphics Processing Units.	Euro-Par	2009	DBLP DOI BibTeX RDF	Canny, CUDA, Video Segmentation, Generalized Hough Transform
12	Cédric Augonnet, Samuel Thibault, Raymond Namyst, Pierre-André Wacrenier	StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures.	Euro-Par	2009	DBLP DOI BibTeX RDF
12	Pedro C. Diniz, Ben H. H. Juurlink, Alain Darte, Wolfgang Karl	Introduction.	Euro-Par	2009	DBLP DOI BibTeX RDF
12	Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez	Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers.	CHES	2009	DBLP DOI BibTeX RDF	Karatsuba-Ofman multiplier, FPGA, elliptic curve, hardware accelerator, Tate pairing, finite field arithmetic, ? T pairing
12	David Slogsnat, Alexander Giese, Mondrian Nüssle, Ulrich Brüning 0001	An open-source HyperTransport core.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	HTX, HyperTransport, FPGA, prototyping, RTL
12	Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung	Outer Loop Pipelining for Application Specific Datapaths in FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
12	Tarek A. El-Ghazawi, Esam El-Araby, Miaoqing Huang, Kris Gaj, Volodymyr V. Kindratenko, Duncan A. Buell	The Promise of High-Performance Reconfigurable Computing.	Computer	2008	DBLP DOI BibTeX RDF	HPRC systems, field-programmable gate arrays, high-performance computing, reconfigurable computing
12	Sung Dae Kim, Myung Hoon Sunwoo	ASIP Approach for Implementation of H.264/AVC.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	low power design, H.264/AVC, hardware accelerator, application specific instruction-set processor, data reuse, hardware software codesign
12	Claudio Mucci, Luca Vanzolini, Ilario Mirimin, Daniele Gazzola, Antonio Deledda, Sebastian Goller, Joachim Knäblein, Axel Schneider, Luca Ciccarelli, Fabio Campi	Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array.	DATE	2008	DBLP DOI BibTeX RDF
12	Ronghua Lu, Jun Han 0003, Xiaoyang Zeng, Qing Li, Lang Mai, Jia Zhao	A low-cost cryptographic processor for security embedded system.	ASP-DAC	2008	DBLP DOI BibTeX RDF
12	Sebastian Rohde, Thomas Eisenbarth 0001, Erik Dahmen, Johannes Buchmann 0001, Christof Paar	Fast Hash-Based Signatures on Constrained Devices.	CARDIS	2008	DBLP DOI BibTeX RDF	hash based cryptography, Merkle signature scheme, digital signatures, Embedded security
12	Cédric Augonnet, Raymond Namyst	A Unified Runtime System for Heterogeneous Multi-core Architectures.	Euro-Par Workshops	2008	DBLP DOI BibTeX RDF
12	Koen De Bosschere, Ayal Zaks, Michael C. Huang 0001, Luis Piñuel	Topic 4: High Performance Architectures and Compilers.	Euro-Par	2008	DBLP DOI BibTeX RDF
12	Shan Shan Huang, Amir Hormati, David F. Bacon, Rodric M. Rabbah	Liquid Metal: Object-Oriented Programming Across the Hardware/Software Boundary.	ECOOP	2008	DBLP DOI BibTeX RDF
12	Ana Balevic, Lars Rockstroh, Andreas Tausendfreund, Stefan Patzelt, Gert Goch, Sven Simon 0001	Accelerating Simulations of Light Scattering Based on Finite-Difference Time-Domain Method with General Purpose GPUs.	CSE	2008	DBLP DOI BibTeX RDF	Simulations, Parallel Programming, GPGPU, CUDA, HPC, Light Scattering, FDTD
12	Chen Huang 0005, Frank Vahid	Dynamic coprocessor management for FPGA-enhanced compute platforms.	CASES	2008	DBLP DOI BibTeX RDF	coprocessing, online algorithms., FPGAs, dynamic optimization, acceleration, runtime configuration
12	Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli	ADAPTO: full-adder based reconfigurable architecture for bit level operations.	ISCAS	2008	DBLP DOI BibTeX RDF
12	Shane Ryoo, Christopher I. Rodrigues, Sara S. Baghsorkhi, Sam S. Stone, David Blair Kirk, Wen-mei W. Hwu	Optimization principles and application performance evaluation of a multithreaded GPU using CUDA.	PPoPP	2008	DBLP DOI BibTeX RDF	parallel computing, GPU computing
12	Chen-Yong Cher, Michael Gschwind	Cell GC: using the cell synergistic processor as a garbage collection coprocessor.	VEE	2008	DBLP DOI BibTeX RDF	BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep
12	Iván González 0004, Estanislao Aguayo, Sergio López-Buedo	Self-Reconfigurable Embedded Systems on Low-Cost FPGAs.	IEEE Micro	2007	DBLP DOI BibTeX RDF	reconfigurable hardware, real-time and embedded systems, special-purpose and application-based systems, algorithms implemented in hardware
12	Najwa Aaraj, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
12	Konrad Slind, Scott Owens, Juliano Iyoda, Mike Gordon	Proof producing synthesis of arithmetic and cryptographic hardware.	Formal Aspects Comput.	2007	DBLP DOI BibTeX RDF	Cryptography, Compiling, Theorem proving, Hardware synthesis, High assurance
12	Nele Mentens, Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications.	ICSAMOS	2007	DBLP DOI BibTeX RDF
12	David Slogsnat, Alexander Giese, Ulrich Brüning 0001	A versatile, low latency HyperTransport core.	FPGA	2007	DBLP DOI BibTeX RDF	HTX, HyperTransport, FPGA, prototyping, RTL
12	Christian Sauer 0001, Matthias Gries, Sebastian Dirk	Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform.	DATE	2007	DBLP DOI BibTeX RDF
12	Christopher Lynch, Hani Hagras, Victor Callaghan	Parallel Type-2 Fuzzy Logic Co-Processors for Engine Management.	FUZZ-IEEE	2007	DBLP DOI BibTeX RDF
12	Jay E. Steele, Robert Cochran	Introduction to GPU programming.	ACM Southeast Regional Conference	2007	DBLP DOI BibTeX RDF
12	Heiner Giefers, Marco Platzner	A Many-core Implementation based on the Reconfigurable Mesh Model.	FPL	2007	DBLP DOI BibTeX RDF
12	Jiri Kadlec, Roman Bartosinski, Martin Danek	Accelerating Microblaze Floating Point Operations.	FPL	2007	DBLP DOI BibTeX RDF
12	Michael F. P. O'Boyle, François Bodin, José González, Lucian N. Vintan	Topic 4 High-Performance Architectures and Compilers.	Euro-Par	2007	DBLP DOI BibTeX RDF
12	Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume	Double-Size Bipartite Modular Multiplication.	ACISP	2007	DBLP DOI BibTeX RDF	bipartite modular multiplication, double-size technique, RSA, smartcard, crypto-coprocessor
12	Ahmed Sherif Zekri, Stanislav G. Sedukhin	Performance Evaluation of Basic Linear Algebra Subroutines on a Matrix Co-processor.	PPAM	2007	DBLP DOI BibTeX RDF
12	Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede	Efficient pipelining for modular multiplication architectures in prime fields.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	public key coprocessor, FPGA, cryptography, montgomery multiplication
12	Bryan P. Bergeron	Physics-Based Animation for Qualitative Assessment of Biomimetic Subterranean Burrowing Behaviors.	CIRA	2007	DBLP DOI BibTeX RDF
12	Miguel A. Vega-Rodríguez, Juan Antonio Gómez Pulido, Juan Manuel Sánchez-Pérez, José M. Granado Criado, Manuel Rubio del Solar	Reconfigurable Computing and Parallelism for Implementing and Accelerating Evolutionary Algorithms.	Parallel Evolutionary Computations	2006	DBLP DOI BibTeX RDF
12	Carsten Albrecht, Jürgen Foag, Roman Koch, Erik Maehle	DynaCORE - A Dynamically Reconfigurable Coprocessor Architecture for Network Processors.	PDP	2006	DBLP DOI BibTeX RDF
12	Rakesh Agrawal 0001, Dmitri Asonov, Murat Kantarcioglu, Yaping Li	Sovereign Joins.	ICDE	2006	DBLP DOI BibTeX RDF
12	Götz Kappen, Tobias G. Noll	Application specific instruction processor based implementation of a GNSS receiver on an FPGA.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
12	Christophe Cassagnabère, François Rousselle, Christophe Renaud	CPU-GPU Multithreaded Programming Model: Application to the Path Tracing with Next Event Estimation Algorithm.	ISVC (2)	2006	DBLP DOI BibTeX RDF
12	Arnaud Lagger, Andres Upegui, Eduardo Sanchez, Iván González	Self-Reconfigurable Pervasive Platform for Cryptographic Application.	FPL	2006	DBLP DOI BibTeX RDF
12	William Jalby, Oscar G. Plata, Barbara M. Chapman, Paul H. J. Kelly	Topic 4: Compilers for High Performance.	Euro-Par	2006	DBLP DOI BibTeX RDF
12	Reiner W. Hartenstein	RAW keynote 2: new horizons of very high performance computing (VHPC): hurdles and chances.	IPDPS	2006	DBLP DOI BibTeX RDF
12	Mohamed Taher, Tarek A. El-Ghazawi	Exploiting processing locality through paging configurations in multitasked reconfigurable systems.	IPDPS	2006	DBLP DOI BibTeX RDF
12	Christopher Kachris, Stamatis Vassiliadis	Analysis of a reconfigurable network processor.	IPDPS	2006	DBLP DOI BibTeX RDF
12	Guido Bertoni, Luca Breveglieri, Matteo Venturi	Power Aware Design of an Elliptic Curve Coprocessor for 8 bit Platforms.	PerCom Workshops	2006	DBLP DOI BibTeX RDF
12	Jun-Cheol Jeon, Kee-Won Kim, Jai-Boo Oh, Kee-Young Yoo	Modular Divider for Elliptic Curve Cryptographic Hardware Based on Programmable CA.	International Conference on Computational Science (4)	2006	DBLP DOI BibTeX RDF
12	Jun-Cheol Jeon, Kee-Won Kim, Byung-Heon Kang, Kee-Young Yoo	Cellular Automata Architecture for Elliptic Curve Cryptographic Hardware.	International Conference on Computational Science (3)	2006	DBLP DOI BibTeX RDF
12	Tim Barrett, Sumit D. Mediratta, Taek-Jun Kwon, Ravinder Singh, Sachit Chandra, Jeff Sondeen, Jeffrey T. Draper	A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Guerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat	Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards.	ASAP	2006	DBLP DOI BibTeX RDF
12	Peter R. Cappello	Multicore processors as Array Processors: Research Opportunities.	ASAP	2006	DBLP DOI BibTeX RDF
12	John L. Gustafson	Innovative technologies II - Acceleration technologies: understanding the differences and assessing what's right for you.	SC	2006	DBLP DOI BibTeX RDF
12	John Patrick McGregor, Ruby B. Lee	Protecting cryptographic keys and computations via virtual secure coprocessing.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
12	David Geer	Taking the Graphics Processor beyond Graphics.	Computer	2005	DBLP DOI BibTeX RDF	graphics chips, graphics processing units, GPUs, GPGPUs, streaming processors
12	Nathan Clark, Hongtao Zhong, Scott A. Mahlke	Automated Custom Instruction Generation for Domain-Specific Processor Acceleration.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	instruction set interpretation, special-purpose, Automatic synthesis, special-purpose and application-based systems, instruction set design
12	Alexander Iliev, Sean W. Smith	Protecting Client Privacy with Trusted Computing at the Server.	IEEE Secur. Priv.	2005	DBLP DOI BibTeX RDF	Secure coprocessor, Oblivious RAM, network traffic archival, prototype, PKI, Private Information Retrieval
12	Jeffrey T. Draper, Tim Barrett, Jeff Sondeen, Sumit D. Mediratta, Chang Woo Kang, Ihn Kim, Gokhan Daglikoca	A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	memory bandwidth, memory wall, processing-in-memory
12	Arne Schulz, Wolfgang Nebel	Optimization of Digital Audio Processing Algorithms Suitable for Hearing Aids.	PATMOS	2005	DBLP DOI BibTeX RDF
12	Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid	Techniques for synthesizing binaries to an advanced register/memory structure.	FPGA	2005	DBLP DOI BibTeX RDF	smart buffers, FPGA, embedded systems, synthesis, decompilation, binaries
12	Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee	SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
12	Sven Heithecker, Rolf Ernst	An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
12	Hamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian 0001, Neda Zolfaghari	Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms.	DSD	2005	DBLP DOI BibTeX RDF
12	Wido Kruijtzer, Winfried Gehrke, Víctor Reyes, Ghiath Alkadi, Thomas Hinz, Jörn Jachalsky, Bruno Steux	The design of a smart imaging core for automotive and consumer applications: a case study.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	image processing, system level design
12	Francesco Lertora, Michele Borgatti	Handling Different Computational Granularity by a Reconfigurable IC Featuring Embedded FPGAs and a Network-on-Chip.	FCCM	2005	DBLP DOI BibTeX RDF
12	Jun-Cheol Jeon, Kee-Won Kim, Kee-Young Yoo	Evolutionary Hardware Architecture for Division in Elliptic Curve Cryptosystems over GF(2n).	ICNC (3)	2005	DBLP DOI BibTeX RDF
12	Kai Zheng 0003, Zhen Liu 0018, Bin Liu 0001	High Performance Embedded Route Lookup Coprocessor for Network Processors.	ICCNMC	2005	DBLP DOI BibTeX RDF