Search results for "resynthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	William L. Martens	Principal Components Analysis and Resynthesis of Spectral Cues to Perceived Direction.	ICMC	1987	DBLP BibTeX RDF
21	Russell G. Payne	A Microcomputer-Based Analysis/Resynthesis Scheme for Processing Sampled Sounds using FM.	ICMC	1987	DBLP BibTeX RDF
21	James W. Beauchamp	Data Reduction and Resynthesis of Connected Solo Passages using Frequency, Amplitude, and "Brightness" Detection and the Nonlinear Synthesis Technique.	ICMC	1981	DBLP BibTeX RDF
21	F. J. Owens	Resynthesis of speech.		1980	RDF
21	Lei F. Willems	Speech resynthesis with a hardware synthesizer.	ICASSP	1976	DBLP DOI BibTeX RDF
15	Chen Huang 0005, Frank Vahid	Server-side coprocessor updating for mobile devices with FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	coprocessing, fpgas, dynamic optimization, acceleration
15	Alan Mishchenko, Robert K. Brayton, Stephen Jang	Global delay optimization using structural choices.	FPGA	2010	DBLP DOI BibTeX RDF	technology mpping, FPGA, interpolation, windowing, boolean satisfiability, logic optimization
15	Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li 0001, Gi-Joon Nam, Charles B. Winn	Detecting tangled logic structures in VLSI netlists.	DAC	2010	DBLP DOI BibTeX RDF	congestion prediction, rent rule, tangled logic, clustering
15	Yu Hu 0002, Victor Shih, Rupak Majumdar, Lei He 0001	Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
15	Daniel Rudoy, Prabahan Basu, Thomas F. Quatieri, Bob Dunn, Patrick J. Wolfe	Adaptive short-time analysis-synthesis for speech enhancement.	ICASSP	2008	DBLP DOI BibTeX RDF
15	Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi	SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement.	ICCD	2008	DBLP DOI BibTeX RDF
15	Anna Pribilová, Jiri Pribil	Spectrum Modification for Emotional Speech Synthesis.	COST 2102 School (Vietri)	2008	DBLP DOI BibTeX RDF	spectral envelope, emotional voice conversion, speech synthesis, emotional speech
15	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller	Techniques for the synthesis of reversible Toffoli networks.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	reversible logic synthesis, quantum computing, circuit optimization
15	Esther Klabbers, Jan P. H. van Santen, Alexander Kain	The Contribution of Various Sources of Spectral Mismatch to Audible Discontinuities in a Diphone Database.	IEEE Trans. Speech Audio Process.	2007	DBLP DOI BibTeX RDF
15	Nicola Laurenti, Giovanni De Poli, Daniele Montagner	A Nonlinear Method for Stochastic Spectrum Estimation in the Modeling of Musical Sounds.	IEEE Trans. Speech Audio Process.	2007	DBLP DOI BibTeX RDF
15	Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown	BddCut: Towards Scalable Symbolic Cut Enumeration.	ASP-DAC	2007	DBLP DOI BibTeX RDF
15	Ali Taylan Cemgil	Bayesian methods for multimedia signal processing.	ACM Multimedia	2007	DBLP DOI BibTeX RDF	multimedia signal processing, bayesian networks, graphical models, markov chain monte carlo, factor graphs, sequential monte carlo, variational bayes
15	Dimitri Kagaris, Themistoklis Haniotakis	Transistor-Level Synthesis for Low-Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
15	Dongwoo Lee, David T. Blaauw, Dennis Sylvester	Runtime Leakage Minimization Through Probability-Aware Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
15	Eva Navas, Inma Hernáez, Iker Luengo	An objective and subjective study of the role of semantics and prosodic features in building corpora for emotional TTS.	IEEE Trans. Speech Audio Process.	2006	DBLP DOI BibTeX RDF
15	Andrew G. Brooks, Cynthia Breazeal	Working with robots and objects: revisiting deictic reference for achieving spatial common ground.	HRI	2006	DBLP DOI BibTeX RDF	natural gesture understanding, spatial behavior, human-robot interaction, multimodal interfaces
15	M. Moiz Khan, Spyros Tragoudas	Rewiring for watermarking digital circuit netlists.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
15	Peter Suaris, Dongsheng Wang 0012, Nan-Chi Chou	A practical cut-based physical retiming algorithm for field programmable gate arrays.	ASP-DAC	2005	DBLP DOI BibTeX RDF
15	Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown	FPGA Logic Synthesis Using Quantified Boolean Satisfiability.	SAT	2005	DBLP DOI BibTeX RDF
15	Keoncheol Shin, Taewhan Kim	Tight integration of timing-driven synthesis and placement of parallel multiplier circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
15	Keoncheol Shin, Taewhan Kim	An integrated approach to timing-driven synthesis and placement of arithmetic circuits.	ASP-DAC	2004	DBLP DOI BibTeX RDF
15	M. Moiz Khan, Spyros Tragoudas	Rewiring for Watermarking Digital Circuits.	ISQED	2004	DBLP DOI BibTeX RDF
15	Navin Vemuri, Priyank Kalla, Russell Tessier	BDD-based logic synthesis for LUT-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	FPGA, decomposition, logic synthesis, BDD
15	Martin A. Giese, Barbara Knappmeyer, Heinrich H. Bülthoff	Automatic Synthesis of Sequences of Human Movements by Linear Combination of Learned Example Patterns.	Biologically Motivated Computer Vision	2002	DBLP DOI BibTeX RDF
15	Philip Heng Wai Leong, Chiu-Wing Sham, W. C. Wong, H. Y. Wong, Wing Seung Yuen, Monk-Ping Leong	A bitstream reconfigurable FPGA implementation of the WSAT algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
15	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev	Decomposition and technology mapping of speed-independent circuits using Boolean relations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
15	Ganesh Lakshminarayana, Niraj K. Jha	High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
15	Andreas G. Veneris, Ibrahim N. Hajj	Design error diagnosis and correction via test vector simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
15	W. Knox Carey, Daniel B. Chuang, Sheila S. Hemami	Regularity-preserving image interpolation.	IEEE Trans. Image Process.	1999	DBLP DOI BibTeX RDF
15	Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen	ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	concurrent object-oriented system-level synthesis, fuzzy design-space exploration, learning
15	Ganesh Lakshminarayana, Niraj K. Jha	Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions.	DAC	1998	DBLP DOI BibTeX RDF	transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band
15	Jason Cong, Chang Wu	FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits.	DAC	1997	DBLP DOI BibTeX RDF
15	Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal	Functional test generation for synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
15	Balakrishnan Iyer, Maciej J. Ciesielski	Metamorphosis: state assignment by retiming and re-encoding.	ICCAD	1996	DBLP DOI BibTeX RDF	Sequential Logic, Finite State Machine, Logic Synthesis, State Assignment, State Encoding
15	Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev	Synthesizing Petri nets from state-based models.	ICCAD	1995	DBLP DOI BibTeX RDF	Petri nets, Synthesis, Finite State Machines, Asynchronous Circuits, Transition Systems