Search results for "routability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang 0001, Evangeline F. Y. Young, Bei Yu 0001	RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
19	Ziad Abuowaimer, Dani Maarouf, Timothy Martin, Jérémy Foxcroft, Gary Gréwal, Shawki Areibi, Anthony Vannelli	GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures.	ACM Trans. Design Autom. Electr. Syst.	2018	DBLP DOI BibTeX RDF
19	Hongxia Zhou, Chiu-Wing Sham, Hailong Yao	Revisiting Routability-Driven Placement for Analog and Mixed-Signal Circuits.	ACM Trans. Design Autom. Electr. Syst.	2018	DBLP DOI BibTeX RDF
19	Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal	Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model.	CoRR	2018	DBLP BibTeX RDF
19	Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen 0001, Nvidia Corporation	RouteNet: routability prediction for mixed-size designs using convolutional neural network.	ICCAD	2018	DBLP DOI BibTeX RDF
19	Jai-Ming Lin, Jhih-Sheng Syu, I-Ru Chen	Macro-aware row-style power delivery network design for better routability.	ICCAD	2018	DBLP DOI BibTeX RDF
19	Li-Chin Chen, Chien-Chia Huang, Yao-Lin Chang, Hung-Ming Chen	A learning-based methodology for routability prediction in placement.	VLSI-DAT	2018	DBLP DOI BibTeX RDF
19	Ilgweon Kang, Dongwon Park, Changho Han, Chung-Kuan Cheng	Fast and precise routability analysis with conditional design rules.	SLIP@DAC	2018	DBLP DOI BibTeX RDF
19	Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young, Bei Yu 0001	Routability-driven and fence-aware legalization for mixed-cell-height circuits.	DAC	2018	DBLP DOI BibTeX RDF
19	Jai-Ming Lin, Jung-An Yang	Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
19	Guanshun Yu, Tom Y. Cheng, Blayne Kettlewell, Harrison Liew, Mingoo Seok, Peter R. Kinget	FPGA with Improved Routability and Robustness in 130nm CMOS with Open-Source CAD Targetability.	CoRR	2017	DBLP BibTeX RDF
19	Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler	Effects of cell shapes on the routability of Digital Microfluidic Biochips.	DATE	2017	DBLP DOI BibTeX RDF
19	Jai-Ming Lin, Bo-Heng Yu, Li-Yen Chang	Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits.	ASP-DAC	2017	DBLP DOI BibTeX RDF
19	Julia Casarin Puget, Andre Saldanha Oliveira, Jorge Seelen, Ricardo Reis 0001	UFRGSPlace: Routability driven FPGA placement algorithm for heterogeneous FPGAs.	ICECS	2017	DBLP DOI BibTeX RDF
19	Daohang Shi, Azadeh Davoodi	Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells.	ISPD	2017	DBLP DOI BibTeX RDF
19	Wei-Ting Jonas Chan, Pei-Hsin Ho, Andrew B. Kahng, Prashant Saxena	Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning.	ISPD	2017	DBLP DOI BibTeX RDF
19	Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu 0001	Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper).	ICCAD	2017	DBLP DOI BibTeX RDF
19	Wing-Kai Chow, Jian Kuang 0001, Peishan Tu, Evangeline F. Y. Young	Fence-aware detailed-routability driven placement.	SLIP	2017	DBLP DOI BibTeX RDF
19	Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera	Pin accessibility evaluating model for improving routability of VLSI designs.	SoCC	2017	DBLP DOI BibTeX RDF
19	Wenchao Gao, Tian Gao, Ruijie Zhao 0006, Liumin Wang, Xing Liang	Routability-driven legalization algorithm with minimum total movement for supporting agricultural machinery design.	Agro-Geoinformatics	2017	DBLP DOI BibTeX RDF
19	Wing-Kai Chow, Evangeline F. Y. Young	Placement: From Wirelength to Detailed Routability.	IPSJ Trans. Syst. LSI Des. Methodol.	2016	DBLP DOI BibTeX RDF
19	Aiwu Ruan, Haiyang Huang, Jingwu Wang, Yifan Zhao	A Routability-Aware Algorithm for Both Global and Local Interconnect Resource Test and Diagnosis of Xilinx SRAM-FPGAs.	J. Electron. Test.	2016	DBLP DOI BibTeX RDF
19	Xu He, Yao Wang 0002, Yang Guo 0003, Evangeline F. Y. Young	Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement.	ACM Trans. Design Autom. Electr. Syst.	2016	DBLP DOI BibTeX RDF
19	Jiajun Shi, Mingyu Li, Santosh Khasanvis, Mostafizur Rahman, Csaba Andras Moritz	Routability in 3D IC Design: Monolithic 3D vs. Skybridge 3D CMOS.	CoRR	2016	DBLP BibTeX RDF
19	Gong Chen 0002, Bo Liu 0031, Shigetoshi Nakatake, Bo Yang 0004	Routability of twisted common-centroid capacitor array under signal coupling constraints.	MWSCAS	2016	DBLP DOI BibTeX RDF
19	Srihari Yechangunja, Raj Shekhar, Mohit Kumar, Nikhil Tripathi, Abhishek Mittal, Abhishek Ranjan, Jianfeng Liu, Minyoung Mo, Kyung Tae Do, Jung Yun Choi, SungHo Park	Sequential analysis driven reset optimization to improve power, area and routability.	DATE	2016	DBLP BibTeX RDF
19	Yi-Siang Su, Tsung-Yi Ho, Der-Tsai Lee	A routability-driven flow routing algorithm for programmable microfluidic devices.	ASP-DAC	2016	DBLP DOI BibTeX RDF
19	André Ivanov, Peter Hallschmid, Zhonghua Zhou	Local congestion and blockage aware routability analysis using adaptive flexible modeling.	ICECS	2016	DBLP DOI BibTeX RDF
19	Stephen Yang, Aman Gayasen, Chandra Mulpuri, Sainath Reddy, Rajat Aggarwal	Routability-Driven FPGA Placement Contest.	ISPD	2016	DBLP DOI BibTeX RDF
19	Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang 0001, Peishan Tu, Hang Zhang 0010, Evangeline F. Y. Young, Bei Yu 0001	RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs.	ICCAD	2016	DBLP DOI BibTeX RDF
19	Wuxi Li, Shounak Dhar, David Z. Pan	UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing.	ICCAD	2016	DBLP DOI BibTeX RDF
19	Jiajun Shi, Mingyu Li, Santosh Khasanvis, Mostafizur Rahman, Csaba Andras Moritz	Routability in 3D IC design: Monolithic 3D vs. Skybridge 3D CMOS.	NANOARCH	2016	DBLP DOI BibTeX RDF
19	Wei-Ting Jonas Chan, Yang Du 0001, Andrew B. Kahng, Siddhartha Nath, Kambiz Samadi	BEOL stack-aware routability prediction from placement using data mining techniques.	ICCD	2016	DBLP DOI BibTeX RDF
19	Oleg Petelin, Vaughn Betz	Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks.	FPL	2015	DBLP DOI BibTeX RDF
19	Qin Wang 0005, Weiran He, Hailong Yao, Tsung-Yi Ho, Yici Cai	SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips.	ISPD	2015	DBLP DOI BibTeX RDF
19	Chun-Kai Wang, Chuan-Chia Huang, Shih-Ying Sean Liu, Ching-Yu Chin, Sheng-Te Hu, Wei-Chen Wu, Hung-Ming Chen	Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability.	ISPD	2015	DBLP DOI BibTeX RDF
19	Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang	Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints.	ICCAD	2015	DBLP DOI BibTeX RDF
19	Jai-Ming Lin, Chih-Yao Hu, Kai-Chung Chan	Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint.	VLSI-DAT	2015	DBLP DOI BibTeX RDF
19	Wen-Hsiang Chang, Mango Chia-Tso Chao, Shi-Hao Chen	Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
19	Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Sheng Chou, Tzu-Hen Lin, Tung-Chieh Chen, Yao-Wen Chang	NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
19	Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li 0001, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar	Techniques for scalable and effective routability evaluation.	ACM Trans. Design Autom. Electr. Syst.	2014	DBLP DOI BibTeX RDF
19	Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi	Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA.	ISVLSI	2014	DBLP DOI BibTeX RDF
19	Ka-Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young	A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
19	Wenyi Feng, Jonathan W. Greene, Kristofer Vorwerk, Val Pevzner, Arun Kundu	Rent's rule based FPGA packing for routability optimization.	FPGA	2014	DBLP DOI BibTeX RDF
19	Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang	Metal layer planning for silicon interposers with consideration of routability and manufacturing cost.	DATE	2014	DBLP DOI BibTeX RDF
19	Shuai Li, Cheng-Kok Koh	Analytical placement of mixed-size circuits for better detailed-routability.	ASP-DAC	2014	DBLP DOI BibTeX RDF
19	Meng-Ling Chen, Tu-Hsiung Tsai, Hung-Ming Chen, Shi-Hao Chen	Routability-driven bump assignment for chip-package co-design.	ASP-DAC	2014	DBLP DOI BibTeX RDF
19	Yuan Wang, Simon J. Bale, James Alfred Walker, Martin A. Trefzer, Andy M. Tyrrell	Multiobjective genetic algorithm for routability-driven circuit clustering on FPGAs.	ICES	2014	DBLP DOI BibTeX RDF
19	Yi-Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang	Routability-Driven Blockage-Aware Macro Placement.	DAC	2014	DBLP DOI BibTeX RDF
19	Tao Lin 0007, Chris Chu	POLAR 2.0: An Effective Routability-Driven Placer.	DAC	2014	DBLP DOI BibTeX RDF
19	Hanyu Liu, Senthilkumar Thoravi Rajavel, Ali Akoglu	Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms.	ACM Trans. Reconfigurable Technol. Syst.	2013	DBLP DOI BibTeX RDF
19	Joydip Das, Steven J. E. Wilton	Towards development of an analytical model relating FPGA architecture parameters to routability.	ACM Trans. Reconfigurable Technol. Syst.	2013	DBLP DOI BibTeX RDF
19	Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih	Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs.	Integr.	2013	DBLP DOI BibTeX RDF
19	Zhi-Wei Chen, Jin-Tai Yan	Routability-constrained multi-bit flip-flop construction for clock power reduction.	Integr.	2013	DBLP DOI BibTeX RDF
19	Yanheng Zhang, Chris Chu	Fast and Effective Placement Refinement for Routability.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
19	Xu He, Tao Huang 0016, Linfu Xiao, Haitong Tian, Evangeline F. Y. Young	Ripple: A Robust and Effective Routability-Driven Placer.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
19	Wafaa A. H. Ali Alsalihy, Majed Salam S. Alsayfi	Integrating Identity-Based Encryption in the Return Routability Protocol to Enhance Signal Security in Mobile IPv6.	Wirel. Pers. Commun.	2013	DBLP DOI BibTeX RDF
19	Mei-Hsiang Tsai, Po-Yang Hsu, Hung-Yi Li, Yi-Huang Hung, Yi-Yu Liu	Routability optimization for crossbar-switch structured ASIC design.	ACM Trans. Design Autom. Electr. Syst.	2013	DBLP DOI BibTeX RDF
19	Jason Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao	Optimizing routability in large-scale mixed-size placement.	ASP-DAC	2013	DBLP DOI BibTeX RDF
19	Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li	Case study for placement solutions in ispd11 and dac12 routability-driven placement contests.	ISPD	2013	DBLP DOI BibTeX RDF
19	Faisal Al Hawi, Chan Yeob Yeun, Khaled Salah 0001	Secure Framework for the Return Routability Procedure in MIPv6.	GreenCom/iThings/CPScom	2013	DBLP DOI BibTeX RDF
19	Xu He, Tao Huang 0016, Wing-Kai Chow, Jian Kuang 0001, Ka-Chun Lam, Wenzan Cai, Evangeline F. Y. Young	Ripple 2.0: high quality routability-driven placement via global router integration.	DAC	2013	DBLP DOI BibTeX RDF
19	Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li	Optimization of placement solutions for routability.	DAC	2013	DBLP DOI BibTeX RDF
19	Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang	Routability-driven placement for hierarchical mixed-size circuit designs.	DAC	2013	DBLP DOI BibTeX RDF
19	Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang	Routability-driven placement algorithm for analog integrated circuits.	ISPD	2012	DBLP DOI BibTeX RDF
19	Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li 0001, Yaoguang Wei	ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite.	ICCAD	2012	DBLP DOI BibTeX RDF
19	Insup Shin, Donkyu Baek, Youngsoo Shin	Introducing irregularity to routing architecture of structured ASIC for better routability.	FPT	2012	DBLP DOI BibTeX RDF
19	Yanheng Zhang, Chris Chu	GDRouter: interleaved global routing and detailed routing for ultimate routability.	DAC	2012	DBLP DOI BibTeX RDF
19	Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li 0001, Yaoguang Wei	The DAC 2012 routability-driven placement contest and benchmark suite.	DAC	2012	DBLP DOI BibTeX RDF
19	Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li 0001, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar	GLARE: global and local wiring aware routability evaluation.	DAC	2012	DBLP DOI BibTeX RDF
19	Mohamed Amine Abid, Abdelfettah Belghith	Stability routing with constrained path length for improved routability in dynamic MANETs.	Pers. Ubiquitous Comput.	2011	DBLP DOI BibTeX RDF
19	Lakshmi Easwaran, Ali Akoglu	Net-length-based routability-driven power-aware clustering.	ACM Trans. Reconfigurable Technol. Syst.	2011	DBLP DOI BibTeX RDF
19	Girish N. Nair	Structural Routability of n-Pairs Information Networks	CoRR	2011	DBLP BibTeX RDF
19	Joydip Das, Steven J. E. Wilton	An analytical model relating FPGA architecture parameters to routability.	FPGA	2011	DBLP DOI BibTeX RDF
19	Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak	Cut-demand based routing resource allocation and consolidation for routability enhancement.	ASP-DAC	2011	DBLP DOI BibTeX RDF
19	Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li 0001, Gi-Joon Nam, Jarrod A. Roy	The ISPD-2011 routability-driven placement contest and benchmark suite.	ISPD	2011	DBLP DOI BibTeX RDF
19	Xu He, Tao Huang 0016, Linfu Xiao, Haitong Tian, Guxin Cui, Evangeline F. Y. Young	Ripple: An effective routability-driven placer by iterative cell movement.	ICCAD	2011	DBLP DOI BibTeX RDF
19	Myung-Chul Kim, Jin Hu, Dongjin Lee, Igor L. Markov	A SimPLR method for routability-driven placement.	ICCAD	2011	DBLP DOI BibTeX RDF
19	Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, Yao-Wen Chang	Routability-driven analytical placement for mixed-size circuit designs.	ICCAD	2011	DBLP DOI BibTeX RDF
19	Tilo Meister, Jens Lienig, Gisbert Thomke	Interface optimization for improved routability in chip-package-board co-design.	SLIP	2011	DBLP DOI BibTeX RDF
19	Yang-Yang Li, Logan M. Rakai, Laleh Behjat, Bill Swartz	Wirelength and congestion estimation for routability-driven placement.	SLIP	2011	DBLP DOI BibTeX RDF
19	Jin-Tai Yan, Tung-Yen Sung, Zhi-Wei Chen	Simultaneous escape routing based on routability-driven net ordering.	SoCC	2011	DBLP DOI BibTeX RDF
19	Zhongdong Qi, Qiang Zhou 0001, Yanming Jia, Yici Cai, Zhuoyuan Li, Hailong Yao	A novel fine-grain track routing approach for routability and crosstalk optimization.	ISQED	2011	DBLP DOI BibTeX RDF
19	Mariem Turki, Mohamed Abid, Zied Marrakchi, Habib Mehrez	Routability driven placement for mesh-based FPGA architecture.	IDT	2010	DBLP DOI BibTeX RDF
19	Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan	Design-hierarchy aware mixed-size placement for routability optimization.	ICCAD	2010	DBLP DOI BibTeX RDF
19	Zhi-Wei Chen, Jin-Tai Yan	Routability-driven flip-flop merging process for clock power reduction.	ICCD	2010	DBLP DOI BibTeX RDF
19	Jin-Tai Yan, Ke-Chyuan Chen, Zhi-Wei Chen	Routability-driven RDL routing with pin reassignment.	SoCC	2010	DBLP DOI BibTeX RDF
19	Jin-Tai Yan, Kai-Ping Lu, Zhi-Wei Chen	Routability-driven partitioning-based IO assignment for flip-chip designs.	APCCAS	2010	DBLP DOI BibTeX RDF
19	Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu	Handling routability in floorplan design with twin binary trees.	Integr.	2009	DBLP DOI BibTeX RDF
19	Yoichi Tomioka, Atsushi Takahashi 0001	Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
19	Hengky Susanto, Byung-Guk Kim	Per-Connection Return Routability Test in Mobile IPv6.	NBiS	2009	DBLP DOI BibTeX RDF
19	JIanDe Yu, Jinmei Lai	A novel minloop SB design to improve FPGA routability.	FPGA	2009	DBLP DOI BibTeX RDF	minimum-loop-size maximization method, minloop switch box, routing resources design, fpga
19	Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih	Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design.	DATE	2009	DBLP DOI BibTeX RDF
19	Ke-Ren Dai, Chien-Hung Lu, Yih-Lang Li	GRPlacer: Improving routability and wire-length of global routing with circuit replacement.	ICCAD	2009	DBLP DOI BibTeX RDF
19	Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan	A study of routability estimation and clustering in placement.	ICCAD	2009	DBLP DOI BibTeX RDF
19	Tsung-Wei Huang, Tsung-Yi Ho	A fast routability- and performance-driven droplet routing algorithm for digital microfluidic biochips.	ICCD	2009	DBLP DOI BibTeX RDF
19	Ali Jahanian 0001, Morteza Saheb Zamani	Using metro-on-chip in physical design flow for congestion and routability improvement.	Microelectron. J.	2008	DBLP DOI BibTeX RDF
19	Wai-Chung Tang, Catherine L. Zhou, Yu-Liang Wu	A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability.	ERSA	2008	DBLP BibTeX RDF
19	Yoichi Tomioka, Atsushi Takahashi 0001	Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages.	ASP-DAC	2008	DBLP DOI BibTeX RDF
19	Audip Pandit, Lakshmi Easwaran, Ali Akoglu	Concurrent timing based and routability driven depopulation technique for FPGA packing.	FPT	2008	DBLP DOI BibTeX RDF