|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 319 occurrences of 199 keywords
|
|
|
Results
Found 437 publication records. Showing 437 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
14 | Louis-Charles Trudeau, Ghyslain Gagnon, François Gagnon, Claude Thibeault, Thomas Awad, Doug Morrissey |
A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 21st IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2015, Mountain View, CA, USA, May 4-6, 2015, pp. 17-18, 2015, IEEE Computer Society, 978-1-4799-8716-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Edwin Hsing-Mean Sha, Weiwen Jiang, Qingfeng Zhuge, Lei Yang 0018, Xianzhang Chen |
On the Design of High-Performance and Energy-Efficient Probabilistic Self-Timed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC/CSS/ICESS ![In: 17th IEEE International Conference on High Performance Computing and Communications, HPCC 2015, 7th IEEE International Symposium on Cyberspace Safety and Security, CSS 2015, and 12th IEEE International Conference on Embedded Software and Systems, ICESS 2015, New York, NY, USA, August 24-26, 2015, pp. 260-265, 2015, IEEE, 978-1-4799-8937-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Stephen Longfield Jr., Brittany Nkounkou, Rajit Manohar, Ross Tate |
Preventing glitches and short circuits in high-level self-timed chip specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation, Portland, OR, USA, June 15-17, 2015, pp. 270-279, 2015, ACM, 978-1-4503-3468-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Mickaël Fiorentino, Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault |
Self-timed circuits FPGA implementation flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 13th International New Circuits and Systems Conference, NEWCAS 2015, Grenoble, France, June 7-10, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8893-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | XuanKhanh Do, Amira Dkhil, Stéphane Louise |
Self-Timed Periodic Scheduling of Data-Dependent Tasks in Embedded Streaming Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP (2) ![In: Algorithms and Architectures for Parallel Processing - 15th International Conference, ICA3PP 2015, Zhangjiajie, China, November 18-20, 2015, Proceedings, Part II, pp. 458-478, 2015, Springer, 978-3-319-27121-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Edwin Hsing-Mean Sha, Weiwen Jiang, Qingfeng Zhuge, Xianzhang Chen, Lei Yang 0018 |
Prevent Deadlock and Remove Blocking for Self-Timed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP (1) ![In: Algorithms and Architectures for Parallel Processing - 15th International Conference, ICA3PP 2015, Zhangjiajie, China, November 18-20, 2015, Proceedings, Part I, pp. 155-169, 2015, Springer, 978-3-319-27118-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Nail Etkin Can Akkaya, Burak Erbagci, Raymond Carley, Ken Mai |
A DPA-resistant self-timed three-phase dual-rail pre-charge logic family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2015, Washington, DC, USA, 5-7 May, 2015, pp. 112-117, 2015, IEEE Computer Society, 978-1-4673-7420-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Jingcheng Wang, Nathaniel Ross Pinckney, David T. Blaauw, Dennis Sylvester |
Reconfigurable self-timed regenerators for wide-range voltage scaled interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015, pp. 1-4, 2015, IEEE, 978-1-4673-7191-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Laura Fick, David Fick, Massimo Alioto, David T. Blaauw, Dennis Sylvester |
A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 49(11), pp. 2462-2473, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Carlos Gómez Osuna, Pablo Ituero, Marisa López-Vallejo |
A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 14(1), pp. 129-143, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu |
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3), pp. 865-876, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Susana Ortega-Cisneros, Juan José Raygoza-Panduro, José Roberto Reyes Barón, Daniel Tonali Aranda Bretón, Antonio Casillas Zamora |
Characterization technique to implement self-timed cells for VLSI design blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCE ![In: 11th International Conference on Electrical Engineering, Computing Science and Automatic Control, CCE 2014, Campeche, Mexico, September 29 - October 3, 2014, pp. 1-6, 2014, IEEE, 978-1-4799-6228-0. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Roshan Silwal, Mohammed Y. Niamat |
Asynchronous physical unclonable function using FPGA-based self-timed ring oscillator (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: The 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Monterey, CA, USA - February 26 - 28, 2014, pp. 252, 2014, ACM, 978-1-4503-2671-1. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Weiwen Jiang, Qingfeng Zhuge, Juan Yi, Lei Yang 0018, Edwin Hsing-Mean Sha |
On self-timed ring for consistent mapping and maximum throughput. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, Chongqing, China, August 20-22, 2014, pp. 1-9, 2014, IEEE Computer Society, 978-1-4799-3953-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Laurent Fesquet, Abdelkarim Cherkaoui, Oussama Elissati |
Self-timed rings as low-phase noise programmable oscillators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 12th International New Circuits and Systems Conference, NEWCAS 2014, Trois-Rivieres, QC, Canada, June 22-25, 2014, pp. 409-412, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Amira Dkhil, XuanKhanh Do, Paul Dubrulle, Stéphane Louise, Christine Rochange |
Self-timed Periodic Scheduling for a Cyclo-static DataFlow Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCS ![In: Graph-Based Representation and Reasoning - 21st International Conference on Conceptual Structures, ICCS 2014, Iaşi, Romania, July 27-30, 2014, Proceedings, pp. 1134-1145, 2014, Springer, 978-3-319-08388-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Ramy N. Tadros, Abdelrahman H. Elsayed, Maged Ghoneima, Yehea I. Ismail |
A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pp. 1520-1523, 2014, IEEE, 978-1-4799-3431-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Daniel Morrison, Irek Ulidowski |
Direction-Reversible Self-Timed Cellular Automata for Delay-Insensitive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACRI ![In: Cellular Automata - 11th International Conference on Cellular Automata for Research and Industry, ACRI 2014, Krakow, Poland, September 22-25, 2014. Proceedings, pp. 367-377, 2014, Springer, 978-3-319-11519-1. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | P. Balasubramanian 0001, David A. Edwards, William B. Toms |
Self-Timed Section-Carry Based Carry Lookahead Adders and the Concept of Alias Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 22(4), 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Shi-Yu Huang, Yu-Hsiang Lin, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng |
Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8), pp. 1265-1273, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Kanad Chakraborty, James E. Kelly, Brian P. Evans |
Novel Self-Timed, Pipelined Clock Scan Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 29(2), pp. 241-247, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Frank P. Burns, Abdullah Baz, Delong Shang, Alex Yakovlev |
Variability analysis of self-timed SRAM robustness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Karlsruhe, Germany, September 9-11, 2013, pp. 24-31, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | P. Balasubramanian, D. Dhivyaa, J. P. Jayakirthika, P. Kaviyarasi, K. Prasad |
Low power self-timed carry lookahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013, pp. 457-460, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Jonathan Tse, Benjamin Hill 0001, Rajit Manohar |
A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 19th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2013, Santa Monica, CA, USA, May 19-22, 2013, pp. 124-133, 2013, IEEE Computer Society, 978-1-4673-5956-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet |
A Self-Timed Ring Based True Random Number Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 19th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2013, Santa Monica, CA, USA, May 19-22, 2013, pp. 99-106, 2013, IEEE Computer Society, 978-1-4673-5956-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Lars Lucas, Tobias Schuele, Wolfgang Schwitzer |
Self-timed Scheduling and Execution of Nonlinear Pipelines with Parallel Stages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MUSEPAT ![In: Multicore Software Engineering, Performance, and Tools - International Conference, MUSEPAT 2013, St. Petersburg, Russia, August 19-20, 2013. Proceedings, pp. 1-12, 2013, Springer, 978-3-642-39954-1. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Chao Chen 0019, Zhichao Tan, Michiel A. P. Pertijs |
A 1V 14b self-timed zero-crossing-based incremental ΔΣ ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013, pp. 274-275, 2013, IEEE, 978-1-4673-4515-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | P. Balasubramanian 0001, David A. Edwards, William B. Toms |
Redundant Logic Insertion and Latency Reduction in Self-Timed Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2012, pp. 575389:1-575389:13, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet |
Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, pp. 1325-1330, 2012, IEEE, 978-1-4577-2145-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu |
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 18th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2012, Kgs. Lyngby, Denmark, May 7-9, 2012, pp. 41-48, 2012, IEEE Computer Society, 978-1-4673-1360-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Julian P. Murphy, Máire O'Neill, Frank P. Burns, Alexandre V. Bystrov, Alexandre Yakovlev, Basel Halak |
Self-Timed Physically Unclonable Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NTMS ![In: 5th International Conference on New Technologies, Mobility and Security, Istanbul, Turkey, NTMS 2012, May 7-10, 2012, pp. 1-5, 2012, IEEE, 978-1-4673-0229-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Ezz El-Din O. Hussein, Sally Safwat, Maged Ghoneima, Yehea I. Ismail |
A 16Gbps low power self-timed SerDes transceiver for multi-core communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 1660-1663, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Daichi Takata, Teijiro Isokawa, Jia Lee, Ferdinand Peper, Nobuyuki Matsui |
On Construction by Worm-Like Agents on a Self-timed Cellular Automaton. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACRI ![In: Cellular Automata - 10th International Conference on Cellular Automata for Research and Industry, ACRI 2012, Santorini Island, Greece, September 24-27, 2012. Proceedings, pp. 575-584, 2012, Springer, 978-3-642-33349-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Markus Ferringer |
On Self-Timed Circuits in Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Reconfigurable Comput. ![In: Int. J. Reconfigurable Comput. 2011, pp. 972375:1-972375:16, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Tobias Strauch |
Multi-FPGA System With Unlimited and Self-Timed Wave-Pipelined Multiplexed Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 19(9), pp. 1549-1558, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Je-Hoon Lee, Young-Jun Song, Sang-Choon Kim |
A Self-Timed SRAM Design for Average-Case Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 94-D(8), pp. 1547-1556, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Ethiopia Nigussie, Sampo Tuuna, Juha Plosila, Pasi Liljeberg, Jouni Isoaho, Hannu Tenhunen |
Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 5(6), pp. 505-517, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø |
Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 5(4), pp. 342-353, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev |
Self-Timed SRAM for Energy Harvesting Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 7(2), pp. 274-284, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye |
An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 58-II(5), pp. 299-303, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Lukás Nagy, Viera Stopjaková |
Current sensing methodology for completion detection in self-timed systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, pp. 405-406, 2011, IEEE Computer Society, 978-1-4244-9755-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Florent Ouchet, Katell Morin-Allory, Laurent Fesquet |
C-elements for Hardened Self-timed Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings, pp. 247-256, 2011, Springer, 978-3-642-24153-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev, Alexandre V. Bystrov |
Improving the Robustness of Self-timed SRAM to Variable Vdds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings, pp. 32-42, 2011, Springer, 978-3-642-24153-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Masoud Zamani, Mehdi Baradaran Tahoori |
Self-timed nano-PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, San Diego, CA, USA, June 8-9, 2011, pp. 78-85, 2011, IEEE Computer Society, 978-1-4577-0993-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(4), pp. 843-845, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Justin Wenck, Jamie Collier, Jeff Siebert, Rajeevan Amirtharajah |
Scaling self-timed systems powered by mechanical vibration energy harvesting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 6(2), pp. 5:1-5:24, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Markus Ferringer |
Towards self-timed logic in the Time-Triggered Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN Workshops ![In: IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28 - July 1, 2010., pp. 136-141, 2010, IEEE Computer Society, 978-1-4244-7729-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev |
Self-Timed SRAM for Energy Harvesting Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers, pp. 105-115, 2010, Springer, 978-3-642-17751-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet |
Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers, pp. 137-149, 2010, Springer, 978-3-642-17751-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet |
A high-speed high-resolution low-phase noise oscillator using self-timed rings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010, pp. 173-178, 2010, IEEE. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Oussama Elissati, Sébastien Rieubon, Eslam Yahya, Laurent Fesquet |
Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC (Selected Papers) ![In: VLSI-SoC: Forward-Looking Trends in IC and Systems Design - 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010, Revised Selected Papers, pp. 22-42, 2010, Springer, 978-3-642-28565-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Phillip David Ferguson, Aristides Efthymiou, Tughrul Arslan, Danny Hume |
Optimising Self-Timed FPGA Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France, pp. 563-570, 2010, IEEE Computer Society, 978-0-7695-4171-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Masoud Zamani, Mehdi Baradaran Tahoori |
A transient error tolerant self-timed asynchronous architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 15th European Test Symposium, ETS 2010, Prague, Czech Republic, May 24-28, 2010, pp. 88-93, 2010, IEEE Computer Society, 978-1-4244-5833-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø |
Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 16th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2010, Grenoble, France, 3-6 May 2010, pp. 41-51, 2010, IEEE Computer Society, 978-0-7695-4032-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Markus Ferringer |
Investigating Self-Timed Circuits for the Time-Triggered Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReCoSoC ![In: Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, ReCoSoC 2010, Karlsruhe, Germany, May 17-19, 2010, pp. 101-108, 2010, KIT Scientific Publishing, 978-3-86644-515-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
14 | William B. Toms, David A. Edwards |
A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 10th International Conference on Application of Concurrency to System Design, ACSD 2010, Braga, Portugal, 21-25 June 2010, pp. 24-34, 2010, IEEE Computer Society, 978-0-7695-4066-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Asynchronous Combinational Logic Synthesis, Datapath Synthesis |
14 | Michele Lombardi 0001, Michela Milano |
Constraint Based Scheduling to Deal with Uncertain Durations and Self-Timed Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CP ![In: Principles and Practice of Constraint Programming - CP 2010 - 16th International Conference, CP 2010, St. Andrews, Scotland, UK, September 6-10, 2010. Proceedings, pp. 383-397, 2010, Springer, 978-3-642-15395-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Naoya Kagawa, Shuji Sannomiya, Makoto Iwata |
Macroscopic Power Simulation for Self-Timed Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2010, Las Vegas, Nevada, USA, July 12-15, 2010, 2 Volumes, pp. 589-595, 2010, CSREA Press, 1-60132-158-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
14 | Shuji Sannomiya, Kei Miyagi, Makoto Iwata, Hiroaki Nishikawa |
Stage-by-Stage Power Gating Circuit for Ultra-Low-Power Self-Timed Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2010, Las Vegas, Nevada, USA, July 12-15, 2010, 2 Volumes, pp. 596-602, 2010, CSREA Press, 1-60132-158-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
14 | Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé |
Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings, pp. 96-110, 2010, Springer, 978-3-642-11514-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Kazuhiro Komatsu, Shuji Sannomiya, Makoto Iwata, Hiroaki Terada, Suguru Kameda, Kazuo Tsubouchi |
Interacting Self-Timed Pipelines and Elementary Coupling Control Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(7), pp. 1642-1651, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Meng-Fan Chang, Su-Meng Yang, Kuang-Ting Chen |
Wide VDD Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8), pp. 1657-1667, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | P. Balasubramanian 0001, Doug A. Edwards |
Dual-Sum Single-Carry Self-Timed Adder Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, 13-15 May 2009, Tampa, Florida, USA, pp. 121-126, 2009, IEEE Computer Society, 978-0-7695-3684-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Eslam Yahya, Oussama Elissati, Hatem Zakaria, Laurent Fesquet, Marc Renaudin |
Programmable/Stoppable Oscillator Based on Self-Timed Rings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 15th IEEE Symposium on Asynchronous Circuits and Systems, ASYNC 2009, Chapel Hill, NC, USA, May 17-20, 2009, pp. 3-12, 2009, IEEE Computer Society, 978-1-4244-3933-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Scott Fairbanks |
The Lackey Self-Timed Switch-Fabric Design Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 15th IEEE Symposium on Asynchronous Circuits and Systems, ASYNC 2009, Chapel Hill, NC, USA, May 17-20, 2009, pp. 45-54, 2009, IEEE Computer Society, 978-1-4244-3933-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Jianwei Zhang 0006, Yizheng Ye, Bin-Da Liu, Feng Guan |
Self-timed Charge Recycling Search-line Drivers in Content-addressable Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 3070-3073, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Xuguang Guan, Duan Zhou, Yintang Yang, Zhangming Zhu |
A GALS Delay-insensitive Self-timed Wrapper for Network on Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACCS ![In: 2009 Pacific-Asia Conference on Circuits, Communications and Systems, PACCS 2009, Chengdu, China, 16-17 May 2009, pp. 265-268, 2009, IEEE Computer Society, 978-0-7695-3614-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Shuji Sannomiya, Kei Miyagi, Keiichi Sakai, Makoto Iwata, Hiroaki Nishikawa |
Self-Timed Power Gating for Ultra-Low-Power Pipeline Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2009, Las Vegas, Nevada, USA, July 13-17, 2009, 2 Volumes, pp. 575-580, 2009, CSREA Press, 1-60132-123-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
14 | Je-Hoon Lee, Kyoung-Rok Cho |
Design of a high performance self-timed ARM9 processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 5(3), pp. 87-93, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Maurizio Tranchero, Leonardo Maria Reyneri |
Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 373-380, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin |
High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 14th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2008, Newcastle upon Tyne, UK, April 7-10, 2008, pp. 29-38, 2008, IEEE Computer Society, 978-0-7695-3107-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Masashi Imai, Takashi Nanya |
A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 8th International Conference on Application of Concurrency to System Design (ACSD 2008), Xi'an, China, June 23-27, 2008, pp. 21-26, 2008, IEEE, 978-1-4244-1838-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Kei Miyagi, Shuji Sannomiya, Keiichi Sakai, Makoto Iwata, Hiroaki Nishikawa |
Autonomous Power-Supply Control for Ultra-Low-Power Self-Timed Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008, Las Vegas, Nevada, USA, July 14-17, 2008, 2 Volumes, pp. 704-709, 2008, CSREA Press, 1-60132-084-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
14 | Teijo Lehtonen, Pasi Liljeberg, Juha Plosila |
Online Reconfigurable Self-Timed Links for Fault Tolerant NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2007, pp. 94676:1-94676:13, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat |
Dynamic differential self-timed logic families for robust and low-power security ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 40(3), pp. 355-364, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Alberto de la Mora Gálvez |
Design and Implementation of the AMCC Self-Timed Microprocessor in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Univers. Comput. Sci. ![In: J. Univers. Comput. Sci. 13(3), pp. 377-387, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Taskin Koçak, George R. Harris, Ronald F. DeMara |
Self-Timed Architecture for Masked Successive Approximation Analog-to-Digital Conversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 16(1), pp. 1-14, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Orlando Moreira, Marco Bekooij |
Self-Timed Scheduling Analysis for Real-Time Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Adv. Signal Process. ![In: EURASIP J. Adv. Signal Process. 2007, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Teijiro Isokawa, Ferdinand Peper, Shin'ya Kowada, Naotake Kamiura, Nobuyuki Matsui |
On Detection and Isolation of Defective Cells in Self-Timed Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWNC ![In: Natural Computing - 2nd International Workshop on Natural Computing, Nagoya, Japan, December 2007, Proceedings, pp. 90-100, 2007, Springer, 978-4-431-88980-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Florian Dittmann 0001, Achim Rettberg, Raphael Weber |
Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ERSA ![In: Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2007, Las Vegas, Nevada, USA, June 25-28, 2007, pp. 152-158, 2007, CSREA Press, 1-60132-026-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
14 | Florian Dittmann 0001, Achim Rettberg, Raphael Weber |
Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 153-158, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
optimization, high-level synthesis, bit-serial architecture |
14 | Maurizio Tranchero, Leonardo Maria Reyneri |
Automatic Generation of VHDL Code for Self-Timed Circuits from Simulink Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007, pp. 287-290, 2007, IEEE, 978-1-4244-1377-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Yuan Chen 0002, Fei Xia, Delong Shang, Alexandre Yakovlev |
The Design of Virtual Self-timed Block for Activity Communication in SOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 10-13 July 2007, Bratislava, Slovak Republic, pp. 100-109, 2007, IEEE Computer Society, 978-0-7695-2902-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Shuji Sannomiya, Kazuhiro Komatsu, Makoto Iwata |
A Self-Timed Pipeline Circuit for Low-Power Surrounding LSI Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2007, Las Vegas, Nevada, USA, June 25-28, 2007, Volume 2, pp. 613-622, 2007, CSREA Press, 1-60132-021-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
14 | Makoto Iwata, Hiroshi Shima, Shuji Sannomiya, Hiroaki Nishikawa |
Self-Timed Stream Processor for Surrounding Computing Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2007, Las Vegas, Nevada, USA, June 25-28, 2007, Volume 2, pp. 655-662, 2007, CSREA Press, 1-60132-021-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
14 | David Fang, Filipp Akopyan, Rajit Manohar |
Self-Timed Thermally-Aware Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 438-439, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Heiner Giefers, Achim Rettberg |
Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 113-118, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
high-level synthesis, low power design, voltage scaling, bit-serial architecture |
14 | Dong-Wook Lee, Dong-Soo Har |
An Area Efficient Approach to Design Self-Timed Cryptosystems Combatting DPA Attack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(1), pp. 331-333, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
14 | Sizhong Chen, Tong Zhang 0002 |
Self-timed dynamically pipelined adaptive signal processing system: a case study of DLMS equalizer for read channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(7), pp. 1338-1347, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Eduardo I. Boemo |
FPGA implementation of a synchronous and self-timed neuroprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2005 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2005, Puebla City, Mexico, September 28-30, 2005, 2005, IEEE Computer Society, 0-7695-2456-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Juan Suardíaz Muro, Eduardo I. Boemo |
Rapid prototyping of a self-timed ALU with FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2005 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2005, Puebla City, Mexico, September 28-30, 2005, 2005, IEEE Computer Society, 0-7695-2456-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Adit D. Singh |
A self-timed structural test methodology for timing anomalies due to defects and process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pp. 7, 2005, IEEE Computer Society, 0-7803-9038-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Eun-Gu Jung, Eonpyo Hong, Kyoung-Son Jhang, Jeong-A Lee, Dong-Soo Har |
Self-timed Interconnect with Layered Interface Based on Distributed and Modularized Control for Multimedia SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PCM (1) ![In: Advances in Multimedia Information Processing - PCM 2005, 6th Pacific-Rim Conference on Multimedia, Jeju Island, Korea, November 13-16, 2005, Proceedings, Part I, pp. 500-511, 2005, Springer, 3-540-30027-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Scott C. Smith, Ronald F. DeMara, Jiann-Shiun Yuan, Dennis Ferguson, D. Lamb |
Optimization of NULL convention self-timed circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 37(3), pp. 135-165, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Pasi Liljeberg, Juha Plosila, Jouni Isoaho |
Self-timed communication platform for implementing high-performance systems-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 38(1), pp. 43-67, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Delong Shang, Frank P. Burns, Alexandre V. Bystrov, Albert Koelmans, Danil Sokolov, Alexandre Yakovlev |
A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 471-480, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Scott C. Smith |
Design of a NULL Convention Self-Timed Divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA/VLSI ![In: Proceedings of the International Conference on Embedded Systems and Applications, ESA '04 & Proceedings of the International Conference on VLSI, VLSI '04, June 21-24, 2004, Las Vegas, Nevada, USA, pp. 447-453, 2004, CSREA Press, 1-932415-41-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
14 | Ronald F. DeMara, Amit Kejriwal, Jude Seeber |
Feedback Techniques for Dual-Rail Self-Timed Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA/VLSI ![In: Proceedings of the International Conference on Embedded Systems and Applications, ESA '04 & Proceedings of the International Conference on VLSI, VLSI '04, June 21-24, 2004, Las Vegas, Nevada, USA, pp. 458-464, 2004, CSREA Press, 1-932415-41-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
14 | Xin Jia, Ranga Vemuri |
A Design Methodology for Self-Timed Event Logic Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA/VLSI ![In: Proceedings of the International Conference on Embedded Systems and Applications, ESA '04 & Proceedings of the International Conference on VLSI, VLSI '04, June 21-24, 2004, Las Vegas, Nevada, USA, pp. 475-479, 2004, CSREA Press, 1-932415-41-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
14 | Ethiopia Nigussie, Johanna Tuominen, Jouni Isoaho |
Analyses of signaling techniques for self-timed systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: Proceedings of the 2004 International Symposium on System-on-Chip, Tampere, Finland, November 16-18, 2004, pp. 89-92, 2004, IEEE, 0-7803-8558-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
Displaying result #201 - #300 of 437 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ >>] |
|