Search results for "self-timed"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Louis-Charles Trudeau, Ghyslain Gagnon, François Gagnon, Claude Thibeault, Thomas Awad, Doug Morrissey	A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline.	ASYNC	2015	DBLP DOI BibTeX RDF
14	Edwin Hsing-Mean Sha, Weiwen Jiang, Qingfeng Zhuge, Lei Yang 0018, Xianzhang Chen	On the Design of High-Performance and Energy-Efficient Probabilistic Self-Timed Systems.	HPCC/CSS/ICESS	2015	DBLP DOI BibTeX RDF
14	Stephen Longfield Jr., Brittany Nkounkou, Rajit Manohar, Ross Tate	Preventing glitches and short circuits in high-level self-timed chip specifications.	PLDI	2015	DBLP DOI BibTeX RDF
14	Mickaël Fiorentino, Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault	Self-timed circuits FPGA implementation flow.	NEWCAS	2015	DBLP DOI BibTeX RDF
14	XuanKhanh Do, Amira Dkhil, Stéphane Louise	Self-Timed Periodic Scheduling of Data-Dependent Tasks in Embedded Streaming Applications.	ICA3PP (2)	2015	DBLP DOI BibTeX RDF
14	Edwin Hsing-Mean Sha, Weiwen Jiang, Qingfeng Zhuge, Xianzhang Chen, Lei Yang 0018	Prevent Deadlock and Remove Blocking for Self-Timed Systems.	ICA3PP (1)	2015	DBLP DOI BibTeX RDF
14	Nail Etkin Can Akkaya, Burak Erbagci, Raymond Carley, Ken Mai	A DPA-resistant self-timed three-phase dual-rail pre-charge logic family.	HOST	2015	DBLP DOI BibTeX RDF
14	Jingcheng Wang, Nathaniel Ross Pinckney, David T. Blaauw, Dennis Sylvester	Reconfigurable self-timed regenerators for wide-range voltage scaled interconnect.	A-SSCC	2015	DBLP DOI BibTeX RDF
14	Laura Fick, David Fick, Massimo Alioto, David T. Blaauw, Dennis Sylvester	A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
14	Carlos Gómez Osuna, Pablo Ituero, Marisa López-Vallejo	A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs).	Sensors	2014	DBLP DOI BibTeX RDF
14	Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu	High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
14	Susana Ortega-Cisneros, Juan José Raygoza-Panduro, José Roberto Reyes Barón, Daniel Tonali Aranda Bretón, Antonio Casillas Zamora	Characterization technique to implement self-timed cells for VLSI design blocks.	CCE	2014	DBLP DOI BibTeX RDF
14	Roshan Silwal, Mohammed Y. Niamat	Asynchronous physical unclonable function using FPGA-based self-timed ring oscillator (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
14	Weiwen Jiang, Qingfeng Zhuge, Juan Yi, Lei Yang 0018, Edwin Hsing-Mean Sha	On self-timed ring for consistent mapping and maximum throughput.	RTCSA	2014	DBLP DOI BibTeX RDF
14	Laurent Fesquet, Abdelkarim Cherkaoui, Oussama Elissati	Self-timed rings as low-phase noise programmable oscillators.	NEWCAS	2014	DBLP DOI BibTeX RDF
14	Amira Dkhil, XuanKhanh Do, Paul Dubrulle, Stéphane Louise, Christine Rochange	Self-timed Periodic Scheduling for a Cyclo-static DataFlow Model.	ICCS	2014	DBLP DOI BibTeX RDF
14	Ramy N. Tadros, Abdelrahman H. Elsayed, Maged Ghoneima, Yehea I. Ismail	A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks.	ISCAS	2014	DBLP DOI BibTeX RDF
14	Daniel Morrison, Irek Ulidowski	Direction-Reversible Self-Timed Cellular Automata for Delay-Insensitive Circuits.	ACRI	2014	DBLP DOI BibTeX RDF
14	P. Balasubramanian 0001, David A. Edwards, William B. Toms	Self-Timed Section-Carry Based Carry Lookahead Adders and the Concept of Alias Logic.	J. Circuits Syst. Comput.	2013	DBLP DOI BibTeX RDF
14	Shi-Yu Huang, Yu-Hsiang Lin, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng	Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
14	Kanad Chakraborty, James E. Kelly, Brian P. Evans	Novel Self-Timed, Pipelined Clock Scan Architecture.	J. Electron. Test.	2013	DBLP DOI BibTeX RDF
14	Frank P. Burns, Abdullah Baz, Delong Shang, Alex Yakovlev	Variability analysis of self-timed SRAM robustness.	PATMOS	2013	DBLP DOI BibTeX RDF
14	P. Balasubramanian, D. Dhivyaa, J. P. Jayakirthika, P. Kaviyarasi, K. Prasad	Low power self-timed carry lookahead adders.	MWSCAS	2013	DBLP DOI BibTeX RDF
14	Jonathan Tse, Benjamin Hill 0001, Rajit Manohar	A Bit of Analysis on Self-Timed Single-Bit On-Chip Links.	ASYNC	2013	DBLP DOI BibTeX RDF
14	Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet	A Self-Timed Ring Based True Random Number Generator.	ASYNC	2013	DBLP DOI BibTeX RDF
14	Lars Lucas, Tobias Schuele, Wolfgang Schwitzer	Self-timed Scheduling and Execution of Nonlinear Pipelines with Parallel Stages.	MUSEPAT	2013	DBLP DOI BibTeX RDF
14	Chao Chen 0019, Zhichao Tan, Michiel A. P. Pertijs	A 1V 14b self-timed zero-crossing-based incremental ΔΣ ADC.	ISSCC	2013	DBLP DOI BibTeX RDF
14	P. Balasubramanian 0001, David A. Edwards, William B. Toms	Redundant Logic Insertion and Latency Reduction in Self-Timed Adders.	VLSI Design	2012	DBLP DOI BibTeX RDF
14	Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet	Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs.	DATE	2012	DBLP DOI BibTeX RDF
14	Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu	High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism.	ASYNC	2012	DBLP DOI BibTeX RDF
14	Julian P. Murphy, Máire O'Neill, Frank P. Burns, Alexandre V. Bystrov, Alexandre Yakovlev, Basel Halak	Self-Timed Physically Unclonable Functions.	NTMS	2012	DBLP DOI BibTeX RDF
14	Ezz El-Din O. Hussein, Sally Safwat, Maged Ghoneima, Yehea I. Ismail	A 16Gbps low power self-timed SerDes transceiver for multi-core communication.	ISCAS	2012	DBLP DOI BibTeX RDF
14	Daichi Takata, Teijiro Isokawa, Jia Lee, Ferdinand Peper, Nobuyuki Matsui	On Construction by Worm-Like Agents on a Self-timed Cellular Automaton.	ACRI	2012	DBLP DOI BibTeX RDF
14	Markus Ferringer	On Self-Timed Circuits in Real-Time Systems.	Int. J. Reconfigurable Comput.	2011	DBLP DOI BibTeX RDF
14	Tobias Strauch	Multi-FPGA System With Unlimited and Self-Timed Wave-Pipelined Multiplexed Routing.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
14	Je-Hoon Lee, Young-Jun Song, Sang-Choon Kim	A Self-Timed SRAM Design for Average-Case Performance.	IEICE Trans. Inf. Syst.	2011	DBLP DOI BibTeX RDF
14	Ethiopia Nigussie, Sampo Tuuna, Juha Plosila, Pasi Liljeberg, Jouni Isoaho, Hannu Tenhunen	Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects.	IET Circuits Devices Syst.	2011	DBLP DOI BibTeX RDF
14	Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø	Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection.	IET Comput. Digit. Tech.	2011	DBLP DOI BibTeX RDF
14	Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev	Self-Timed SRAM for Energy Harvesting Systems.	J. Low Power Electron.	2011	DBLP DOI BibTeX RDF
14	Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye	An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion.	IEEE Trans. Circuits Syst. II Express Briefs	2011	DBLP DOI BibTeX RDF
14	Lukás Nagy, Viera Stopjaková	Current sensing methodology for completion detection in self-timed systems.	DDECS	2011	DBLP DOI BibTeX RDF
14	Florent Ouchet, Katell Morin-Allory, Laurent Fesquet	C-elements for Hardened Self-timed Circuits.	PATMOS	2011	DBLP DOI BibTeX RDF
14	Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev, Alexandre V. Bystrov	Improving the Robustness of Self-timed SRAM to Variable Vdds.	PATMOS	2011	DBLP DOI BibTeX RDF
14	Masoud Zamani, Mehdi Baradaran Tahoori	Self-timed nano-PLA.	NANOARCH	2011	DBLP DOI BibTeX RDF
14	Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu	A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2010	DBLP DOI BibTeX RDF
14	Justin Wenck, Jamie Collier, Jeff Siebert, Rajeevan Amirtharajah	Scaling self-timed systems powered by mechanical vibration energy harvesting.	ACM J. Emerg. Technol. Comput. Syst.	2010	DBLP DOI BibTeX RDF
14	Markus Ferringer	Towards self-timed logic in the Time-Triggered Protocol.	DSN Workshops	2010	DBLP DOI BibTeX RDF
14	Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev	Self-Timed SRAM for Energy Harvesting Systems.	PATMOS	2010	DBLP DOI BibTeX RDF
14	Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet	Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case.	PATMOS	2010	DBLP DOI BibTeX RDF
14	Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet	A high-speed high-resolution low-phase noise oscillator using self-timed rings.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
14	Oussama Elissati, Sébastien Rieubon, Eslam Yahya, Laurent Fesquet	Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
14	Phillip David Ferguson, Aristides Efthymiou, Tughrul Arslan, Danny Hume	Optimising Self-Timed FPGA Circuits.	DSD	2010	DBLP DOI BibTeX RDF
14	Masoud Zamani, Mehdi Baradaran Tahoori	A transient error tolerant self-timed asynchronous architecture.	ETS	2010	DBLP DOI BibTeX RDF
14	Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø	Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study.	ASYNC	2010	DBLP DOI BibTeX RDF
14	Markus Ferringer	Investigating Self-Timed Circuits for the Time-Triggered Protocol.	ReCoSoC	2010	DBLP BibTeX RDF
14	William B. Toms, David A. Edwards	A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths.	ACSD	2010	DBLP DOI BibTeX RDF	Asynchronous Combinational Logic Synthesis, Datapath Synthesis
14	Michele Lombardi 0001, Michela Milano	Constraint Based Scheduling to Deal with Uncertain Durations and Self-Timed Execution.	CP	2010	DBLP DOI BibTeX RDF
14	Naoya Kagawa, Shuji Sannomiya, Makoto Iwata	Macroscopic Power Simulation for Self-Timed Pipeline.	PDPTA	2010	DBLP BibTeX RDF
14	Shuji Sannomiya, Kei Miyagi, Makoto Iwata, Hiroaki Nishikawa	Stage-by-Stage Power Gating Circuit for Ultra-Low-Power Self-Timed Pipeline.	PDPTA	2010	DBLP BibTeX RDF
14	Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé	Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors.	HiPEAC	2010	DBLP DOI BibTeX RDF
14	Kazuhiro Komatsu, Shuji Sannomiya, Makoto Iwata, Hiroaki Terada, Suguru Kameda, Kazuo Tsubouchi	Interacting Self-Timed Pipelines and Elementary Coupling Control Modules.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
14	Meng-Fan Chang, Su-Meng Yang, Kuang-Ting Chen	Wide VDD Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
14	P. Balasubramanian 0001, Doug A. Edwards	Dual-Sum Single-Carry Self-Timed Adder Designs.	ISVLSI	2009	DBLP DOI BibTeX RDF
14	Eslam Yahya, Oussama Elissati, Hatem Zakaria, Laurent Fesquet, Marc Renaudin	Programmable/Stoppable Oscillator Based on Self-Timed Rings.	ASYNC	2009	DBLP DOI BibTeX RDF
14	Scott Fairbanks	The Lackey Self-Timed Switch-Fabric Design Framework.	ASYNC	2009	DBLP DOI BibTeX RDF
14	Jianwei Zhang 0006, Yizheng Ye, Bin-Da Liu, Feng Guan	Self-timed Charge Recycling Search-line Drivers in Content-addressable Memories.	ISCAS	2009	DBLP DOI BibTeX RDF
14	Xuguang Guan, Duan Zhou, Yintang Yang, Zhangming Zhu	A GALS Delay-insensitive Self-timed Wrapper for Network on Chips.	PACCS	2009	DBLP DOI BibTeX RDF
14	Shuji Sannomiya, Kei Miyagi, Keiichi Sakai, Makoto Iwata, Hiroaki Nishikawa	Self-Timed Power Gating for Ultra-Low-Power Pipeline Circuit.	PDPTA	2009	DBLP BibTeX RDF
14	Je-Hoon Lee, Kyoung-Rok Cho	Design of a high performance self-timed ARM9 processor.	IEICE Electron. Express	2008	DBLP DOI BibTeX RDF
14	Maurizio Tranchero, Leonardo Maria Reyneri	Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools.	DSD	2008	DBLP DOI BibTeX RDF
14	Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin	High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators.	ASYNC	2008	DBLP DOI BibTeX RDF
14	Masashi Imai, Takashi Nanya	A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries.	ACSD	2008	DBLP DOI BibTeX RDF
14	Kei Miyagi, Shuji Sannomiya, Keiichi Sakai, Makoto Iwata, Hiroaki Nishikawa	Autonomous Power-Supply Control for Ultra-Low-Power Self-Timed Pipeline.	PDPTA	2008	DBLP BibTeX RDF
14	Teijo Lehtonen, Pasi Liljeberg, Juha Plosila	Online Reconfigurable Self-Timed Links for Fault Tolerant NoC.	VLSI Design	2007	DBLP DOI BibTeX RDF
14	Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat	Dynamic differential self-timed logic families for robust and low-power security ICs.	Integr.	2007	DBLP DOI BibTeX RDF
14	Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Alberto de la Mora Gálvez	Design and Implementation of the AMCC Self-Timed Microprocessor in FPGAs.	J. Univers. Comput. Sci.	2007	DBLP DOI BibTeX RDF
14	Taskin Koçak, George R. Harris, Ronald F. DeMara	Self-Timed Architecture for Masked Successive Approximation Analog-to-Digital Conversion.	J. Circuits Syst. Comput.	2007	DBLP DOI BibTeX RDF
14	Orlando Moreira, Marco Bekooij	Self-Timed Scheduling Analysis for Real-Time Applications.	EURASIP J. Adv. Signal Process.	2007	DBLP DOI BibTeX RDF
14	Teijiro Isokawa, Ferdinand Peper, Shin'ya Kowada, Naotake Kamiura, Nobuyuki Matsui	On Detection and Isolation of Defective Cells in Self-Timed Cellular Automata.	IWNC	2007	DBLP DOI BibTeX RDF
14	Florian Dittmann 0001, Achim Rettberg, Raphael Weber	Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial Architecture.	ERSA	2007	DBLP BibTeX RDF
14	Florian Dittmann 0001, Achim Rettberg, Raphael Weber	Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture.	SBCCI	2007	DBLP DOI BibTeX RDF	optimization, high-level synthesis, bit-serial architecture
14	Maurizio Tranchero, Leonardo Maria Reyneri	Automatic Generation of VHDL Code for Self-Timed Circuits from Simulink Specifications.	ICECS	2007	DBLP DOI BibTeX RDF
14	Yuan Chen 0002, Fei Xia, Delong Shang, Alexandre Yakovlev	The Design of Virtual Self-timed Block for Activity Communication in SOC.	ACSD	2007	DBLP DOI BibTeX RDF
14	Shuji Sannomiya, Kazuhiro Komatsu, Makoto Iwata	A Self-Timed Pipeline Circuit for Low-Power Surrounding LSI Chips.	PDPTA	2007	DBLP BibTeX RDF
14	Makoto Iwata, Hiroshi Shima, Shuji Sannomiya, Hiroaki Nishikawa	Self-Timed Stream Processor for Surrounding Computing Environment.	PDPTA	2007	DBLP BibTeX RDF
14	David Fang, Filipp Akopyan, Rajit Manohar	Self-Timed Thermally-Aware Circuits.	ISVLSI	2006	DBLP DOI BibTeX RDF
14	Heiner Giefers, Achim Rettberg	Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture.	SBCCI	2006	DBLP DOI BibTeX RDF	high-level synthesis, low power design, voltage scaling, bit-serial architecture
14	Dong-Wook Lee, Dong-Soo Har	An Area Efficient Approach to Design Self-Timed Cryptosystems Combatting DPA Attack.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2005	DBLP BibTeX RDF
14	Sizhong Chen, Tong Zhang 0002	Self-timed dynamically pipelined adaptive signal processing system: a case study of DLMS equalizer for read channel.	IEEE Trans. Circuits Syst. I Regul. Pap.	2005	DBLP DOI BibTeX RDF
14	Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Eduardo I. Boemo	FPGA implementation of a synchronous and self-timed neuroprocessor.	ReConFig	2005	DBLP DOI BibTeX RDF
14	Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Juan Suardíaz Muro, Eduardo I. Boemo	Rapid prototyping of a self-timed ALU with FPGAs.	ReConFig	2005	DBLP DOI BibTeX RDF
14	Adit D. Singh	A self-timed structural test methodology for timing anomalies due to defects and process variations.	ITC	2005	DBLP DOI BibTeX RDF
14	Eun-Gu Jung, Eonpyo Hong, Kyoung-Son Jhang, Jeong-A Lee, Dong-Soo Har	Self-timed Interconnect with Layered Interface Based on Distributed and Modularized Control for Multimedia SoCs.	PCM (1)	2005	DBLP DOI BibTeX RDF
14	Scott C. Smith, Ronald F. DeMara, Jiann-Shiun Yuan, Dennis Ferguson, D. Lamb	Optimization of NULL convention self-timed circuits.	Integr.	2004	DBLP DOI BibTeX RDF
14	Pasi Liljeberg, Juha Plosila, Jouni Isoaho	Self-timed communication platform for implementing high-performance systems-on-chip.	Integr.	2004	DBLP DOI BibTeX RDF
14	Delong Shang, Frank P. Burns, Alexandre V. Bystrov, Albert Koelmans, Danil Sokolov, Alexandre Yakovlev	A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
14	Scott C. Smith	Design of a NULL Convention Self-Timed Divider.	ESA/VLSI	2004	DBLP BibTeX RDF
14	Ronald F. DeMara, Amit Kejriwal, Jude Seeber	Feedback Techniques for Dual-Rail Self-Timed Circuits.	ESA/VLSI	2004	DBLP BibTeX RDF
14	Xin Jia, Ranga Vemuri	A Design Methodology for Self-Timed Event Logic Pipelines.	ESA/VLSI	2004	DBLP BibTeX RDF
14	Ethiopia Nigussie, Johanna Tuominen, Jouni Isoaho	Analyses of signaling techniques for self-timed systems.	SoC	2004	DBLP DOI BibTeX RDF