Search results for "ARC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Vasileios Tsoutsouras, Sotirios Xydis, Dimitrios Soudris, Leonidas Lymperopoulos	SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring.	ARC	2015	DBLP DOI BibTeX RDF
1	Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris, Jürgen Becker 0001	A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware.	ARC	2015	DBLP DOI BibTeX RDF
1	Kentaro Sano, Dimitrios Soudris, Michael Hübner 0001, Pedro C. Diniz (eds.)	Applied Reconfigurable Computing - 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings	ARC	2015	DBLP DOI BibTeX RDF
1	Dionysios Diamantopoulos, Sotirios Xydis, Kostas Siozios, Dimitrios Soudris	Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures.	ARC	2015	DBLP DOI BibTeX RDF
1	Stephan Nolting, Guillermo Payá Vayá, Florian Giesemann, Holger Blume	Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture.	ARC	2015	DBLP DOI BibTeX RDF
1	Michael Metzner, Jesus Lizarraga, Christophe Bobda	Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays.	ARC	2015	DBLP DOI BibTeX RDF
1	Zeyad Aklah, David Andrews 0001	A Flexible Multilayer Perceptron Co-processor for FPGAs.	ARC	2015	DBLP DOI BibTeX RDF
1	Lucas A. Tambara, Felipe Almeida, Paolo Rech, Fernanda Lima Kastensmidt, Giovanni Bruni, Christopher Frost 0002	Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects.	ARC	2015	DBLP DOI BibTeX RDF
1	Xerach Peña, Fernando Rincón, Julio Dondo, Julián Caba, Juan Carlos López 0001	Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components.	ARC	2015	DBLP DOI BibTeX RDF
1	Philipp Gorski, Tim Wegner, Dirk Timmermann	Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip.	ARC	2015	DBLP DOI BibTeX RDF
1	Kostas Siozios, Peter Figuli, Harry Sidiropoulos, Carsten Tradowsky, Dionysios Diamantopoulos, Konstantinos Maragos 0001, Shalina Percy Delicia, Dimitrios Soudris, Jürgen Becker 0001	TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools.	ARC	2015	DBLP DOI BibTeX RDF
1	Ernesto Villegas Castillo, Gabriele Miorandi, Davide Bertozzi, Jiang Chau Wang	DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost.	ARC	2015	DBLP DOI BibTeX RDF
1	Markus Happe, Andreas Traber, Ariane Keller	Preemptive Hardware Multitasking in ReconOS.	ARC	2015	DBLP DOI BibTeX RDF
1	Andreas Raptopoulos, Sotirios Xydis, Dimitrios Soudris	Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach.	ARC	2015	DBLP DOI BibTeX RDF
1	Nele Mentens, Jochen Vandorpe, Jo Vliegen, An Braeken, Bruno da Silva 0001, Abdellah Touhafi, Alois Kern, Stephan Knappmann, Jens Rettkowski, Muhammed Al Kadi, Diana Göhringer, Michael Hübner 0001	DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications.	ARC	2015	DBLP DOI BibTeX RDF
1	Anupam Chattopadhyay, Xiaolin Chen	A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures.	ARC	2015	DBLP DOI BibTeX RDF
1	Ekawat Homsirikamol, Kris Gaj	Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study.	ARC	2015	DBLP DOI BibTeX RDF
1	Maikon Adiles Fernandez Bueno, Carlos R. P. Almeida Jr., José A. M. de Holanda, Eduardo Marques	Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs.	ARC	2015	DBLP DOI BibTeX RDF
1	Bilal Habib, Jens-Peter Kaps, Kris Gaj	Efficient SR-Latch PUF.	ARC	2015	DBLP DOI BibTeX RDF
1	George Lentaris, Ioannis Stamoulias, Dionysios Diamantopoulos, Konstantinos Maragos 0001, Kostas Siozios, Dimitrios Soudris, Marcos Avilés Rodrigálvarez, Manolis I. A. Lourakis, Xenophon Zabulis, Ioannis Kostavelis, Lazaros Nalpantidis, Evangelos Boukas, Antonios Gasteratos	SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms.	ARC	2015	DBLP DOI BibTeX RDF
1	Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano, Hitoshi Murai, Masayuki Umemura, Mitsuhisa Sato	Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing.	ARC	2015	DBLP DOI BibTeX RDF
1	Giuseppe Massari, Edoardo Paone, Michele Scandale, Patrick Bellasi, Gianluca Palermo, Vittorio Zaccaria, Giovanni Agosta, William Fornaciari, Cristina Silvano	Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures.	ARC	2014	DBLP DOI BibTeX RDF
1	Tassadaq Hussain, Oscar Palomar, Osman S. Ünsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Amna Haider	Stand-Alone Memory Controller for Graphics System.	ARC	2014	DBLP DOI BibTeX RDF
1	Ihsen Alouani, Mazen A. R. Saghir, Smaïl Niar	ARABICA: A Reconfigurable Arithmetic Block for ISA Customization.	ARC	2014	DBLP DOI BibTeX RDF
1	Neil Scicluna, Christos-Savvas Bouganis	FPGA-Based Parallel DBSCAN Architecture.	ARC	2014	DBLP DOI BibTeX RDF
1	Pascal Sasdrich, Tim Güneysu	Efficient Elliptic-Curve Cryptography Using Curve25519 on Reconfigurable Devices.	ARC	2014	DBLP DOI BibTeX RDF
1	Chao Wang 0003, Xi Li 0003, Huizhen Zhang, Liang Shi, Xuehai Zhou	Instruction Extension and Generation for Adaptive Processors.	ARC	2014	DBLP DOI BibTeX RDF
1	Umar Ibrahim Minhas, Samuel Bayliss, George A. Constantinides	GPU vs FPGA: A Comparative Analysis for Non-standard Precision.	ARC	2014	DBLP DOI BibTeX RDF
1	Takashi Yoza, Minoru Watanabe	Enhanced Radiation Tolerance of an Optically Reconfigurable Gate Array by Exploiting an Inversion/Non-inversion Implementation.	ARC	2014	DBLP DOI BibTeX RDF
1	Jecel Mattos de Assumpção Jr., Merik Voswinkel, Eduardo Marques	Adapting Processor Grain via Reconfiguration.	ARC	2014	DBLP DOI BibTeX RDF
1	Rui Policarpo Duarte, Christos-Savvas Bouganis	A Unified Framework for Over-Clocking Linear Projections on FPGAs under PVT Variation.	ARC	2014	DBLP DOI BibTeX RDF
1	Jie Li 0004, Amin Salighehdar, Narayan Ganesan	Simulation of Complex Biochemical Pathways in 3D Process Space via Heterogeneous Computing Platform: Preliminary Results.	ARC	2014	DBLP DOI BibTeX RDF
1	Rinse Wester, Jan Kuper	Design Space Exploration of a Particle Filter Using Higher-Order Functions.	ARC	2014	DBLP DOI BibTeX RDF
1	Kaoru Hamasaki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri	FPGA Implementation of a Video Based Abnormal Action Detection System with Real-Time Cubic Higher Order Local Auto-Correlation Analysis.	ARC	2014	DBLP DOI BibTeX RDF
1	B. Chagun Basha, Stanislaw J. Piestrak, Sébastien Pillement	Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs.	ARC	2014	DBLP DOI BibTeX RDF
1	Christopher Pöpper, Oliver Mischke, Tim Güneysu	MicroACP - A Fast and Secure Reconfigurable Asymmetric Crypto-Processor - -Overhead Evaluation of Side-Channel Countermeasures-.	ARC	2014	DBLP DOI BibTeX RDF
1	Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado	Accelerating Heap-Based Priority Queue in Image Coding Application Using Parallel Index-Aware Tree Access.	ARC	2014	DBLP DOI BibTeX RDF
1	Enrique Sedano, Daniel Ménard, Juan A. López	Automated Data Flow Graph Partitioning for a Hierarchical Approach to Wordlength Optimization.	ARC	2014	DBLP DOI BibTeX RDF
1	Tobias Kenter, Gavin Vaz, Christian Plessl	Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.	ARC	2014	DBLP DOI BibTeX RDF
1	Ali Asghar, Husain Parvez	Diffusion-Based Placement Algorithm for Reducing High Interconnect Demand in Congested Regions of FPGAs.	ARC	2014	DBLP DOI BibTeX RDF
1	José Gabriel F. Coutinho, Oliver Pell, Eoghan O'Neill, Peter Sanders 0002, John McGlone, Paul Grigoras, Wayne Luk, Carmelo Ragusa	HARNESS Project: Managing Heterogeneous Computing Resources for a Cloud Platform.	ARC	2014	DBLP DOI BibTeX RDF
1	Sebastian Meisner, Marco Platzner	Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection.	ARC	2014	DBLP DOI BibTeX RDF
1	Eddie Hung, Jeffrey B. Goeders, Steven J. E. Wilton	Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry.	ARC	2014	DBLP DOI BibTeX RDF
1	Diana Goehringer, Marco Domenico Santambrogio, João M. P. Cardoso, Koen Bertels (eds.)	Reconfigurable Computing: Architectures, Tools, and Applications - 10th International Symposium, ARC 2014, Vilamoura, Portugal, April 14-16, 2014. Proceedings	ARC	2014	DBLP DOI BibTeX RDF
1	Jalal Khalifat, Ali Ebrahim, Tughrul Arslan	An Efficient Implementation of the Adams-Hamilton's Demosaicing Algorithm in FPGAs.	ARC	2014	DBLP DOI BibTeX RDF
1	Gianluca Durelli, Marcello Coppola, Karim Djafarian, George Kornaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, Cristiana Bolchini	SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.	ARC	2014	DBLP DOI BibTeX RDF
1	Ioannis Sourdis, Christos Strydis, Antonino Armato, Christos-Savvas Bouganis, Babak Falsafi, Georgi Nedeltchev Gaydadjiev, Sebastián Isaza, Alirad Malek, R. Mariani, Samuel N. Pagliarini, Dionisios N. Pnevmatikatos, Dhiraj K. Pradhan, Gerard K. Rauwerda, Robert M. Seepers, Rishad Ahmed Shafik, Georgios Smaragdos, Dimitris Theodoropoulos, Stavros Tzilis, Michalis Vavouras	DeSyRe: On-Demand Adaptive and Reconfigurable Fault-Tolerant SoCs.	ARC	2014	DBLP DOI BibTeX RDF
1	Carsten Tradowsky, Martin Schreiber 0001, Malte Vesper, Ivan Domladovec, Maximilian Braun, Hans-Joachim Bungartz, Jürgen Becker 0001	Towards Dynamic Cache and Bandwidth Invasion.	ARC	2014	DBLP DOI BibTeX RDF
1	Pablo Calleja, Gabriel Caffarena, Ana Iriarte	FPGA Design of Delay-Based Digital Effects for Electric Guitar.	ARC	2014	DBLP DOI BibTeX RDF
1	Zdravko Panjkov, Juergen Haas, Martin Aigner 0002, Herbert Rosmanith, Tianlun Liu, Roland Poppenreiter, Andreas Wasserbauer, Richard Hagelauer	OCP2XI Bridge: An OCP to AXI Protocol Bridge.	ARC	2014	DBLP DOI BibTeX RDF
1	Alexander Wold, Andreas Agne, Jim Tørresen	Relocatable Hardware Threads in Run-Time Reconfigurable Systems.	ARC	2014	DBLP DOI BibTeX RDF
1	Joonseok Park, Pedro C. Diniz	Evaluating High-Level Program Invariants Using Reconfigurable Hardware.	ARC	2014	DBLP DOI BibTeX RDF
1	Jürgen Becker 0001, Thomas Bruckschlögl, Oliver Oey, Timo Stripf, George Goulas, Nick Raptis, Christos Valouxis, Panayiotis Alefragis, Nikolaos S. Voros, Christos Gogos	Profile-Guided Compilation of Scilab Algorithms for Multiprocessor Systems.	ARC	2014	DBLP DOI BibTeX RDF
1	Taimour Wehbe, Xiaofang Wang	Efficient Buffer Design and Implementation for Wormhole Routers on FPGAs.	ARC	2014	DBLP DOI BibTeX RDF
1	Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez	FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm.	ARC	2014	DBLP DOI BibTeX RDF
1	Dionisios N. Pnevmatikatos, Tobias Becker, Andreas Brokalakis, Georgi Nedeltchev Gaydadjiev, Wayne Luk, Kyprianos Papadimitriou, Ioannis Papaefstathiou, Danilo Pau, Oliver Pell, Christian Pilato, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt	Effective Reconfigurable Design: The FASTER Approach.	ARC	2014	DBLP DOI BibTeX RDF
1	Karel Heyse, Dirk Stroobandt, Oliver Kadlcek, Oliver Pell	On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA's Configuration Infrastructure.	ARC	2014	DBLP DOI BibTeX RDF
1	Andreas Engel 0003, Andreas Koch 0001	Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks.	ARC	2014	DBLP DOI BibTeX RDF
1	Max Ferger, Michael Hübner 0001	Instruction Set Optimization for Application Specific Processors.	ARC	2014	DBLP DOI BibTeX RDF
1	Pascal Schleuniger, Sven Karlsson	A Synthesizable Multicore Platform for Microwave Imaging.	ARC	2014	DBLP DOI BibTeX RDF
1	Anja Niedermeier, Jan Kuper, Gerard J. M. Smit	A Dataflow Inspired Programming Paradigm for Coarse-Grained Reconfigurable Arrays.	ARC	2014	DBLP DOI BibTeX RDF
1	Kiran Kumar Matam, Viktor K. Prasanna	Algorithm Design Methodology for Embedded Architectures.	ARC	2013	DBLP DOI BibTeX RDF
1	Shane T. Fleming, David B. Thomas	Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields.	ARC	2013	DBLP DOI BibTeX RDF
1	Youenn Corre, Jean-Philippe Diguet, Loïc Lagadec, Dominique Heller, Dominique Blouin	Fast Template-Based Heterogeneous MPSoC Synthesis on FPGA.	ARC	2013	DBLP DOI BibTeX RDF
1	Gabriel Nunez, Evan Tsai, Airs Lin, Aleksander Milshteyn, Garth Herman, Helen Boussalis, Charles Liu	High Level FPGA Modeling of an JPEG Encoder.	ARC	2013	DBLP DOI BibTeX RDF
1	Vitor Gomes 0001, Haroldo Fraga de Campos Velho, Andrea Charão	A Fast Poisson Solver for Hybrid Reconfigurable System.	ARC	2013	DBLP DOI BibTeX RDF
1	Geoffrey Ottoy, Bart Preneel, Jean-Pierre Goemaere, Lieven De Strycker	Flexible Design of a Modular Simultaneous Exponentiation Core for Embedded Platforms.	ARC	2013	DBLP DOI BibTeX RDF
1	Qingshan Tang, Matthieu Tuna, Zied Marrakchi, Habib Mehrez	Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist.	ARC	2013	DBLP DOI BibTeX RDF
1	Uli Kretzschmar, Armando Astarloa, Jesús Lázaro 0001	SEU Resilience of DES, AES and Twofish in SRAM-Based FPGA.	ARC	2013	DBLP DOI BibTeX RDF
1	Christopher J. Martinez	Teaching SoC Using Video Games to Improve Student Engagement.	ARC	2013	DBLP DOI BibTeX RDF
1	Fakhar Anjam, Stephan Wong	Configurable Fault-Tolerance for a Configurable VLIW Processor.	ARC	2013	DBLP DOI BibTeX RDF
1	Qi Guo, Chao Wang 0003, Xuehai Zhou, Xi Li 0003	Pipeline Optimization for Loops on Reconfigurable Platform.	ARC	2013	DBLP DOI BibTeX RDF
1	Stephan Wong	Embedded Reconfigurable Architectures.	ARC	2013	DBLP DOI BibTeX RDF
1	Sam Skalicky, Sonia López, Marcin Lukowiak, James Letendre, Matthew Ryan	Performance Modeling of Pipelined Linear Algebra Architectures on FPGAs.	ARC	2013	DBLP DOI BibTeX RDF
1	Li Zhou, Dongpei Liu, Botao Zhang, Hengzhu Liu	Ant Colony Optimization for Application Mapping in Coarse-Grained Reconfigurable Array.	ARC	2013	DBLP DOI BibTeX RDF
1	Christos P. Antonopoulos, George Krikis, Nikolaos S. Voros	Efficient Hardware Based Security Algorithm Implementation for WSN Medical Applications: The ARMOR Perspective.	ARC	2013	DBLP DOI BibTeX RDF
1	Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso	Architecture for Transparent Binary Acceleration of Loops with Memory Accesses.	ARC	2013	DBLP DOI BibTeX RDF
1	Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto	Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-Based Custom Computing.	ARC	2013	DBLP DOI BibTeX RDF
1	Philip Brisk, José Gabriel F. Coutinho, Pedro C. Diniz (eds.)	Reconfigurable Computing: Architectures, Tools and Applications - 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013. Proceedings	ARC	2013	DBLP DOI BibTeX RDF
1	Takuya Kuhara, Takaaki Miyajima, Masato Yoshimi, Hideharu Amano	An FPGA Acceleration for the Kd-tree Search in Photon Mapping.	ARC	2013	DBLP DOI BibTeX RDF
1	Yuya Shirahashi, Minoru Watanabe	Dependability-Increasing Method of Processors under a Space Radiation Environment.	ARC	2013	DBLP DOI BibTeX RDF
1	James Arram, Kuen Hung Tsoi, Wayne Luk, Peiyong Jiang	Hardware Acceleration of Genetic Sequence Alignment.	ARC	2013	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura	An Architecture for IPv6 Lookup Using Parallel Index Generation Units.	ARC	2013	DBLP DOI BibTeX RDF
1	Mohammed A. S. Abdallah	FPGA-Based Adaptive Data Acquisition Scheduler-on-Chip (SchoC) for Heterogeneous Signals.	ARC	2013	DBLP DOI BibTeX RDF
1	Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez	Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA.	ARC	2013	DBLP DOI BibTeX RDF
1	Maciej Kurek, Tobias Becker, Wayne Luk	Parametric Optimization of Reconfigurable Designs Using Machine Learning.	ARC	2013	DBLP DOI BibTeX RDF
1	Jingfei Jiang, Rongdong Hu, Mikel Luján, Yong Dou	Empirical Evaluation of Fixed-Point Arithmetic for Deep Belief Networks.	ARC	2013	DBLP DOI BibTeX RDF
1	Aurelio Morales-Villanueva, Ann Gordon-Ross	HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs.	ARC	2013	DBLP DOI BibTeX RDF
1	José Gabriel F. Coutinho, João M. P. Cardoso, Tiago Carvalho, Ricardo Nobre, Sujit Bhattacharya 0002, Pedro C. Diniz, Liam Fitzpatrick, Razvan Nane	Deriving Resource Efficient Designs Using the REFLECT Aspect-Oriented Approach - (Extended Abstract).	ARC	2013	DBLP DOI BibTeX RDF
1	Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, Masato Motomura	C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join.	ARC	2013	DBLP DOI BibTeX RDF
1	Debora Matos, Cezar Reinbrecht, Márcio Eduardo Kreutz, Gianluca Palermo, Luigi Carro, Altamiro Amadeu Susin	Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability.	ARC	2013	DBLP DOI BibTeX RDF
1	George Goulas, Christos Gogos, Christos Valouxis, Panayiotis Alefragis, Nikolaos S. Voros	Coarse Grained Parallelism Optimization for Multicore Architectures: The ALMA Project Approach.	ARC	2013	DBLP DOI BibTeX RDF
1	Thomas C. P. Chau, Xinyu Niu, Alison Eele, Wayne Luk, Peter Y. K. Cheung, Jan M. Maciejowski	Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications.	ARC	2013	DBLP DOI BibTeX RDF
1	Jon T. Butler, Tsutomu Sasao	Hardware Index to Set Partition Converter.	ARC	2013	DBLP DOI BibTeX RDF
1	Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid	Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform.	ARC	2013	DBLP DOI BibTeX RDF
1	Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano	Cost Effective Implementation of Flux Limiter Functions Using Partial Reconfiguration.	ARC	2012	DBLP DOI BibTeX RDF
1	Fakhar Anjam, Quan Kong, Roel Seedorf, Stephan Wong	A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor.	ARC	2012	DBLP DOI BibTeX RDF
1	Xuan You Tan, David Boland, George A. Constantinides	FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores.	ARC	2012	DBLP DOI BibTeX RDF
1	Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang 0002, Jinian Bian	PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs.	ARC	2012	DBLP DOI BibTeX RDF
1	Qiang Liu 0011, Wayne Luk	Heterogeneous Systems for Energy Efficient Scientific Computing.	ARC	2012	DBLP DOI BibTeX RDF

Publications at "ARC"( http://dblp.L3S.de/Venues/ARC )