Search results for "ARC"

Hits ?▲	Authors	Title	Venue	Year	Link
28	Nadir Khan, Arthur Silitonga, Brian Pachideh, Sven Nitzsche, Jürgen Becker 0001	Secure Local Configuration of Intellectual Property Without a Trusted Third Party.	ARC	2019	DBLP DOI BibTeX RDF
28	Johanna Rohde, Lukas Johannes Jung, Christian Hochberger	Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators.	ARC	2019	DBLP DOI BibTeX RDF
28	Tiago Peres, Ana Gonçalves, Mário P. Véstias	Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning.	ARC	2019	DBLP DOI BibTeX RDF
28	Helena Cruz, Rui Policarpo Duarte, Horácio C. Neto	Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging.	ARC	2019	DBLP DOI BibTeX RDF
28	Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, H. Peter Hofstee, Zaid Al-Ars	Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow.	ARC	2019	DBLP DOI BibTeX RDF
28	Masayuki Shimoda, Youki Sada, Hiroki Nakahara	Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation.	ARC	2019	DBLP DOI BibTeX RDF
28	André Werner 0001, Florian Fricke, Keyvan Shahin, Florian Werner 0002, Michael Hübner 0001	Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms.	ARC	2019	DBLP DOI BibTeX RDF
28	Kenneth Schmitz, Buse Ustaoglu, Daniel Große, Rolf Drechsler	(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs.	ARC	2019	DBLP DOI BibTeX RDF
28	Bruno da Silva 0001, An Braeken, Abdellah Touhafi	Probabilistic Performance Modelling when Using Partial Reconfiguration to Accelerate Streaming Applications with Non-deterministic Task Scheduling.	ARC	2019	DBLP DOI BibTeX RDF
28	Afonso Canas Ferreira, João M. P. Cardoso	Graph-Based Code Restructuring Targeting HLS for FPGAs.	ARC	2019	DBLP DOI BibTeX RDF
28	Brent E. Nelson	Third Party CAD Tools for FPGA Design - A Survey of the Current Landscape.	ARC	2019	DBLP DOI BibTeX RDF
28	Nikolaos S. Voros, Michael Hübner 0001, Georgios Keramidas, Diana Goehringer, Christos P. Antonopoulos, Pedro C. Diniz (eds.)	Applied Reconfigurable Computing. Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings	ARC	2018	DBLP DOI BibTeX RDF
28	Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung	Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic.	ARC	2018	DBLP DOI BibTeX RDF
28	Peter Littlewood, Shahnam Mirzaei, Krishna Murthy Kattiyan Ramamoorthy	Reconfigurable IP-Based Spectral Interference Canceller.	ARC	2018	DBLP DOI BibTeX RDF
28	Christos P. Antonopoulos, Georgios Keramidas, Nikolaos S. Voros, Michael Hübner 0001, Fynn Schwiegelshohn, Diana Goehringer, Maria Dagioglou, Georgios Stavrinos, Stasinos Konstantopoulos, Vangelis Karkaletsis	Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Experience.	ARC	2018	DBLP DOI BibTeX RDF
28	Paulo Garcia, Deepayan Bhowmik, Andrew M. Wallace, Robert J. Stewart 0001, Greg Michaelson	Area-Energy Aware Dataflow Optimisation of Visual Tracking Systems.	ARC	2018	DBLP DOI BibTeX RDF
28	Augusto W. Hoppe, Fernanda Lima Kastensmidt, Jürgen Becker 0001	Control Flow Analysis for Embedded Multi-core Hybrid Systems.	ARC	2018	DBLP DOI BibTeX RDF
28	Kalindu Herath, Alok Prakash, Thambipillai Srikanthan	Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network.	ARC	2018	DBLP DOI BibTeX RDF
28	Nikolaos Tzanis, Grigorios Proiskos, Michael K. Birbas, Alexios N. Birbas	FPGA-Assisted Distribution Grid Simulator.	ARC	2018	DBLP DOI BibTeX RDF
28	Sikandar Khan, Kyprianos Papadimitriou, Giorgio C. Buttazzo, Kostas Kalaitzakis	A Reconfigurable PID Controller.	ARC	2018	DBLP DOI BibTeX RDF
28	Jiang Su, Julian Faraone, Junyi Liu, Yiren Zhao, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung	Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification.	ARC	2018	DBLP DOI BibTeX RDF
28	Masahiro Fukuda, Yasushi Inoguchi	FPGA-Based Parallel Pattern Matching.	ARC	2018	DBLP DOI BibTeX RDF
28	Björn Liebig, Julian Oppermann, Oliver Sinnen, Andreas Koch 0001	Improved High-Level Synthesis for Complex CellML Models.	ARC	2018	DBLP DOI BibTeX RDF
28	Gennaro Severino Rodrigues, Ádria Barros de Oliveira, Fernanda Lima Kastensmidt, Alberto Bosio	Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs.	ARC	2018	DBLP DOI BibTeX RDF
28	Ahmad Sadek, Ananya Muddukrishna, Lester Kalms, Asbjørn Djupdal, Ariel Podlubne, Antonio Paolillo, Diana Goehringer, Magnus Jahre	Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview.	ARC	2018	DBLP DOI BibTeX RDF
28	Tim Hansmeier, Marco Platzner, David Andrews 0001	An FPGA/HMC-Based Accelerator for Resolution Proof Checking.	ARC	2018	DBLP DOI BibTeX RDF
28	Kamil Piszczek, Piotr Janus, Tomasz Kryjak	The Use of HACP+SBT Lossless Compression in Optimizing Memory Bandwidth Requirement for Hardware Implementation of Background Modelling Algorithms.	ARC	2018	DBLP DOI BibTeX RDF
28	Jeckson Dellagostin Souza, Anderson Luiz Sartor, Luigi Carro, Mateus Beck Rutzig, Stephan Wong, Antonio C. S. Beck	DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability.	ARC	2018	DBLP DOI BibTeX RDF
28	Milind Parelkar, Darshan Jetly	High Performance UDP/IP 40Gb Ethernet Stack for FPGAs.	ARC	2018	DBLP DOI BibTeX RDF
28	Fabio Benevenuti, Fernanda Lima Kastensmidt	Analyzing AXI Streaming Interface for Hardware Acceleration in AP-SoC Under Soft Errors.	ARC	2018	DBLP DOI BibTeX RDF
28	Junsik Kim 0004, Jaehyun Park 0003	FPGA-Based Memory Efficient Shift-And Algorithm for Regular Expression Matching.	ARC	2018	DBLP DOI BibTeX RDF
28	Augusto G. Erichsen, Anderson Luiz Sartor, Jeckson Dellagostin Souza, Monica Magalhães Pereira, Stephan Wong, Antonio C. S. Beck	ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores.	ARC	2018	DBLP DOI BibTeX RDF
28	Lukas Johannes Jung, Christian Hochberger	Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling.	ARC	2018	DBLP DOI BibTeX RDF
28	Bruno da Silva 0001, Laurent Segers, An Braeken, Kris Steenhaut, Abdellah Touhafi	A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks.	ARC	2018	DBLP DOI BibTeX RDF
28	Kazuei Hironaka, Ng. Anh Vu Doan, Hideharu Amano	Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study.	ARC	2018	DBLP DOI BibTeX RDF
28	Uzaif Sharif, Shahnam Mirzaei	High Level Synthesis Implementation of Object Tracking Algorithm on Reconfigurable Hardware.	ARC	2018	DBLP DOI BibTeX RDF
28	Konstantinos Katsantonis, Christoforos Kachris, Dimitrios Soudris	Efficient Hardware Acceleration of Recommendation Engines: A Use Case on Collaborative Filtering.	ARC	2018	DBLP DOI BibTeX RDF
28	Panayiotis Alefragis, George Theodoridis, Merkourios Katsimpris, Christos Valouxis, Christos Gogos, George Goulas, Nikolaos S. Voros, Simon Reder, Koray Kasnakli, Marcus Bednara, David Müller 0005, Umut Durak, Jürgen Becker 0001	Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach.	ARC	2018	DBLP DOI BibTeX RDF
28	Mário Lopes Ferreira, João Canas Ferreira, Michael Hübner 0001	A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems.	ARC	2018	DBLP DOI BibTeX RDF
28	Kazusa Musha, Tomohiro Kudoh, Hideharu Amano	Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud.	ARC	2018	DBLP DOI BibTeX RDF
28	Raheel Afsharmazayejani, Fahimeh Yazdanpanah, Amin Rezaei 0001, Mohammad Alaei, Masoud Daneshtalab	HoneyWiN: Novel Honeycomb-Based Wireless NoC Architecture in Many-Core Era.	ARC	2018	DBLP DOI BibTeX RDF
28	Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima	Efficient Multitasking on FPGA Using HDL-Based Checkpointing.	ARC	2018	DBLP DOI BibTeX RDF
28	Panagiotis G. Mousouliotis, Loukas P. Petrou	SqueezeJet: High-Level Synthesis Accelerator Design for Deep Convolutional Neural Networks.	ARC	2018	DBLP DOI BibTeX RDF
28	Osvaldo Navarro, Michael Hübner 0001	Runtime Adaptive Cache for the LEON3 Processor.	ARC	2018	DBLP DOI BibTeX RDF
28	Christoforos Kachris, Ioannis Stamelos, Elias Koromilas, Dimitrios Soudris	Seamless FPGA Deployment over Spark in Cloud Computing: A Use Case on Machine Learning Hardware Acceleration.	ARC	2018	DBLP DOI BibTeX RDF
28	Pavlos Malakonakis, Konstantinos Georgopoulos, Aggelos Ioannou, Luciano Lavagno, Ioannis Papaefstathiou, Iakovos Mavroidis	HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALE.	ARC	2018	DBLP DOI BibTeX RDF
28	Ayan Palchaudhuri, Anindya Sundar Dhar	Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs.	ARC	2018	DBLP DOI BibTeX RDF
28	Michalis Rizakis, Stylianos I. Venieris, Alexandros Kouris, Christos-Savvas Bouganis	Approximate FPGA-Based LSTMs Under Computation Time Constraints.	ARC	2018	DBLP DOI BibTeX RDF
28	Santhi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy 0001	ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs.	ARC	2018	DBLP DOI BibTeX RDF
28	Johannes Pfau, Shalina Percy Delicia Figuli, Steffen Bähr, Jürgen Becker 0001	Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems.	ARC	2018	DBLP DOI BibTeX RDF
28	Christos P. Antonopoulos, Konstantinos Antonopoulos, Christos Panagiotou, Nikolaos S. Voros	Tackling Wireless Sensor Network Heterogeneity Through Novel Reconfigurable Gateway Approach.	ARC	2018	DBLP DOI BibTeX RDF
28	Almabrok Abdoalnasir, Mihalis Psarakis, Anastasios I. Dounis	An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization Algorithm.	ARC	2018	DBLP DOI BibTeX RDF
28	Oguzhan Sezenlik, Sebastian Schüller, Joachim K. Anlauf	VerCoLib: Fast and Versatile Communication for FPGAs via PCI Express.	ARC	2018	DBLP DOI BibTeX RDF
28	Pedro Henrique Exenberger Becker, Anderson Luiz Sartor, Marcelo Brandalero, Tiago Trevisan Jost, Stephan Wong, Luigi Carro, Antonio C. S. Beck	A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs.	ARC	2018	DBLP DOI BibTeX RDF
28	Benedikt Janßen, Florian Kästner, Tim Wingender, Michael Hübner 0001	A Dynamic Partial Reconfigurable Overlay Framework for Python.	ARC	2018	DBLP DOI BibTeX RDF
28	Kris Heid, Jakob Wenzel 0002, Christian Hochberger	Fast DSE for Automated Parallelization of Embedded Legacy Applications.	ARC	2018	DBLP DOI BibTeX RDF
28	Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy 0001, Ranjani Narayan	Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design.	ARC	2018	DBLP DOI BibTeX RDF
28	Florian Fricke, André Werner 0001, Keyvan Shahin, Michael Hübner 0001	CGRA Tool Flow for Fast Run-Time Reconfiguration.	ARC	2018	DBLP DOI BibTeX RDF
28	Deepayan Bhowmik, Kofi Appiah	Embedded Vision Systems: A Review of the Literature.	ARC	2018	DBLP DOI BibTeX RDF
28	Umar Ibrahim Minhas, Roger F. Woods, George Karakonstantis	Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent Optimizations.	ARC	2018	DBLP DOI BibTeX RDF
28	Jürgen Becker 0001, Falco K. Bapp	The ARAMiS Project Initiative - Multicore Systems in Safety- and Mixed-Critical Applications.	ARC	2018	DBLP DOI BibTeX RDF
28	Jens Rettkowski, Diana Goehringer	High-Level Synthesis of Software-Defined MPSoCs.	ARC	2018	DBLP DOI BibTeX RDF
28	Habib ul Hasan Khan, Ahmed Kamal, Diana Goehringer	An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded Processors.	ARC	2018	DBLP DOI BibTeX RDF
28	Emmanuel Ofori-Attah, Xiaohang Wang 0001, Michael Opoku Agyeman	A Survey of Low Power Design Techniques for Last Level Caches.	ARC	2018	DBLP DOI BibTeX RDF
28	Rafael Fão de Moura, Michael Guilherme Jordan, Antonio Carlos Schneider Beck, Mateus Beck Rutzig	Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture.	ARC	2018	DBLP DOI BibTeX RDF
28	Santhi Natarajan, N. Krishna Kumar, H. V. Anuchan, Debnath Pal, S. K. Nandy 0001	ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads.	ARC	2018	DBLP DOI BibTeX RDF
28	Luca Sterpone, Ludovica Bozzoli	Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach.	ARC	2018	DBLP DOI BibTeX RDF
28	Lampros Pyrgas, Paris Kitsos	A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip Sensing.	ARC	2018	DBLP DOI BibTeX RDF
28	Konstantinos Georgopoulos, Pavlos Malakonakis, Nikolaos Tampouratzis, Antonis Nikitakis, Grigorios Chrysos 0001, Apostolos Dollas, Dionysios N. Pnevmatikatos, Ioannis Papaefstathiou	Comparing C and SystemC Based HLS Methods for Reconfigurable Systems Design.	ARC	2018	DBLP DOI BibTeX RDF
28	Julián Caba, João M. P. Cardoso, Fernando Rincón, Julio Dondo, Juan Carlos López 0001	Rapid Prototyping and Verification of Hardware Modules Generated Using HLS.	ARC	2018	DBLP DOI BibTeX RDF
28	Zhenhua Guo 0003, Baoyu Fan, Yaqian Zhao, Xuelei Li, Shixin Wei, Long Li 0006	An OpenCLTM Implementation of WebP Accelerator on FPGAs.	ARC	2018	DBLP DOI BibTeX RDF
28	Stephan Wong, Antonio Carlos Schneider Beck, Koen Bertels, Luigi Carro (eds.)	Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings	ARC	2017	DBLP DOI BibTeX RDF
28	Muhammad Adeel Pasha, Umer Farooq 0001, Muhammad Ali, Bilal Siddiqui	A Framework for High Level Simulation and Optimization of Coarse-Grained Reconfigurable Architectures.	ARC	2017	DBLP DOI BibTeX RDF
28	Sensen Hu, Anthony Brandon, Qi Guo, Yizhuo Wang	Improving the Performance of Adaptive Cache in Reconfigurable VLIW Processor.	ARC	2017	DBLP DOI BibTeX RDF
28	Paul Grigoras, Pavel Burovskiy, James Arram, Xinyu Niu, Kit Cheung, Junyi Xie, Wayne Luk	dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs.	ARC	2017	DBLP DOI BibTeX RDF
28	Geraldo F. Oliveira, Paulo C. Santos 0001, Marco A. Z. Alves, Luigi Carro	NIM: An HMC-Based Machine for Neuron Computation.	ARC	2017	DBLP DOI BibTeX RDF
28	Osvaldo Navarro, Jones Yudi Mori, Javier Hoffmann, Fabian Stuckmann, Michael Hübner 0001	A Machine Learning Methodology for Cache Recommendation.	ARC	2017	DBLP DOI BibTeX RDF
28	Ngoc-Hung Nguyen, Sheraz Ali Khan, Cheol Hong Kim, Jong-Myon Kim	An FPGA-Based Implementation of a Pipelined FFT Processor for High-Speed Signal Processing Applications.	ARC	2017	DBLP DOI BibTeX RDF
28	Ruizhe Zhao, Xinyu Niu, Yajie Wu, Wayne Luk, Qiang Liu 0011	Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms.	ARC	2017	DBLP DOI BibTeX RDF
28	Ádria Barros de Oliveira, Lucas Antunes Tambara, Fernanda Lima Kastensmidt	Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC.	ARC	2017	DBLP DOI BibTeX RDF
28	Enrico Petraglio, Rick Wertenbroek, Flavio Capitao, Nicolas Guex, Christian Iseli, Yann Thoma	Genomic Data Clustering on FPGAs for Compression.	ARC	2017	DBLP DOI BibTeX RDF
28	Théotime Bollengier, Loïc Lagadec, Mohamad Najem, Jean-Christophe Le Lann, Pierre Guilloux	Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach.	ARC	2017	DBLP DOI BibTeX RDF
28	Peter Figuli, Weiqiao Ding, Shalina Percy Delicia Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker 0001	Parameter Sensitivity in Virtual FPGA Architectures.	ARC	2017	DBLP DOI BibTeX RDF
28	Matthias Göbel 0001, Ahmed Elhossini, Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink	A Quantitative Analysis of the Memory Architecture of FPGA-SoCs.	ARC	2017	DBLP DOI BibTeX RDF
28	Mustapha Bouhali, Farid Shamani, Zine Elabadine Dahmane, Abdelkader Belaidi, Jari Nurmi	FPGA Applications in Unmanned Aerial Vehicles - A Review.	ARC	2017	DBLP DOI BibTeX RDF
28	Dimple Sharma, Victor Dumitriu, Lev Kirischian	Architecture Reconfiguration as a Mechanism for Sustainable Performance of Embedded Systems in case of Variations in Available Power.	ARC	2017	DBLP DOI BibTeX RDF
28	Álvaro Avelino, Valentin Obac Roda, Naim Harb, Carlos Valderrama 0001, Glauberto Albuquerque, Paulo Da Cunha Possa	LP-P2IP: A Low-Power Version of P1IP Architecture Using Partial Reconfiguration.	ARC	2017	DBLP DOI BibTeX RDF
28	Karim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser	Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation.	ARC	2017	DBLP DOI BibTeX RDF
28	Andreas Fiessler, Daniel Loebenberger, Sven Hager, Björn Scheuermann 0001	On the Use of (Non-)Cryptographic Hashes on FPGAs.	ARC	2017	DBLP DOI BibTeX RDF
28	Abdul Rafay Khatri, Ali Hayek, Josef Börcsök	Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs.	ARC	2017	DBLP DOI BibTeX RDF
28	Joost Hoozemans, Rolf Heij, Jeroen van Straten, Zaid Al-Ars	VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications.	ARC	2017	DBLP DOI BibTeX RDF
28	Mostafa Morshedi, Hamid Noori	FPGA Implementation of a Short Read Mapping Accelerator.	ARC	2017	DBLP DOI BibTeX RDF
28	Habib ul Hasan Khan, Diana Göhringer	FPGA Debugging with MATLAB Using a Rule-Based Inference System.	ARC	2017	DBLP DOI BibTeX RDF
28	Nils Voss, Tobias Becker, Oskar Mencer, Georgi Gaydadjiev	Rapid Development of Gzip with MaxJ.	ARC	2017	DBLP DOI BibTeX RDF
28	Andreea-Ingrid Funie, Liucheng Guo, Xinyu Niu, Wayne Luk, Mark Salmon	Custom Framework for Run-Time Trading Strategies.	ARC	2017	DBLP DOI BibTeX RDF
28	Tomoya Fujii, Simpei Sato, Hiroki Nakahara, Masato Motomura	An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning.	ARC	2017	DBLP DOI BibTeX RDF
28	Jan Macheta, Agnieszka Dabrowska-Boruch, Pawel Russek, Kazimierz Wiatr	ArPALib: A Big Number Arithmetic Library for Hardware and Software Implementations. A Case Study for the Miller-Rabin Primality Test.	ARC	2017	DBLP DOI BibTeX RDF
28	Ruochun Jin, Jingfei Jiang, Yong Dou	Accuracy Evaluation of Long Short Term Memory Network Based Language Model with Fixed-Point Arithmetic.	ARC	2017	DBLP DOI BibTeX RDF
28	André Flores dos Santos, Lucas Antunes Tambara, Fabio Benevenuti, Jorge L. Tonfat, Fernanda Lima Kastensmidt	Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs.	ARC	2017	DBLP DOI BibTeX RDF
28	Christophe Bobda, Joshua Mead, Taylor J. L. Whitaker, Charles A. Kamhoua, Kevin A. Kwiat	Hardware Sandboxing: A Novel Defense Paradigm Against Hardware Trojans in Systems on Chip.	ARC	2017	DBLP DOI BibTeX RDF