Search results for "DFT"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Masoumeh Ebrahimi, Junshi Wang, Letian Huang, Masoud Daneshtalab, Axel Jantsch	Rescuing healthy cores against disabled routers.	DFT	2014	DBLP DOI BibTeX RDF
1	Pilin Junsangsri, Jie Han 0001, Fabrizio Lombardi	A system-level scheme for resistance drift tolerance of a multilevel phase change memory.	DFT	2014	DBLP DOI BibTeX RDF
1	Glenn H. Chapman, Rohit Thomas, Rahul Thomas, Israel Koren, Zahava Koren	Improved correction for hot pixels in digital imagers.	DFT	2014	DBLP DOI BibTeX RDF
1	Halit Dogan, Domenic Forte, Mark Mohammad Tehranipoor	Aging analysis for recycled FPGA detection.	DFT	2014	DBLP DOI BibTeX RDF
1	Paniz Foroutan, Mehdi Kamal, Zainalabedin Navabi	A heuristic path selection method for small delay defects test.	DFT	2014	DBLP DOI BibTeX RDF
1	Anup Das 0001, Akash Kumar 0001, Bharadwaj Veeravalli	Artificial intelligence based task mapping and pipelined scheduling for checkpointing on real time systems with imperfect fault detection.	DFT	2014	DBLP DOI BibTeX RDF
1	Mohammad Hashem Haghbayan, Bijan Alizadeh, Amir-Mohammad Rahmani, Pasi Liljeberg, Hannu Tenhunen	Automated formal approach for debugging dividers using dynamic specification.	DFT	2014	DBLP DOI BibTeX RDF
1		2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014	DFT	2014	DBLP BibTeX RDF
1	Paolo Bernardi, Riccardo Cantoro, Lyl M. Ciganda Brasca, Ernesto Sánchez 0001, Matteo Sonza Reorda, Sergio de Luca, Renato Meregalli, Alessandro Sansonetti	On the in-field functional testing of decode units in pipelined RISC processors.	DFT	2014	DBLP DOI BibTeX RDF
1	Md. Tauhidur Rahman 0001, Domenic Forte, Quihang Shi, Gustavo K. Contreras, Mark Mohammad Tehranipoor	CSST: Preventing distribution of unlicensed and rejected ICs by untrusted foundry and assembly.	DFT	2014	DBLP DOI BibTeX RDF
1	Jorge Semião, David Saraiva, Carlos Leong, André Romão, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	Performance sensor for tolerance and predictive detection of delay-faults.	DFT	2014	DBLP DOI BibTeX RDF
1	Shahrzad Keshavarz, Amirreza Nekooei, Zainalabedin Navabi	Preemptive multi-bit IJTAG testing with reconfigurable infrastructure.	DFT	2014	DBLP DOI BibTeX RDF
1	Martin Omaña 0001, Daniele Rossi 0001, Edda Beniamino, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche	Power droop reduction during Launch-On-Shift scan-based logic BIST.	DFT	2014	DBLP DOI BibTeX RDF
1	Stefano Di Carlo, Marco Indaco, Paolo Prinetto, Elena I. Vatajelu, Rosa Rodríguez-Montañés, Joan Figueras	Reliability estimation at block-level granularity of spin-transfer-torque MRAMs.	DFT	2014	DBLP DOI BibTeX RDF
1	Alirad Malek, Stavros Tzilis, Danish Anis Khan, Ioannis Sourdis, Georgios Smaragdos, Christos Strydis	A probabilistic analysis of resilient reconfigurable designs.	DFT	2014	DBLP DOI BibTeX RDF
1	Florian Haas, Sebastian Weis, Stefan Metzlaff, Theo Ungerer	Exploiting Intel TSX for fault-tolerant execution in safety-critical systems.	DFT	2014	DBLP DOI BibTeX RDF
1	Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Energy-efficient concurrent testing approach for many-core systems in the dark silicon age.	DFT	2014	DBLP DOI BibTeX RDF
1	Daniel A. G. de Oliveira, Paolo Rech, Laércio Lima Pilla, Philippe Olivier Alexandre Navaux, Luigi Carro	GPGPUs ECC efficiency and efficacy.	DFT	2014	DBLP DOI BibTeX RDF
1	Prashant D. Joshi, Said Hamdioui	Security methods in fault tolerant modified line graph based networks.	DFT	2014	DBLP DOI BibTeX RDF
1	Miao Tony He, Mohammad Tehranipoor	SAM: A comprehensive mechanism for accessing embedded sensors in modern SoCs.	DFT	2014	DBLP DOI BibTeX RDF
1	Bahareh J. Farahani, Saeed Safari	An instance-based SER analysis in the presence of PVTA variations.	DFT	2014	DBLP DOI BibTeX RDF
1	Prashant D. Joshi, Said Hamdioui	Shortest path reduction in a class of uniform fault tolerant networks.	DFT	2014	DBLP DOI BibTeX RDF
1	Bartolomeo Montrucchio, Maurizio Rebaudengo, Alejandro Velasco	Fault injection in the process descriptor of a Unix-based operating system.	DFT	2014	DBLP DOI BibTeX RDF
1	Tiago A. O. Alves, Leandro A. J. Marzulo, Sandip Kundu, Felipe Maia Galvão França	Domino effect protection on dataflow error detection and recovery.	DFT	2014	DBLP DOI BibTeX RDF
1	Senwen Kan, Jennifer Dworak	Triggering Trojans in SRAM circuits with X-propagation.	DFT	2014	DBLP DOI BibTeX RDF
1	Angelo Bacchini, Marco Rovatti, Gianluca Furano, Marco Ottavi	Characterization of data retention faults in DRAM devices.	DFT	2014	DBLP DOI BibTeX RDF
1	Hossein Sayadi, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Seyed Ghassem Miremadi	A data recomputation approach for reliability improvement of scratchpad memory in embedded systems.	DFT	2014	DBLP DOI BibTeX RDF
1	Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, Marvin Onabajo, Yong-Bin Kim	A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA.	DFT	2014	DBLP DOI BibTeX RDF
1	Chuanlei Zheng, Shuai Wang 0006	Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors.	DFT	2014	DBLP DOI BibTeX RDF
1	Manoj Kumar 0001, Vijay Laxmi, Manoj Singh Gaur, Masoud Daneshtalab, Masoumeh Ebrahimi, Mark Zwolinski	Fault tolerant and highly adaptive routing for 2D NoCs.	DFT	2014	DBLP DOI BibTeX RDF
1	Hassen Aziza, Haithem Ayari, Santhosh Onkaraiah, Jean-Michel Portal, Mathieu Moreau, Marc Bocquet	Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability.	DFT	2014	DBLP DOI BibTeX RDF
1	Wei Wei 0034, Fabrizio Lombardi, Kazuteru Namba	Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance.	DFT	2014	DBLP DOI BibTeX RDF
1	Richard A. Guinee	A novel pseudonoise tester for transmission line fault location and identification using pseudorandom binary sequences.	DFT	2012	DBLP DOI BibTeX RDF
1	Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Adrian Evans	Single event upset tolerance in flip-flop based microprocessor cores.	DFT	2012	DBLP DOI BibTeX RDF
1	Sreenivas Gangadhar, Spyros Tragoudas	Accurate calculation of SET propagation probability for hardening.	DFT	2012	DBLP DOI BibTeX RDF
1	Linus Feiten, Matthias Sauer 0002, Tobias Schubert 0001, Alexander Czutro, Eberhard Böhl, Ilia Polian, Bernd Becker 0001	#SAT-based vulnerability analysis of security components - A case study.	DFT	2012	DBLP DOI BibTeX RDF
1	Oscar Acevedo, Dimitri Kagaris	Using the Berlekamp-Massey algorithm to obtain LFSR characteristic polynomials for TPG.	DFT	2012	DBLP DOI BibTeX RDF
1	Yang Lu, Fabrizio Lombardi, Salvatore Pontarelli, Marco Ottavi	On the design of two single event tolerant slave latches for scan delay testing.	DFT	2012	DBLP DOI BibTeX RDF
1	Tomohiro Yoneda, Masashi Imai	Dependable routing in multi-chip NoC platforms for automotive applications.	DFT	2012	DBLP DOI BibTeX RDF
1	Ali Arabi M. Shahi, Payman Zarkesh-Ha	Prediction of gate delay variation for CNFET under CNT density variation.	DFT	2012	DBLP DOI BibTeX RDF
1	Alireza Rohani, Hans G. Kerkhoff	An on-line soft error mitigation technique for control logic of VLIW processors.	DFT	2012	DBLP DOI BibTeX RDF
1	Mohammad Maghsoudloo, Hamid R. Zarandi	Dirty data vulnerability mitigation by means of sharing management in cache coherence protocols.	DFT	2012	DBLP DOI BibTeX RDF
1	Juan Carlos Martínez Santos, Yunsi Fei	Designing and implementing a Malicious 8051 processor.	DFT	2012	DBLP DOI BibTeX RDF
1	Glenn H. Chapman, Rohit Thomas, Israel Koren, Zahava Koren	Relating digital imager defect rates to pixel size, sensor area and ISO.	DFT	2012	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Built-in generation of multi-cycle broadside tests.	DFT	2012	DBLP DOI BibTeX RDF
1	Jianping Gong, Yong-Bin Kim, Fabrizio Lombardi, Jie Han 0001	Hardening a memory cell for low power operation by gate leakage reduction.	DFT	2012	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Maintaining proximity to functional operation conditions under enhanced-scan tests based on functional broadside tests.	DFT	2012	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Generation and compaction of mixed broadside and skewed-load n-detection test sets for transition faults.	DFT	2012	DBLP DOI BibTeX RDF
1	Vadim Geurkov	Optimal choice of arithmetic compactors for mixed-signal systems.	DFT	2012	DBLP DOI BibTeX RDF
1	Yifat Manzor, Osnat Keren	Amalgamated q-ary codes for multi-level flash memories.	DFT	2012	DBLP DOI BibTeX RDF
1	Xuehui Zhang, Kan Xiao, Mohammad Tehranipoor	Path-delay fingerprinting for identification of recovered ICs.	DFT	2012	DBLP DOI BibTeX RDF
1	Kyu-Nam Shim, Jiang Hu	A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience.	DFT	2012	DBLP DOI BibTeX RDF
1	Adam Watkins, Spyros Tragoudas	Transient pulse propagation using the Weibull distribution function.	DFT	2012	DBLP DOI BibTeX RDF
1	Rance Rodrigues, Israel Koren, Sandip Kundu	A mechanism to verify cache coherence transactions in multicore systems.	DFT	2012	DBLP DOI BibTeX RDF
1	Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba	Implementing defect tolerance in 3D-ICs by exploiting degrees of freedom in assembly.	DFT	2012	DBLP DOI BibTeX RDF
1	Kazuteru Namba, Takashi Katagiri, Hideo Ito	Dual-edge-triggered FF with timing error detection capability.	DFT	2012	DBLP DOI BibTeX RDF
1	Gabriel L. Nazar, Luigi Carro	Fast single-FPGA fault injection platform.	DFT	2012	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña 0001, Daniele Rossi 0001, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, Marta Bagatin, Alessandro Paccagnella	High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.	DFT	2012	DBLP DOI BibTeX RDF
1	Fabrizio Lombardi, Nohpill Park, Haider A. F. Almurib, T. Nandha Kumar	On the multiple fault detection of a nano crossbar.	DFT	2012	DBLP DOI BibTeX RDF
1	Chuanlei Zheng, Parijat Shukla, Shuai Wang 0006, Jie S. Hu	Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors.	DFT	2012	DBLP DOI BibTeX RDF
1	Marcelo de Souza Moraes, Marcos Barcellos Hervé, Marcelo Lubaszewski	Low pin count DfT technique for RFID ICs.	DFT	2012	DBLP DOI BibTeX RDF
1	Xinmu Wang, Tatini Mal-Sarkar, Aswin Raghav Krishna, Seetharam Narasimhan, Swarup Bhunia	Software exploitable hardware Trojans in embedded processor.	DFT	2012	DBLP DOI BibTeX RDF
1	Da Cheng, Sandeep K. Gupta 0001	A systematic methodology to improve yield per area of highly-parallel CMPs.	DFT	2012	DBLP DOI BibTeX RDF
1		2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012	DFT	2012	DBLP BibTeX RDF
1	Seyab Khan, Said Hamdioui, Halil Kukner, Praveen Raghavan, Francky Catthoor	Incorporating parameter variations in BTI impact on nano-scale logical gates analysis.	DFT	2012	DBLP DOI BibTeX RDF
1	Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh	Minimization of Trojan footprint by reducing Delay/Area impact.	DFT	2012	DBLP DOI BibTeX RDF
1	Wenpo Zhang, Kazuteru Namba, Hideo Ito	Improving small-delay fault coverage for on-chip delay measurement.	DFT	2012	DBLP DOI BibTeX RDF
1	Mafalda Cortez, Apurva Dargar, Said Hamdioui, Geert Jan Schrijen	Modeling SRAM start-up behavior for Physical Unclonable Functions.	DFT	2012	DBLP DOI BibTeX RDF
1	Martin Omaña 0001, Daniele Rossi 0001, G. Collepalumbo, Cecilia Metra, Fabrizio Lombardi	Faults affecting the control blocks of PV arrays and techniques for their concurrent detection.	DFT	2012	DBLP DOI BibTeX RDF
1	Ke Huang 0001, John M. Carulli Jr., Yiorgos Makris	Parametric counterfeit IC detection via Support Vector Machines.	DFT	2012	DBLP DOI BibTeX RDF
1	Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede	A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures.	DFT	2012	DBLP DOI BibTeX RDF
1	Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone	Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs.	DFT	2012	DBLP DOI BibTeX RDF
1	Asad Amin Bawa, Muhammad Tauseef Rab, Nur A. Touba	Using partial masking in X-chains to increase output compaction for an X-canceling MISR.	DFT	2012	DBLP DOI BibTeX RDF
1	Davide Sabena, Matteo Sonza Reorda, Luca Sterpone	On the development of Software-Based Self-Test methods for VLIW processors.	DFT	2012	DBLP DOI BibTeX RDF
1	Luca Amati, Cristiana Bolchini, Fabio Salice	Optimal Test Set Selection for Fault Diagnosis Improvement.	DFT	2011	DBLP DOI BibTeX RDF
1	Uljana Reinsalu, Jaan Raik, Raimund Ubar, Peeter Ellervee	Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations.	DFT	2011	DBLP DOI BibTeX RDF
1		2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011	DFT	2011	DBLP BibTeX RDF
1	Mohammad Hossein Neishaburi, Zeljko Zilic	Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis.	DFT	2011	DBLP DOI BibTeX RDF
1	Daniele Rossi 0001, Martin Omaña 0001, Cecilia Metra, Alessandro Paccagnella	Impact of Aging Phenomena on Soft Error Susceptibility.	DFT	2011	DBLP DOI BibTeX RDF
1	Khalid Latif 0002, Amir-Mohammad Rahmani, Ethiopia Nigussie, Hannu Tenhunen, Tiberiu Seceleanu	A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip.	DFT	2011	DBLP DOI BibTeX RDF
1	Mario Schölzel	Fine-Grained Software-Based Self-Repair of VLIW Processors.	DFT	2011	DBLP DOI BibTeX RDF
1	Hao Chen, Jie Han 0001, Fabrizio Lombardi	A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits.	DFT	2011	DBLP DOI BibTeX RDF
1	Rance Rodrigues, Israel Koren, Sandip Kundu	An Architecture to Enable Life Cycle Testing in CMPs.	DFT	2011	DBLP DOI BibTeX RDF
1	Costas Argyrides, Ronaldo Rodrigues Ferreira, Carlos Arthur Lang Lisbôa, Luigi Carro	Decimal Hamming: A Software-Implemented Technique to Cope with Soft Errors.	DFT	2011	DBLP DOI BibTeX RDF
1	Mohammad Hossein Neishaburi, Zeljko Zilic	A Fault Tolerant Hierarchical Network on Chip Router Architecture.	DFT	2011	DBLP DOI BibTeX RDF
1	Behnam Ghavami, Mohsen Raji, Hossein Pedram, Omid Naghshineh Arjmand	CNT-count Failure Characteristics of Carbon Nanotube FETs under Process Variations.	DFT	2011	DBLP DOI BibTeX RDF
1	Muhammad Aamir Khan 0002, Hans G. Kerkhoff	SoC Mixed-Signal Dependability Enhancement: A Strategy from Design to End-of-Life.	DFT	2011	DBLP DOI BibTeX RDF
1	Gabriel L. Nazar, Luigi Carro	An Area Effective Parity-Based Fault Detection Technique for FPGAs.	DFT	2011	DBLP DOI BibTeX RDF
1	Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Huaxing Tang, Sudhakar M. Reddy	Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree.	DFT	2011	DBLP DOI BibTeX RDF
1	Joon-Sung Yang, Rudrajit Datta	Efficient Function Mapping in Nanoscale Crossbar Architecture.	DFT	2011	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel	Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector.	DFT	2011	DBLP DOI BibTeX RDF
1	Tobias Koal, Daniel Scheit, Mario Schölzel, Heinrich Theodor Vierhaus	On the Feasibility of Built-In Self Repair for Logic Circuits.	DFT	2011	DBLP DOI BibTeX RDF
1	Nachiket Rajderkar, Marco Ottavi, Salvatore Pontarelli, Jie Han 0001, Fabrizio Lombardi	On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS.	DFT	2011	DBLP DOI BibTeX RDF
1	Masoud Zamani, Mehdi Baradaran Tahoori	Online Missing/Repeated Gate Faults Detection in Reversible Circuits.	DFT	2011	DBLP DOI BibTeX RDF
1	Mohammad Hossein Neishaburi, Zeljko Zilic	Debug Aware AXI-based Network Interface.	DFT	2011	DBLP DOI BibTeX RDF
1	Jongho Seol, Noh-Jin Park, K. M. George, Nohpill Park	Modeling Yield of Self-Healing Carbon Nanotubes/Silicon-Nanowire FET-based Nanoarray.	DFT	2011	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Chiara Sandionigi	A Reliability-Aware Partitioner for Multi-FPGA Platforms.	DFT	2011	DBLP DOI BibTeX RDF
1	Zahra Lak, Nicola Nicolici	A New Algorithm for Post-Silicon Clock Measurement and Tuning.	DFT	2011	DBLP DOI BibTeX RDF
1	Sven Eisenhardt, Anja Küster, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel	Spatial and Temporal Data Path Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures.	DFT	2011	DBLP DOI BibTeX RDF
1	Jinghang Liang, Jie Han 0001, Fabrizio Lombardi	On the Reliable Performance of Sequential Adders for Soft Computing.	DFT	2011	DBLP DOI BibTeX RDF

Publications at "DFT"( http://dblp.L3S.de/Venues/DFT )