Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
11 | Michael Wolfe |
How compilers and tools differ for embedded systems. |
CASES |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Viktor K. Prasanna |
High Performance Computing using Reconfigurable Hardware. |
ENC |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Rodolfo Pellizzoni, Giuseppe Lipari |
Improved Schedulability Analysis of Real-Time Transactions with Earliest Deadline Scheduling. |
IEEE Real-Time and Embedded Technology and Applications Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen |
Hierarchical instruction encoding for VLIW digital signal processors. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Nobuhiko Sugino, Tomoyuki Matsuura, Akinori Nishihara |
New graph transformation schemes in graph-based memory allocation method for an indirect addressing DSP. |
ISCAS (5) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Sung Dae Kim, Jung Hoo Lee, J. M. Yang, Myung Hoon Sunwoo, Seung Keun Oh |
Novel instructions and their hardware architecture for video signal processing. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Francine Bacchini, Jan M. Rabaey, Allan Cox, Frank Lane, Rudy Lauwereins, Ulrich Ramacher, David Witt |
Wireless platforms: GOPS for cents and MilliWatts. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
implementation platforms, data communications, wireless architectures |
11 | Michael Bramberger, Bernhard Rinner, Helmut Schwabach |
A Mobile Agent-Based System for Dynamic Task Allocation in Clusters of Embedded Smart Cameras. |
WISES |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu 0011 |
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
Data communications devices, application studies resulting in better multiple-processor systems, reconfigurable hardware, wireless systems, special-purpose and application-based systems, adaptable architectures, heterogeneous (hybrid) systems, design studies, signal processing systems |
11 | Antonio Gentile, D. Scott Wills |
Portable Video Supercomputing. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Hendrik Seidel, Emil Matús, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard P. Fettweis |
Generated DSP Cores for Implementation of an OFDM Communication System. |
SAMOS |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Kerem Küçük, Mustafa Karakoç, Adnan Kavak |
Software Radio Implementation of a Smart Antenna System on Digital Signal Processors for cdma2000. |
CIT |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Markus Lorenz, Peter Marwedel, Thorsten Dräger, Gerhard P. Fettweis, Rainer Leupers |
Compiler based exploration of DSP energy savings by SIMD operations. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere |
An Integer Linear Programming Approach to Classify the Communication in Process Networks. |
SCOPES |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Sumit Mohanty, Viktor K. Prasanna |
A Framework for Energy Efficient Design of Multi-rate Applications Using Hybrid Reconfigurable Systems. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Zachary K. Baker |
Efficient FPGA-Based Security Kernels. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Nick Tredennick, Brion Shimamoto |
Reconfigurable Systems Emerge. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Tomoya Kitani, Yoshifumi Takamoto, Keiichi Yasumoto, Akio Nakata, Teruo Higashino |
A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems. |
RTSS |
2004 |
DBLP DOI BibTeX RDF |
parametric model checking, real-time systems, high-level synthesis, HW/SW co-design |
11 | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere |
Translating affine nested-loop programs to process networks. |
CASES |
2004 |
DBLP DOI BibTeX RDF |
integer linear programming, process networks, heterogeneous embedded systems |
11 | Moisès Serra, Pere Martí-Puig, Jordi Carrabina |
Implementation of a Channel Equalizer for OFDM Wireless LANs. |
IEEE International Workshop on Rapid System Prototyping |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Sujay Phadke, Rhishikesh Limaye, Siddharth Verma, Kavitha Subramanian |
On Design and Implementation of an Embedded Automatic Speech Recognition System. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Laszlo Hars |
Long Modular Multiplication for Cryptographic Applications. |
CHES |
2004 |
DBLP DOI BibTeX RDF |
Quisquater multiplication, multiply-accumulate architecture, optimization, cryptography, Computer arithmetic, Montgomery multiplication, reciprocal, modular multiplication, Modular reduction |
11 | Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin 0001 |
Power Consumption Modeling and Characterization of the TI C6201. |
IEEE Micro |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Seonil Choi, Ju-wook Jang, Sumit Mohanty, Viktor K. Prasanna |
Domain-Specific Modeling for Rapid Energy Estimation of Reconfigurable Architectures. |
J. Supercomput. |
2003 |
DBLP DOI BibTeX RDF |
FPGA, energy optimization, domain-specific modeling, energy estimation |
11 | Giorgio Zoia, Claudio Alberti |
A virtual DSP architecture for audio applications from a complexity analysis of MPEG-4 structured audio. |
IEEE Trans. Multim. |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto |
Online Self-Repair of FIR Filters. |
IEEE Des. Test Comput. |
2003 |
DBLP DOI BibTeX RDF |
|
11 | F. Hunsinger, Sebastien Francois, Ahmed Amine Jerraya |
Definition of a systematic method for the generation of software test programs allowing the functional verification of System On Chip (SoC). |
MTV |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Seonil Choi, Ronald Scrofano, Viktor K. Prasanna, Ju-wook Jang |
Energy-efficient signal processing using FPGAs. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
energy efficient design techniques, matrix multiplicaiton, FPGA, FFT, performance estimation |
11 | Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers |
Improving Offset Assignment through Simultaneous Variable Coalescing. |
SCOPES |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Gang-Ryung Uh |
Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer. |
SCOPES |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu 0011 |
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
|
11 | David J. Johnston, Martin Fleury, Andy C. Downton |
Multi-Paradigm Framework for Parallel Image Processing. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Sumit Mohanty, Viktor K. Prasanna |
A hierarchical approach for energy efficient application design using heterogeneous embedded systems. |
CASES |
2003 |
DBLP DOI BibTeX RDF |
energy efficiency, design space exploration, performance estimation, heterogeneous embedded systems |
11 | Alessandro Fin, Franco Fummi, Graziano Pravadelli |
Mixing ATPG and property checking for testing HW/SW interfaces. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
model cecking, ATPG, fault simulation |
11 | Magesh Sadasivam, Sangjin Hong |
Application Specific Coarse-Grained FPGA for Processing Element in Real-Time Parallel Particle Filters. |
IWSOC |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Steven J. Vaughan-Nichols |
OFDM: Back to the Wireless Future. |
Computer |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Pierre G. Paulin, Miguel Santana |
FlexWare: A Retargetable Embedded-Software Development Environment. |
IEEE Des. Test Comput. |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Xiushan Feng, Alan J. Hu |
Automatic formal verification for scheduled VLIW code. |
LCTES-SCOPES |
2002 |
DBLP DOI BibTeX RDF |
theory of equality with uninterpreted functions, formal verification, DSP, symbolic execution, VLIW |
11 | Christoph W. Keßler, Andrzej Bednarski |
Optimal integrated code generation for clustered VLIW architectures. |
LCTES-SCOPES |
2002 |
DBLP DOI BibTeX RDF |
integrated code generation, space profile, dynamic programming, register allocation, instruction scheduling, instruction selection |
11 | Xiaotong Zhuang, Santosh Pande, John S. Greenland Jr. |
A Framework for Parallelizing Load/Stores on Embedded Processors. |
IEEE PACT |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Song Hun Kim, William H. Tranter, Scott F. Midkiff |
Middleware for a Distributed Reconfigurable Simulator. |
Annual Simulation Symposium |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Sungchul Yoon, Sangwook Kim, Jae Seuk Oh, Sungho Kang |
A New DSP Architecture for Correcting Errors Using Viterbi Algorithm. |
AISA |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Kevin Skadron |
A microprocessor survey course for learning advanced computer architecture. |
SIGCSE |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss |
A novel codesign approach based on distributed virtual machines. |
CODES |
2002 |
DBLP DOI BibTeX RDF |
Linux |
11 | Cyprian Grassmann, Joachim K. Anlauf |
RACER - A Rapid Prototyping Accelerator for Pulsed Neural Networks. |
FCCM |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu |
Validation in a Component-Based Design Flow for Multicore SoCs. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
validation, SoC, abstraction levels, component-based design, cosimulation |
11 | Valérie Bertin, Jean-Marc Daveau, Philippe Guillaume, Thierry Lepley, Denis Pilat, Claire Richard, Miguel Santana, Thomas Thery |
FlexCC2: An Optimizing Retargetable C Compiler for DSP Processors. |
EMSOFT |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Jinhwan Kim, Sungjoon Jung, Yunheung Paek, Gang-Ryung Uh |
Experience with a retargetable compiler for a commercial network processor. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
non-orthogonal architecture, compiler, network processor |
11 | Luis E. Anido-Rifón, Juan Manuel Santos, Manuel Caeiro, Judith S. Rodríguez |
An Online Environment Supporting High Quality Education in Computational Science. |
International Conference on Computational Science (3) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Michael Hosemann, Gerhard P. Fettweis, Vladimir Nikolajevic, Rene Nüssgen |
Applications for the Highly Parallel Mobile Multimedia Modem M3-DSP. |
EUROMICRO |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Yung-Chia Lin, Yuan-Shin Hwang, Jenq Kuen Lee |
Compiler Optimizations with DSP-Specific Semantic Descriptions. |
LCPC |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Holger Blume, H. Hübert, H. T. Feldkämper, Tobias G. Noll |
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. |
ASAP |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Dieter Bauer, Axel Plinge, Martin Finke |
Selective Phoneme Spotting for Realization of an /s, z, C, t/ Transposer. |
ICCHP |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
TAO: regular expression-based register-transfer level testability analysis and optimization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Elana D. Granston, Eric Stotzer, Joe Zbiciak |
Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture. |
LCTES/OM |
2001 |
DBLP DOI BibTeX RDF |
WHILE loops, software pipelining, digital signal processors, VLIW architectures |
11 | Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss |
A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines. |
DSD |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Takashi Saito, Tsutomu Maruyama, Tsutomu Hoshino, Saburo Hirano |
A Music Synthesizer on FPGA. |
FPL |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Sungtaek Lim, Jihong Kim 0001, Kiyoung Choi |
Scheduling-based code size reduction in processors with indirect addressing mode. |
CODES |
2001 |
DBLP DOI BibTeX RDF |
indirect addressing mode, code generation, code size reduction, storage assignment |
11 | Ruby B. Lee, A. Murat Fiskiran, Abdulla Bubsha |
Multimedia Instructions In IA-64. |
ICME |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie |
An efficient BIST method for testing of embedded SRAMs. |
ISCAS (5) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Raj K. Jain, R. Frenzel, M. Terschluse, Pramod K. Pandey, Seo H. Low, Biju Sukumaran, Lup M. Lam |
System-on-chip design of a four-port ADSL-lite Data DSP. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Erno Salminen, Timo D. Hämäläinen, Tero Kangas, Kimmo Kuusilinna, Jukka Saarinen |
Interfacing multiple processors in a system-on-chip video encoder. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Olli Lehtoranta, Timo Hämäläinen 0001, Jukka Saarinen |
Parallel implementation of H.263 encoder for CIF-sized images on quad DSP system. |
ISCAS (2) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Chung-Hsien Tso, Jiin-Chuan Wu |
An integrated digital PWM DC/DC converter using proportional current feedback. |
ISCAS (3) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Rainer Leupers, Steven Bashford |
Graph-based code selection techniques for embedded processors. |
ACM Trans. Design Autom. Electr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
code selection, irregular data paths, embedded processors, data-flow graphs, SIMD instructions |
11 | Herman Schmit, Srihari Cadambi, Matthew Moe, Seth Copen Goldstein |
Pipeline Reconfigurable FPGAs. |
J. VLSI Signal Process. |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Shiro Kobayashi, Gerhard P. Fettweis |
A Hierarchical Block-Floating-Point Arithmetic. |
J. VLSI Signal Process. |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Stefan Pees, Andreas Hoffmann 0002, Heinrich Meyr |
Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian |
Effective Low Power BIST for Datapaths. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
11 | James Brusey, Mark Makies, Lin Padgham, Brad Woodvine, Karl Fantone |
RMIT United. |
RoboCup |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Mathias Kortke, Thomas Schmitt 0002, Renate Merker |
Application of Partitioning Methods for the Design of Parallel Programs for a System of Digital Signal Processors. |
PARELEC |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Ingrid Verbauwhede, Chris Nicol |
Low power DSP's for wireless communications (embedded tutorial session). |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
programmable processors, architectures, wireless communications, digital signal processing |
11 | Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo |
Designing High-Speed Asynchronous Pipelines. |
EUROMICRO |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Simon Leung, Adam Postula, Ahmed Hemani |
Development of Programmable Architecture for Base-Band Processing. |
EUROMICRO |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Dave Comisky, Sanjive Agarwala, Charles Fuoco |
A Scalable High-Performance DMA Architecture for DSP Applications. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Tor E. Jeremiassen |
Sleipnir - An Instruction-Level Simulator Generator. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian |
Low Power/Energy BIST Scheme for Datapaths. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Ted Bapty, Jason Scott, Sandeep Neema, Janos Sztipanovits |
Uniform Execution Environment for Dynamic Reconfiguration. |
ECBS |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Daniel P. Van der Velde, Ad J. van de Goor |
Designing a Memory Module Tester. |
MTDT |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Praveen K. Murthy, Shuvra S. Bhattacharyya |
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications. |
ISSS |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Paulo Centoducatte, Ricardo Pannain, Guido Araujo |
Compressed Code Execution on DSP Architectures. |
ISSS |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Byung Kook Kim |
Reliability Analysis of Real-Time Controllers with Dual-Modular Temporal Redundancy. |
RTCSA |
1999 |
DBLP DOI BibTeX RDF |
reliability improvement, dual-modular redundancy, temporal redundancy and reliability analysis, Fault tolerance |
11 | Nikil D. Dutt, Brian Kelley |
On the rapid prototyping and design of a wireless communication system on a chip (abstract). |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Mathias Kortke, Dirk Fimmel, Renate Merker |
Parallelization of Algorithms for a System of Digital Signal Processors. |
EUROMICRO |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Tor E. Jeremiassen |
A DSP with Caches-A Study of the GSM-EFR Codec on the TI C6211. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
GSM-EFR Speech Codec, Performance, Cache, DSP |
11 | Nobuhiko Sugino, Harushige Funaki, Akinori Nishihara |
Memory address allocation method for a indirect addressing DSP with consideration of modification in local computational order. |
ISCAS (3) |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Stefan Fröhlich, Martin Gotschlich, Udo Krebelder, Bernhard Wess |
Dynamic trellis diagrams for optimized DSP code generation. |
ISCAS (3) |
1999 |
DBLP DOI BibTeX RDF |
|
11 | S. Masupe, Tughrul Arslan |
Low power DCT implementation approach for VLSI DSP processors. |
ISCAS (1) |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. |
VTS |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas |
Managing Pipeline-Reconfigurable FPGAs. |
FPGA |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Paul S. Graham, Brent E. Nelson |
FPGA-Based Sonar Processing. |
FPGA |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Holger Keding, Markus Willems, Martin Coors, Heinrich Meyr |
FRIDGE: A Fixed-Point Design and Simulation Environment. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
FRIDGE, interpolative approach, fixed-C, assignment-time instantiation, simulation, design, interpolation, quantization, fixed-point |
11 | Neil W. Bergmann, Peter R. Sutton |
A High-Performance Computing Module for a Low Earth Orbit Satellite Using Reconfigurable Logic. |
FPL |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Luciano Lavagno |
System-Level Design Models and Implementation Techniques. |
ACSD |
1998 |
DBLP DOI BibTeX RDF |
finite state machines, formal models, system-level design, co-simulation, co-synthesis |
11 | Nikhil D. Gupta, John K. Antonio, Jack M. West |
Reconfigurable Computing for Space-Time Adaptive Processing. |
FCCM |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Dionysis Papadimatos, Theodore Antonakopoulos 0001, Vassilios Makios |
Real-Time Disparity Information Compression in 3D Teleconferencing Systems. |
EUROMICRO |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Chouki Aktouf, Ghassan Al Hayek, Chantal Robach |
On-line testing of scalable signal processing architectures using a software test method. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001 |
Extensions to Programmable DSP architectures for Reduced Power Dissipation. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
Low Power Design, DSP Architecture |
11 | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001 |
Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
Hardware/Software High Level Synthesis, Low Power Design, FIR Filters |