Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Haigeng Wang, Nikil D. Dutt, Alex Nicolau |
Regular schedules for scalable design of IIR filters. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Antonio Hernández, Luis Gómez, Antonio Núñez |
GASTIM: A timing analyzer for GaAs digital circuits. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Polen Kission, Etienne Closse, Laurent Bergher, Ahmed Amine Jerraya |
Industrial experimentation of high-level synthesis. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | U. Bruning, G. Radke, J. Sladky |
State-machine-development-tool for high-level-design entry and simulation. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Gustavo R. Alves, Manuel G. Gericota, José L. Ramalho, José Manuel Martins Ferreira |
An HDL approach to board-level BIST. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Wen-Lin Yang, Robert Michael Owens, Mary Jane Irwin |
Multi-way FSM decomposition based on interconnect complexity. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Péter Keresztes, Istvan Agotai |
The concept of superprocesses for high-level synthesis and their VHDL modelling. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Venkataramana Kommu, Irith Pomeranz |
GAFPGA: Genetic algorithm for FPGA technology mapping. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Ronald D. Hindmarsh |
JOGM: A CMOS cell layout style using jogged transistor gates. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Usha Prabhu, Barry M. Pangrle |
Conditional and unconditional hardware sharing in pipeline synthesis. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Chaeryung Park, Taewhan Kim, C. L. Liu 0001 |
Register allocation for data flow graphs with conditional branches and loops. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Ulrich Weinmann, Wolfgang Rosenstiel |
Technology mapping for sequential circuits based on retiming techniques. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Iksoo Pyo, Alvin M. Despain |
PDAS: Processor design automation system. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Bernhard Klaassen, Karl L. Paap |
SPAN: Tightly coupled thermal and electrical simulation. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | |
Proceedings of the European Design Automation Conference 1993, EURO-DAC '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993 |
EURO-DAC |
1993 |
DBLP BibTeX RDF |
|
1 | Jack T. Yao, Andrew T. Yang |
A consistent nonlinear simulation environment based on improved harmonic balance techniques. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Peter M. Kist, Rene van Leuken 0001, Mattie N. Sim |
Aspects of realizing the CFI design representation specification in the NELSIS framework. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Maria Brielmann, Bernd Kleinjohann |
A formal model for coupling computer based system and physical systems. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Paolo Camurati, Fulvio Corno, Paolo Prinetto |
An efficient tool for system-level verification of behaviors and temporal properties. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Ilan Levin, Ron Y. Pinter |
Realizing expression graphs using table-lookup FPGAs. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | T. W. Her, D. F. Wong 0001 |
Cell area minimization by transistor folding. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida |
A new global routing algorithm for over-the-cell routing in standard cell layouts. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Manzer Masud, Maddu Karunaratne |
Test generation based on synthesizable VHDL descriptions. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Hans Achatz |
Extended 0/1 LP formulation for the scheduling problem in high-level synthesis. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Hans-Georg Martin |
Retiming by combination of relocation and clock delay adjustment. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Tong Gao, Chung Laung (Dave) Liu, Kuang-Chien Chen |
A performance driven hierarchical partitioning placement algorithm. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Antonio J. Acosta 0001, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas |
Modeling of real bistables in VHDL. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Chabane Oussalah, Guilaine Talens, M. F. Colinas |
Concepts and methods for version modeling. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Charles Munk, Pierre Ukelo, Alain Vachoux, Daniel Mlynek |
The MODES Global Control Environment - A tool for rapid prototyping. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Gabriele Pulini, Stefan Hamacher |
Next generation environment for extremely fast test pattern generation. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Alain Debreil, Philippe Oddo |
Synchronous designs in VHDL. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Ting-Chi Wang, D. F. Wong 0001, Yachyang Sun, C. K. Wong |
On over-the-cell channel routing. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Wolfgang Ecker |
Using VHDL for HW/SW co-specification. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Peter Windirsch, Peter Duzy |
The CALLAS synthesis system and its application to mechatronic ASIC design problems. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | João P. Marques Silva, Karem A. Sakallah |
Concurrent path sensitization in timing analysis. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Werner Damm, Bernhard Josko, Rainer Schlör |
A net-based semantics for VHDL. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Jean Paul Calvez, Dominique Heller, P. Bakowski |
Functional-level synthesis with VHDL. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Gerd Rietsche |
State assignment for finite state machines using T flip-flops. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Michael Gössel, Helmut Jürgensen |
Monitoring BIST by covers. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Hirendu Vaishnav, Massoud Pedram |
PCUBE: A performance driven placement algorithm for low power designs. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Youssef Saab |
Post-analysis-based clustering dramatically improves the Fiduccia-Mattheyses algorithm. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Negoslav Simic, Harden Ortner |
Partitioning strategies within a distributed multilevel logic simulator including dynamic repartitioning. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal |
Test function embedding algorithms with application to interconnected finite state machines. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Peter Gutberlet, Wolfgang Rosenstiel |
Interface specification and synthesis for VHDL processes. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Philippe Moeschler, Hans Peter Amann, Fausto Pellandini |
High-level modeling using extended timing diagrams - A formalism for the behavioral specification of digital hardware. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Too-Seng Tia, Chung Laung Liu |
A new performance driven macro-cell placement algorithm. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Serafín Olcoz, José Manuel Colom |
Toward a formal semantics of IEEE Std. VHDL 1076. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Franz J. Rammig |
Modelling aspects of system level design. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | I. Shagurin, A. Ivanov |
Computer-aided technique for optimal design of defect-tolerant VLSI with built-in redundancy. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Cheng-Liang Ding, Ching-Yen Ho, Mary Jane Irwin |
A new optimization driven clustering algorithm for large circuits. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Eric Martin 0001, Olivier Sentieys, Hélène Dubois, Jean Luc Philippe |
GAUT: An architectural synthesis tool for dedicated signal processors. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Kenneth D. Boese, Andrew B. Kahng, Chung-Wen Albert Tsao |
Best-so-far vs. where-you-are: New perspectives on simulated annealing for CAD. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Malgorzata Chrzanowska-Jeske, Steffen Goller |
Partitioning approach to find an exact solution to the fitting problem in an application-specific EPLD device. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Vladimir A. Koval, Anatolij I. Ostapchuk, Igor V. Farmaga, Dmytro V. Fedasyuk |
CAD: The numerical and analytical methods combined for the analysis of IC's thermal fields. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Mohamed Belhadj, Roderick McConnell, Paul Le Guernic |
A framework for macro- and micro-time to model VHDL attributes. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Gilles Fourneris, Nourouddine Bekkara, Jacques Benkoski, Lucia Zullino, Dino Spatafora, Giuseppe Martino |
Demosthenes-A technology-independent power DMOS layout generator. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Bernd Becker 0001, Rolf Drechsler, Paul Molitor |
On the implementation of an efficient performance driven generator for conditional-sum-adders. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Bertram Després, Robert Piloty, Ulf Schellin |
An approach to CAD database support of design consistency control. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Veronique Pla, Jean François Santucci, Norbert Giambiasi |
On the modeling and testing of VHDL behavioral descriptions of sequential circuits. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | James R. Armstrong |
Hierarchical test generation: Where we are, and where we should be going. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Loganath Ramachandran, Sanjiv Narayan, Frank Vahid, Daniel D. Gajski |
Synthesis of functions and procedures in behavioral VHDL. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Xiao Sun 0002, Fabrizio Lombardi, Donatella Sciuto |
On the minimal test set for single fault location. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | M. Rullán, F. C. Blom, Joan Oliver, Carles Ferrer 0001 |
Layout-level design for testability rules for a CMOS cell library. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Ricardo P. Jacobi, Anne-Marie Trullemans |
A new logic minimization method for multiplexor-based FPGA synthesis. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Sanjiv Narayan, Daniel D. Gajski |
Features supporting system-level specification in HDLs. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Maria José Aguado, Miguel Miranda, Eduardo de la Torre, Carlos A. López-Barrio |
A dynamic communication strategy for the distributed ATPG system DPLATON. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Loganath Ramachandran, Daniel D. Gajski |
Architectural tradeoffs in synthesis of pipelined controls. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Marcus Bluml, Michael Lenzen, Adam Pawlak |
A workbench for generation of component models. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Hsiao-Ping Juan, Nancy D. Holmes, Smita Bakshi, Daniel D. Gajski |
Top-down modeling of RISC processors in VHDL. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Mitchell A. Thornton, V. S. S. Nair |
An iterative combinational logic synthesis technique using spectral information. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Román Hermida, Milagros Fernández, Francisco Tirado, Victor Manuel Sanchez, Pablo Ruperez |
An approach to module binding by fuzzy partitioning. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Peter Poechmueller, Manfred Glesner, Fang Longsen |
High-level synthesis transformations for programmable architectures. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | M.-N. Sabry, M. S. Tawfik, Hazem ElTahawy, Serge Garcia Sabiro, Joel Besnard |
A novel and efficient technique for transient analysis of tightly coupled circuits: The integral equation method (IEM). |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Eric Felt, Gary York, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
Dynamic variable reordering for BDD minimization. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Kai Zhu 0001, D. F. Wong 0001 |
Fast Boolean matching for field-programmable gate arrays. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Jens Müller 0008, Heinrich Krämer |
Analysis of multi-process VHDL specifications with a Petri net model. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Markus Robinson |
Technology independent boundary scan synthesis (design flow issues). |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | D. K. Arvind 0001 |
Locally optimistic methods of concurrent simulation. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Kuang-Chien Chen |
Boolean matching based on Boolean unification. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
1 | Eero Pajarre, Tapani Ritoniemi, T. Tenhunen |
PAR-APLAC: Parallel Circuit Analysis and Optimization. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Werner Rissiek, Werner John |
A dynamic scheduling algorithm for the simulation of MOS and bipolar circuits using waveform relaxation. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Günter Dedié |
Challenges for CAD in computer development in the 1990s. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Klaus Glasmacher, Gerhard Zimmermann |
Chip assembly in the PLAYOUT VLSI design system. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Moe Shahdad |
1992 VHDL standardization overview. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Vincent Olive, R. Airiau, J. M. Bergé, Anne Robert |
Using VHDL for datapath synthesis. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Timothy Kam, P. A. Subrahmanyam |
State machine abstraction from circuit layouts using BDD's: applications in verification and synthesis. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Michael Rumsey, Colin Farquhar |
Unifying tool, data and process flow management. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | C. A. Schot, Mattie N. Sim, Peter M. Kist |
ANT - a test harness for the NELSIS CAD system. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Alain Fonkoua, Jacques Rouillard |
VHDL intermediate format standardization activity: status and trends. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Jens Sparsø, Jørgen Staunstrup, Michael Dantzer-Sørensen |
Design of delay insensitive circuits using multi-ring structures. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Wolfgang Ecker, Michael Hofmeister |
The design cube: a new model for VHDL designflow representation. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Serge Maginot |
Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I & M. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | J. L. Giordana |
Interest of a VHDL native environment. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Viraphol Chaiyakul, Allen C.-H. Wu, Daniel D. Gajski |
Timing models for high-level synthesis. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Peter Gutberlet, Jens Müller 0008, Heinrich Krämer, Wolfgang Rosenstiel |
Automatic module allocation in high level synthesis. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Roy Davies |
Electronic System Design: tools and methodology to meet the productivity challenge. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Takashi Shimamoto, Hidetaka Hane, Isao Shirakawa, Shuji Tsukiyama, Shoji Shinoda, Nobuyasu Yui, Nobuyuki Nishiguchi |
A distributed routing system for multilayer SOG. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Mark Beardslee, Bill Lin 0001, Alberto L. Sangiovanni-Vincentelli |
Communication based logic partitioning. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Derek Feltham, Jitendra Khare, Wojciech Maly |
Design for testability view on placement and routing. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
1 | Yogesh Mishra, Sunil D. Sherlekar, G. Venkatesh 0001 |
Path breaker: a tool for the optimal design of speed independent asynchronous controllers. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|