Search results for "FCCM"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Qijing Huang 0001, Ameer Haj-Ali, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek	AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning.	FCCM	2019	DBLP DOI BibTeX RDF
1	Mohsen Imani, Sahand Salamat, Behnam Khaleghi, Mohammad Samragh, Farinaz Koushanfar, Tajana Rosing	SparseHD: Algorithm-Hardware Co-optimization for Efficient High-Dimensional Computing.	FCCM	2019	DBLP DOI BibTeX RDF
1	Dan Pritsker, Colman Cheung	Monobit Wideband Receiver with Integrated Dithering in FPGA.	FCCM	2019	DBLP DOI BibTeX RDF
1	Michail Papadimitriou, Juan Fumero, Athanasios Stratikopoulos, Christos Kotselidis	Towards Prototyping and Acceleration of Java Programs onto Intel FPGAs.	FCCM	2019	DBLP DOI BibTeX RDF
1	Nils Voss, Pablo Quintana, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev	Memory Mapping for Multi-die FPGAs.	FCCM	2019	DBLP DOI BibTeX RDF
1	Amir Yazdanbakhsh, Michael Brzozowski, Behnam Khaleghi, Soroush Ghodrati, Kambiz Samadi, Nam Sung Kim, Hadi Esmaeilzadeh	FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial Networks.	FCCM	2018	DBLP DOI BibTeX RDF
1	Nadesh Ramanathan, George A. Constantinides, John Wickerson	Concurrency-Aware Thread Scheduling for High-Level Synthesis.	FCCM	2018	DBLP DOI BibTeX RDF
1	Guohao Dai, Tianhao Huang, Yu Wang 0002, Huazhong Yang, John Wawrzynek	NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing Overheads.	FCCM	2018	DBLP DOI BibTeX RDF
1	Sunwoong Kim, Rob A. Rutenbar	Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA.	FCCM	2018	DBLP DOI BibTeX RDF
1	Festus Hategekimana, Joel Mandebi Mbongue, Md Jubaer Hossain Pantho, Christophe Bobda	Inheriting Software Security Policies within Hardware IP Components.	FCCM	2018	DBLP DOI BibTeX RDF
1	Dimitris Agiakatsikas, Ganghee Lee, Thomas Mitchell, Ediz Cetin, Oliver Diessel	From C to Fault-Tolerant FPGA-Based Systems.	FCCM	2018	DBLP DOI BibTeX RDF
1	Denis Matousek, Jirí Matousek 0002, Jan Korenek	High-Speed Regular Expression Matching with Pipelined Memory-Based Automata.	FCCM	2018	DBLP DOI BibTeX RDF
1	Jiayi Sheng, Chen Yang 0010, Tianqi Wang, Martin C. Herbordt	High Performance Dynamic Communication on Reconfigurable Clusters.	FCCM	2018	DBLP DOI BibTeX RDF
1	Zhong Guan	EM-Aware Memory Mapping Algorithms for SRAM Based FPGA.	FCCM	2018	DBLP DOI BibTeX RDF
1	Abhishek Kumar Jain, G. Scott Lloyd, Maya B. Gokhale	Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments.	FCCM	2018	DBLP DOI BibTeX RDF
1	Eric Matthews, Zavier Aguila, Lesley Shannon	Evaluating the Performance Efficiency of a Soft-Processor, Variable-Length, Parallel-Execution-Unit Architecture for FPGAs Using the RISC-V ISA.	FCCM	2018	DBLP DOI BibTeX RDF
1	Chris Lavin, Alireza Kaviani	RapidWright: Enabling Custom Crafted Implementations for FPGAs.	FCCM	2018	DBLP DOI BibTeX RDF
1	Ryota Yasudo, Ana Lucia Varbanescu, José Gabriel F. Coutinho, Wayne Luk, Hideharu Amano	Performance Prediction for Large-Scale Heterogeneous Platforms.	FCCM	2018	DBLP DOI BibTeX RDF
1	Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise	A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath.	FCCM	2018	DBLP DOI BibTeX RDF
1	Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang 0002, Jingxian Xu, Shaochong Zhang	Understanding Performance Differences of FPGAs and GPUs.	FCCM	2018	DBLP DOI BibTeX RDF
1	Chethan Ramesh, Shivukumar B. Patil, Siva Nishok Dhanuskodi, George Provelengios, Sébastien Pillement, Daniel E. Holcomb, Russell Tessier	FPGA Side Channel Attacks without Physical Access.	FCCM	2018	DBLP DOI BibTeX RDF
1	Erwei Wang, James J. Davis 0001, Peter Y. K. Cheung	A PYNQ-Based Framework for Rapid CNN Prototyping.	FCCM	2018	DBLP DOI BibTeX RDF
1	Ciro Ceissler, Ramon Nepomuceno, Márcio Machado Pereira, Guido Araujo	Automatic Offloading of Cluster Accelerators.	FCCM	2018	DBLP DOI BibTeX RDF
1	Dongyang Li, Fei Wu 0005, Yang Weng, Qing Yang 0001, Changsheng Xie	HODS: Hardware Object Deserialization Inside SSD Storage.	FCCM	2018	DBLP DOI BibTeX RDF
1	Jason Cong, Jie Wang 0022	Automatic Interior I/O Elimination in Systolic Array Architecture.	FCCM	2018	DBLP DOI BibTeX RDF
1	Zhuolun He, Hanxian Huang, Ming Jiang 0001, Yuanchao Bai, Guojie Luo	FPGA-Based Real-Time Super-Resolution System for Ultra High Definition Videos.	FCCM	2018	DBLP DOI BibTeX RDF
1	Minghua Shen, Guojie Luo, Nong Xiao	Exploiting Box Expansion and Grid Partitioning for Parallel FPGA Routing.	FCCM	2018	DBLP DOI BibTeX RDF
1	Asif Islam, Nachiket Kapre	LegUp-NoC: High-Level Synthesis of Loops with Indirect Addressing.	FCCM	2018	DBLP DOI BibTeX RDF
1	Xiaofan Zhang 0001, Junsong Wang, Chao Zhu, Yonghua Lin, Jinjun Xiong, Wen-Mei W. Hwu, Deming Chen	AccDNN: An IP-Based DNN Generator for FPGAs.	FCCM	2018	DBLP DOI BibTeX RDF
1	Matthew Cannon, Andrew M. Keller, Michael J. Wirthlin	Improving the Effectiveness of TMR Designs on FPGAs with SEU-Aware Incremental Placement.	FCCM	2018	DBLP DOI BibTeX RDF
1	Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda, David Andrews 0001, Marjan Asadinia	Enabling Transparent Acceleration of OpenCV Library Kernels on a Hybrid Memory Cube Computer.	FCCM	2018	DBLP DOI BibTeX RDF
1	Steve Dai, Yuan Zhou, Hang Zhang 0010, Ecenur Ustun, Evangeline F. Y. Young, Zhiru Zhang	Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning.	FCCM	2018	DBLP DOI BibTeX RDF
1	Jason Cong, Peng Wei 0004, Cody Hao Yu, Peipei Zhou 0001	Latte: Locality Aware Transformation for High-Level Synthesis.	FCCM	2018	DBLP DOI BibTeX RDF
1	Tobias Kenter, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt 0003, Ayesha Afzal, Frank Hannig, Jens Förstner, Christian Plessl	OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.	FCCM	2018	DBLP DOI BibTeX RDF
1	Weikang Qiao, Jieqiong Du, Zhenman Fang, Michael Lo, Mau-Chung Frank Chang, Jason Cong	High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms.	FCCM	2018	DBLP DOI BibTeX RDF
1	Siddhartha 0001, Nachiket Kapre	Hoplite-Q: Priority-Aware Routing in FPGA Overlay NoCs.	FCCM	2018	DBLP DOI BibTeX RDF
1	Jieming Xu, Miriam Leeser	Cross Component Optimization for Modern LTE Downlink Shared Channel Implementation.	FCCM	2018	DBLP DOI BibTeX RDF
1	Katayoun Neshatpour, Hosein Mohammadi Makrani, Avesta Sasan, Hassan Ghasemzadeh 0001, Setareh Rafatirad, Houman Homayoun	Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce.	FCCM	2018	DBLP DOI BibTeX RDF
1	Sajjad Taheri, Jin Heo, Payman Behnam, Jeffrey Chen, Alexander V. Veidenbaum, Alexandru Nicolau	Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines.	FCCM	2018	DBLP DOI BibTeX RDF
1	Sam Skalicky, Joshua S. Monson, Andrew G. Schmidt, Matthew French	Hot & Spicy: Improving Productivity with Python and HLS for FPGAs.	FCCM	2018	DBLP DOI BibTeX RDF
1	Abhi D. Rajagopala, Ron Sass, Andrew G. Schmidt, Matthew French	Bridging the Gap between Advanced Memory and Heterogeneous Architectures.	FCCM	2018	DBLP DOI BibTeX RDF
1	Liang Feng 0001, Sharad Sinha, Wei Zhang 0012, Yun Liang 0001	CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms.	FCCM	2018	DBLP DOI BibTeX RDF
1	Abdul-Amir Yassine, Yasmin Afsharnejad, Omar Ragheb, Vaughn Betz, Paul Chow	A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media.	FCCM	2018	DBLP DOI BibTeX RDF
1		26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018, Boulder, CO, USA, April 29 - May 1, 2018	FCCM	2018	DBLP BibTeX RDF
1	Tong Geng, Tianqi Wang, Ahmed Sanaullah, Chen Yang 0010, Rui Xu, Rushi Patel, Martin C. Herbordt	FPDeep: Acceleration and Load Balancing of CNN Training on FPGA Clusters.	FCCM	2018	DBLP DOI BibTeX RDF
1	Omar Ragheb, Jason Helge Anderson	High-Level Synthesis of FPGA Circuits with Multiple Clock Domains.	FCCM	2018	DBLP DOI BibTeX RDF
1	Farnoud Farahmand, William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj	Improved Lightweight Implementations of CAESAR Authenticated Ciphers.	FCCM	2018	DBLP DOI BibTeX RDF
1	Jialiang Zhang, Jing Li 0073	PQ-CNN: Accelerating Product Quantized Convolutional Neural Network on FPGA.	FCCM	2018	DBLP DOI BibTeX RDF
1	Nele Mentens, Edoardo Charbon, Francesco Regazzoni 0001	Rethinking Secure FPGAs: Towards a Cryptography-Friendly Configurable Cell Architecture and Its Automated Design Flow.	FCCM	2018	DBLP DOI BibTeX RDF
1	Madison N. Emas, Austin Baylis, Greg Stitt	High-Frequency Absorption-FIFO Pipelining for Stratix 10 HyperFlex.	FCCM	2018	DBLP DOI BibTeX RDF
1	Shivukumar B. Patil, Tianqi Liu, Russell Tessier	A Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-Chip.	FCCM	2018	DBLP DOI BibTeX RDF
1	Björn Gottschall, Thomas PreuBer, Akash Kumar 0001	Reloc - An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration Tiles.	FCCM	2018	DBLP DOI BibTeX RDF
1	Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei 0004, Tianhe Yu	SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing.	FCCM	2018	DBLP DOI BibTeX RDF
1	Zhenyuan Ruan, Tong He, Bojie Li, Peipei Zhou 0001, Jason Cong	ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA.	FCCM	2018	DBLP DOI BibTeX RDF
1	Jeffrey Goeders, Tanner Gaskin, Brad L. Hutchings	Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ.	FCCM	2018	DBLP DOI BibTeX RDF
1	José Luis Imaña	Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials.	FCCM	2018	DBLP DOI BibTeX RDF
1	Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis	Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs.	FCCM	2018	DBLP DOI BibTeX RDF
1	Mohammad Ghasemzadeh 0002, Mohammad Samragh, Farinaz Koushanfar	ReBNet: Residual Binarized Neural Network.	FCCM	2018	DBLP DOI BibTeX RDF
1	Deshya Wijesundera, Alok Prakash, Thilina Perera, Kalindu Herath, Thambipillai Srikanthan	Wibheda: Framework for Data Dependency-Aware Multi-Constrained Hardware-Software Partitioning in FPGA-Based SoCs for IoT Devices.	FCCM	2018	DBLP DOI BibTeX RDF
1	John Mawer, Oscar Palomar, Cosmin Gorgovan, Andy Nisbet, Will Toms, Mikel Luján	The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation.	FCCM	2017	DBLP DOI BibTeX RDF
1	Ali Jafari, Maysam Ghovanloo, Tinoosh Mohsenin	A Real-Time Embedded FPGA Processor for a Stand-Alone Dual-Mode Assistive Device.	FCCM	2017	DBLP DOI BibTeX RDF
1	Haohuan Fu, Conghui He, Wayne Luk, Weijia Li, Guangwen Yang	A Nanosecond-Level Hybrid Table Design for Financial Market Data Generators.	FCCM	2017	DBLP DOI BibTeX RDF
1	Muhsen Owaida, David Sidler, Kaan Kara, Gustavo Alonso	Centaur: A Framework for Hybrid CPU-FPGA Databases.	FCCM	2017	DBLP DOI BibTeX RDF
1	Edward Bartz, Jorge Chaves, Yuri Gershtein, Eva Halkiadakis, Michael D. Hildreth, Savvas Kyriacou, Kevin Lannon, Anthony Lefeld, Anders Ryd, Louise Skinnari, Robert Stone, Charles Strohman, Zhengcheng Tao, Brian Winer, Peter Wittich, Zhiru Zhang, Margaret Zientek	FPGA-Based Real-Time Charged Particle Trajectory Reconstruction at the Large Hadron Collider.	FCCM	2017	DBLP DOI BibTeX RDF
1	Young Kyu Choi, Jason Cong	HLScope: High-Level Performance Debugging for FPGA Designs.	FCCM	2017	DBLP DOI BibTeX RDF
1	Yongming Shen 0001, Michael Ferdman, Peter A. Milder	Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer.	FCCM	2017	DBLP DOI BibTeX RDF
1	Adewale Adetomi, Godwin Enemali, Tughrul Arslan	Relocating Encrypted Partial Bitstreams by Advance Task Address Loading.	FCCM	2017	DBLP DOI BibTeX RDF
1	Liqiang Lu, Yun Liang 0001, Qingcheng Xiao, Shengen Yan	Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs.	FCCM	2017	DBLP DOI BibTeX RDF
1	Fubing Mao, Wei Zhang 0012, Bingsheng He, SiewKei Lam	Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs.	FCCM	2017	DBLP DOI BibTeX RDF
1	Qiang Liu, HanJing Qian	FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters.	FCCM	2017	DBLP DOI BibTeX RDF
1	Baptiste Roux, Matthieu Gautier, Olivier Sentieys, Jean-Philippe Delahaye	Fast and Energy-Driven Design Space Exploration for Heterogeneous Architectures.	FCCM	2017	DBLP DOI BibTeX RDF
1	Shuanglong Liu, Christos-Savvas Bouganis	Communication-Aware MCMC Method for Big Data Applications on FPGAs.	FCCM	2017	DBLP DOI BibTeX RDF
1	Raghid Morcel, Haitham Akkary, Hazem M. Hajj, Mazen A. R. Saghir, Anil S. Keshavamurthy, Rahul Khanna, Hassan Artail	Minimalist Design for Accelerating Convolutional Neural Networks for Low-End FPGA Platforms.	FCCM	2017	DBLP DOI BibTeX RDF
1	David Ojika, Piotr Majcher, Wojciech Neubauer, Suchit Subhaschandra, Darin Acosta	SWiF: A Simplified Workload-Centric Framework for FPGA-Based Computing.	FCCM	2017	DBLP DOI BibTeX RDF
1	Festus Hategekimana, Christophe Bobda	Applying the Flask Security Architecture to Secure SoC Design.	FCCM	2017	DBLP DOI BibTeX RDF
1	Ganghee Lee, Dimitris Agiakatsikas, Tong Wu 0007, Ediz Cetin, Oliver Diessel	TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS.	FCCM	2017	DBLP DOI BibTeX RDF
1	Taylor J. L. Whitaker, Christophe Bobda	CAPSL: A Tool for Automatic Generation of Hardware Sandboxes for IP Security.	FCCM	2017	DBLP DOI BibTeX RDF
1	Qian Wu, Yongxin Zhu 0001, Xu Wang 0010, Mengjun Li, Junjie Hou, Ali Masoumi	Exploring High Efficiency Hardware Accelerator for the Key Algorithm of Square Kilometer Array Telescope Data Processing.	FCCM	2017	DBLP DOI BibTeX RDF
1	Morteza Hosseini, Rashidul Islam, Amey M. Kulkarni, Tinoosh Mohsenin	A Scalable FPGA-Based Accelerator for High-Throughput MCMC Algorithms.	FCCM	2017	DBLP DOI BibTeX RDF
1	Jeffrey Goeders	Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices.	FCCM	2017	DBLP DOI BibTeX RDF
1	Kaan Kara, Dan Alistarh, Gustavo Alonso, Onur Mutlu, Ce Zhang 0001	FPGA-Accelerated Dense Linear Machine Learning: A Precision-Convergence Trade-Off.	FCCM	2017	DBLP DOI BibTeX RDF
1	Nathaniel McVicar, Chih-Ching Lin, Scott Hauck	K-Mer Counting Using Bloom Filters with an FPGA-Attached HMC.	FCCM	2017	DBLP DOI BibTeX RDF
1	Soroosh Khoram, Jialiang Zhang, Maxwell Strange, Jing Li 0073	Accelerating Large-Scale Graph Analytics with FPGA and HMC.	FCCM	2017	DBLP DOI BibTeX RDF
1		25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017, Napa, CA, USA, April 30 - May 2, 2017	FCCM	2017	DBLP BibTeX RDF
1	Ian J. Barge, Cristinel Ababei	A Network-on-Chip Based H.264 Video Decoder Prototype Implemented on FPGAs.	FCCM	2017	DBLP DOI BibTeX RDF
1	Shane T. Fleming, David B. Thomas	Using Runahead Execution to Hide Memory Latency in High Level Synthesis.	FCCM	2017	DBLP DOI BibTeX RDF
1	Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel E. Holcomb, Russell Tessier	Energy Efficient Loop Unrolling for Low-Cost FPGAs.	FCCM	2017	DBLP DOI BibTeX RDF
1	Sam M. H. Ho, C.-H. Dominic Hung, Ho-Cheung Ng, Maolin Wang, Hayden Kwok-Hay So	A Parameterizable Activation Function Generator for FPGA-Based Neural Network Applications.	FCCM	2017	DBLP DOI BibTeX RDF
1	Jianxin Guo, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei	Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA.	FCCM	2017	DBLP DOI BibTeX RDF
1	Susumu Mashimo, Thiem Van Chu, Kenji Kise	High-Performance Hardware Merge Sorter.	FCCM	2017	DBLP DOI BibTeX RDF
1	Ashutosh Dhar, Deming Chen	Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration.	FCCM	2017	DBLP DOI BibTeX RDF
1	Jong Hun Han, Neelakandan Manihatty Bojan, Andrew W. Moore 0002	Exploration of FPGA-Based Packet Switches for Rack-Scale Computers on a Board.	FCCM	2017	DBLP DOI BibTeX RDF
1	Minghua Shen, Guojie Luo	Megrez: Parallelizing FPGA Routing with Strictly-Ordered Partitioning.	FCCM	2017	DBLP DOI BibTeX RDF
1	Qingqing Xiong, Martin C. Herbordt	Bonded Force Computations on FPGAs.	FCCM	2017	DBLP DOI BibTeX RDF
1	Youngsoo Kim, Hossein Shahdoost, Shrikant Jadhav, Clay S. Gloster Jr.	Improving the Accuracy of Arctan for Face Detection.	FCCM	2017	DBLP DOI BibTeX RDF
1	Almomany Abedalmuhdi, B. Earl Wells, Ken-ichi Nishikawa	Efficient Particle-Grid Space Interpolation of an FPGA-Accelerated Particle-in-Cell Plasma Simulation.	FCCM	2017	DBLP DOI BibTeX RDF
1	Dimitris Theodoropoulos, Nikolaos Alachiotis 0001, Dionisios N. Pnevmatikatos	Multi-FPGA Evaluation Platform for Disaggregated Computing.	FCCM	2017	DBLP DOI BibTeX RDF
1	Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun 0003, Wei Zhang 0012, Jason Cong	FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates.	FCCM	2017	DBLP DOI BibTeX RDF
1	Jack Wadden, Samira Manabi Khan, Kevin Skadron	Automata-to-Routing: An Open-Source Toolchain for Design-Space Exploration of Spatial Automata Processing Architectures.	FCCM	2017	DBLP DOI BibTeX RDF
1	Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel	Scheduling Considerations for Voter Checking in TMR-MER Systems.	FCCM	2017	DBLP DOI BibTeX RDF

Publications at "FCCM"( http://dblp.L3S.de/Venues/FCCM )