Search results for "FPT"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Koya Mitsuzuka, Yuta Tokusashi, Hiroki Matsutani	MultiMQC: A Multilevel Message Queuing Cache Combining In-NIC and In-Kernel Memories.	FPT	2018	DBLP DOI BibTeX RDF
1	Kuang Ping Niu, Jason Helge Anderson	Compact Area and Performance Modelling for CGRA Architecture Evaluation.	FPT	2018	DBLP DOI BibTeX RDF
1	Hongxiang Fan, Shuanglong Liu, Martin Ferianc, Ho-Cheung Ng, Zhiqiang Que, Shen Liu, Xinyu Niu, Wayne Luk	A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA.	FPT	2018	DBLP DOI BibTeX RDF
1	Tian Tan 0007, Eriko Nurvitadhi, David Shih, Derek Chiou	Evaluating The Highly-Pipelined Intel Stratix 10 FPGA Architecture Using Open-Source Benchmarks.	FPT	2018	DBLP DOI BibTeX RDF
1	Jin Hee Kim, Jongeun Lee, Jason Helge Anderson	FPGA Architecture Enhancements for Efficient BNN Implementation.	FPT	2018	DBLP DOI BibTeX RDF
1	Jorge Echavarria, Stefan Wildermann, Jürgen Teich	AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs.	FPT	2018	DBLP DOI BibTeX RDF
1	Shaoxia Fang, Lu Tian, Junbin Wang, Shuang Liang 0010, Dongliang Xie, Zhongmin Chen, Lingzhi Sui, Qian Yu, Xiaoming Sun, Yi Shan, Yu Wang 0002	Real-Time Object Detection and Semantic Segmentation Hardware System with Deep Learning Networks.	FPT	2018	DBLP DOI BibTeX RDF
1	Sadegh Yazdanshenas, Vaughn Betz	Improving Confidentiality in Virtualized FPGAs.	FPT	2018	DBLP DOI BibTeX RDF
1	Kevin E. Murray, Vaughn Betz	Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved Optimization.	FPT	2018	DBLP DOI BibTeX RDF
1	Kento Tajiri, Tsutomu Maruyama	FPGA Acceleration of a Supervised Learning Method for Hyperspectral Image Classification.	FPT	2018	DBLP DOI BibTeX RDF
1	Leandro de Souza Rosa, Vanderlei Bonato, Christos-Savvas Bouganis	Scaling Up Loop Pipelining for High-Level Synthesis: A Non-iterative Approach.	FPT	2018	DBLP DOI BibTeX RDF
1	Brett Grady, Jason Helge Anderson	Synthesizable Heterogeneous FPGA Fabrics.	FPT	2018	DBLP DOI BibTeX RDF
1	Mike Strickland	FPGA Accelerated HPC and Data Analytics.	FPT	2018	DBLP DOI BibTeX RDF
1	Bowen P. Y. Kwan, Gary C. T. Chow, Tim Todman, Wayne Luk, Wenguang Xu	Lossy Multiport Memory.	FPT	2018	DBLP DOI BibTeX RDF
1	Akira Kojima, Yohei Nose	Development of an Autonomous Driving Robot Car Using FPGA.	FPT	2018	DBLP DOI BibTeX RDF
1	Haomiao Wang, Ben Stappers, Prabu Thiagaraj, Oliver Sinnen	Optimisation of Convolution of Multiple Different Sized Filters in SKA Pulsar Search Engine.	FPT	2018	DBLP DOI BibTeX RDF
1	Dionysios Diamantopoulos, Christoph Hagleitner	A System-Level Transprecision FPGA Accelerator for BLSTM Using On-chip Memory Reshaping.	FPT	2018	DBLP DOI BibTeX RDF
1	Qiangpu Chen, Minghua Shen, Nong Xiao	DP-Pack: Distributed Parallel Packing for FPGAs.	FPT	2018	DBLP DOI BibTeX RDF
1	Matthew B. Ashcraft, Jeffrey Goeders	Unified On-Chip Software and Hardware Debug for HLS-Accelerated Programs.	FPT	2018	DBLP DOI BibTeX RDF
1	Nadeen Gebara, Jiuxi Meng, Wayne Luk, Paolo Costa	Scheduling Algorithms for High Performance Network Switching on FPGAs: A Survey.	FPT	2018	DBLP DOI BibTeX RDF
1	Hideharu Amano	Accelerator-in-Switch: A Novel Cooperation Framework for FPGAs and GPUs.	FPT	2018	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato	A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector.	FPT	2018	DBLP DOI BibTeX RDF
1	Krystine Dawn Sherwin, Ben Stappers, Prabu Thiagaraj, Kevin I-Kai Wang, Oliver Sinnen	Investigating How Hardware Architectures are Expressed in High-Level Languages for an SKA Algorithm.	FPT	2018	DBLP DOI BibTeX RDF
1	Kristiyan Manev, Dirk Koch	Large Utility Sorting on FPGAs.	FPT	2018	DBLP DOI BibTeX RDF
1	Yunhui Qiu, Hankun Lv, Jinyu Xie, Wenbo Yin, Lingli Wang	Ultra-Low-Latency and Flexible In-memory Key-Value Store System Design on CPU-FPGA.	FPT	2018	DBLP DOI BibTeX RDF
1	Shuanglong Liu, Chenglong Zeng, Hongxiang Fan, Ho-Cheung Ng, Jiuxi Meng, Zhiqiang Que, Xinyu Niu, Wayne Luk	Memory-Efficient Architecture for Accelerating Generative Networks on FPGA.	FPT	2018	DBLP DOI BibTeX RDF
1	Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar 0001	QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning.	FPT	2018	DBLP DOI BibTeX RDF
1	Shane T. Fleming, David B. Thomas	Injecting FPGA Configuration Faults in Parallel.	FPT	2018	DBLP DOI BibTeX RDF
1	Robert Hale, Brad L. Hutchings	Distributed-Memory Based FPGA Debug: Design Timing Impact.	FPT	2018	DBLP DOI BibTeX RDF
1	Jakub Cabal, Lukás Kekely, Jan Korenek	High-Speed Computation of CRC Codes for FPGAs.	FPT	2018	DBLP DOI BibTeX RDF
1	Wenzhi Fu, Jianlei Yang 0001, Pengcheng Dai, Yiran Chen 0001, Weisheng Zhao	A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform.	FPT	2018	DBLP DOI BibTeX RDF
1	Antoniette Mondigo, Kentaro Sano, Hiroyuki Takizawa	Enhancing Memory Bandwidth in a Single Stream Computation with Multiple FPGAs.	FPT	2018	DBLP DOI BibTeX RDF
1	Dennis R. E. Gnad, Sascha Rapp, Jonas Krautter, Mehdi Baradaran Tahoori	Checking for Electrical Level Security Threats in Bitstreams for Multi-tenant FPGAs.	FPT	2018	DBLP DOI BibTeX RDF
1	Nam Ho, Paul Kaufmann, Marco Platzner	Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor.	FPT	2017	DBLP DOI BibTeX RDF
1	Taito Manabe, Yuichiro Shibata, Kiyoshi Oguri	FPGA implementation of a real-time super-resolution system with a CNN based on a residue number system.	FPT	2017	DBLP DOI BibTeX RDF
1	Hai Peng, Xiaofan Zhang 0001, Letian Huang	An energy efficient approach for C4.5 algorithm using OpenCL design flow.	FPT	2017	DBLP DOI BibTeX RDF
1	Harald Homulle, Edoardo Charbon	Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperatures.	FPT	2017	DBLP DOI BibTeX RDF
1	Rongdi Sun, Peilin Liu, Jun Wang 0137, Cecil Accetti, Abid A. Naqvi	A 42fps full-HD ORB feature extraction accelerator with reduced memory overhead.	FPT	2017	DBLP DOI BibTeX RDF
1	Baofu Zhao, Yubin Li, Yu Wang 0002, Huazhong Yang	Streaming sorting network based BWT acceleration on FPGA for lossless compression.	FPT	2017	DBLP DOI BibTeX RDF
1	Daewoo Kim, Mansureh S. Moghaddam, Hossein Moradian, Hyeon Uk Sim, Jongeun Lee, Kiyoung Choi	FPGA implementation of convolutional neural network based on stochastic computing.	FPT	2017	DBLP DOI BibTeX RDF
1	Moucheng Yang, Jifang Jin, Zhehao Li, Xuegong Zhou, Shaojun Wang, Lingli Wang	A scalable hybrid architecture for high performance data-parallel applications.	FPT	2017	DBLP DOI BibTeX RDF
1	Sadegh Yazdanshenas, Vaughn Betz	Automatic circuit design and modelling for heterogeneous FPGAs.	FPT	2017	DBLP DOI BibTeX RDF
1	Lekhobola J. Tsoeunyane, Simon Winberg, Michael Inggs	An IP core integration tool-flow for prototyping software-defined radios using static dataflow with access patterns.	FPT	2017	DBLP DOI BibTeX RDF
1	He Li 0008, James J. Davis 0001, John Wickerson, George A. Constantinides	architect: Arbitrary-precision constant-hardware iterative compute.	FPT	2017	DBLP DOI BibTeX RDF
1	Mankit Sit, Ryosuke Kazami, Hideharu Amano	FPGA-based accelerator for losslessly quantized convolutional neural networks.	FPT	2017	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato	An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA.	FPT	2017	DBLP DOI BibTeX RDF
1	Hossein Omidian, Guy G. F. Lemieux	Exploring automated space/time tradeoffs for OpenVX compute graphs.	FPT	2017	DBLP DOI BibTeX RDF
1	Yoshikazu Watanabe, Yuki Kobayashi, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura 0002	Accelerating NFV application using CPU-FPGA tightly coupled architecture.	FPT	2017	DBLP DOI BibTeX RDF
1	Jincheng Yu, Yiming Hu, Xuefei Ning, Jiantao Qiu, Kaiyuan Guo, Yu Wang 0002, Huazhong Yang	Instruction driven cross-layer CNN accelerator with winograd transformation on FPGA.	FPT	2017	DBLP DOI BibTeX RDF
1		International Conference on Field Programmable Technology, FPT 2017, Melbourne, Australia, December 11-13, 2017	FPT	2017	DBLP BibTeX RDF
1	Shaoyi Cheng, Qijing Huang 0001, John Wawrzynek	Synthesis of program binaries into FPGA accelerators with runtime dependence validation.	FPT	2017	DBLP DOI BibTeX RDF
1	P. M. K. Tharaka, D. M. D. Wijerathne, Navoda Perera, Dinushan Vishwajith, Ajith Pasqual	Runtime rule-reconfigurable high throughput NIPS on FPGA.	FPT	2017	DBLP DOI BibTeX RDF
1	Erik H. D'Hollander, Bruno Chevalier, Koen De Bosschere	Calling hardware procedures in a reconfigurable accelerator using RPC-FPGA.	FPT	2017	DBLP DOI BibTeX RDF
1	William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj	Comparing the cost of protecting selected lightweight block ciphers against differential power analysis in low-cost FPGAs.	FPT	2017	DBLP DOI BibTeX RDF
1	Wei Li, Yangyang Zhao, Yuhang Liu 0001, Mingyu Chen 0001	SMEFF: A scalable memory extension fabric for FPGA.	FPT	2017	DBLP DOI BibTeX RDF
1	Jack Yinger, Eriko Nurvitadhi, Davor Capalija, Andrew C. Ling, Debbie Marr, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra	Customizable FPGA OpenCL matrix multiply design template for deep neural networks.	FPT	2017	DBLP DOI BibTeX RDF
1	Donald G. Bailey	Hough transform line reconstruction on FPGA using back-projection.	FPT	2017	DBLP DOI BibTeX RDF
1	Prajith Ramakrishnan Geethakumari, Vincenzo Gulisano, Bo Joel Svensson, Pedro Trancoso, Ioannis Sourdis	Single window stream aggregation using reconfigurable hardware.	FPT	2017	DBLP DOI BibTeX RDF
1	Siew-Kei Lam, Rakesh Kumar Bijarniya, Meiqing Wu	Lowering dynamic power in stream-based harris corner detection architecture.	FPT	2017	DBLP DOI BibTeX RDF
1	Shadi Assadikhomami, Jennifer Ongko, Tor M. Aamodt	A state machine block for high-level synthesis.	FPT	2017	DBLP DOI BibTeX RDF
1	Andrew Ang, Matt Bourne, Robin Dykstra	An open source PXIe ecosystem based on FPGA modules.	FPT	2017	DBLP DOI BibTeX RDF
1	Sam M. H. Ho, Hayden Kwok-Hay So	NnCore: A parameterized non-linear function generator for machine learning applications in FPGAs.	FPT	2017	DBLP DOI BibTeX RDF
1	Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt	Liquid: High quality scalable placement for large heterogeneous FPGAs.	FPT	2017	DBLP DOI BibTeX RDF
1	Junqi Yuan, Lingli Wang, Xuegong Zhou, Yinshui Xia, Jianping Hu	RBSA: Range-based simulated annealing for FPGA placement.	FPT	2017	DBLP DOI BibTeX RDF
1	Qian Zhao 0001, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi	hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds.	FPT	2017	DBLP DOI BibTeX RDF
1	Ahmad Salman, William Diehl, Jens-Peter Kaps	A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption.	FPT	2017	DBLP DOI BibTeX RDF
1	Bingyi Li, Linlin Fang, Yizhuang Xie, He Chen, Liang Chen 0004	A unified reconfigurable floating-point arithmetic architecture based on CORDIC algorithm.	FPT	2017	DBLP DOI BibTeX RDF
1	Justin S. J. Wong, Runbin Shi, Maolin Wang, Hayden Kwok-Hay So	Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory.	FPT	2017	DBLP DOI BibTeX RDF
1	Felix Winterstein, George A. Constantinides	Pass a pointer: Exploring shared virtual memory abstractions in OpenCL tools for FPGAs.	FPT	2017	DBLP DOI BibTeX RDF
1	Weikang Fang, Yanjun Zhang, Bo Yu 0014, Shaoshan Liu	FPGA-based ORB feature extraction for real-time visual SLAM.	FPT	2017	DBLP DOI BibTeX RDF
1	Dong Wang 0040, Ke Xu 0011, Diankun Jiang	PipeCNN: An OpenCL-based open-source FPGA accelerator for convolution neural networks.	FPT	2017	DBLP DOI BibTeX RDF
1	Anju P. Johnson, Junxiu Liu, Alan G. Millard, Shvan Karim, Andy M. Tyrrell, Jim Harkin, Jon Timmis, Liam McDaid, David M. Halliday	Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs.	FPT	2017	DBLP DOI BibTeX RDF
1	Patrick Sittel, Konrad Möller, Martin Kumm, Peter Zipf, Bogdan Pasca 0001, Mark Jervis	Model-based hardware design based on compatible sets of isomorphic subgraphs.	FPT	2017	DBLP DOI BibTeX RDF
1	William Kamp	AXI over Ethernet; a protocol for the monitoring and control of FPGA clusters.	FPT	2017	DBLP DOI BibTeX RDF
1	Saud Wasly, Rodolfo Pellizzoni, Nachiket Kapre	HopliteRT: An efficient FPGA NoC for real-time applications.	FPT	2017	DBLP DOI BibTeX RDF
1	Artur Podobas, Satoshi Matsuoka	Designing and accelerating spiking neural networks using OpenCL for FPGAs.	FPT	2017	DBLP DOI BibTeX RDF
1	Roberto DiCecco, Lin Sun, Paul Chow	FPGA-based training of convolutional neural networks with a reduced precision floating-point library.	FPT	2017	DBLP DOI BibTeX RDF
1	Ekawat Homsirikamol, Kris Gaj	Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: The CAESAR contest case study.	FPT	2017	DBLP DOI BibTeX RDF
1	Brice Colombier, Lilian Bossuet, Ugo Mureddu, David Hély	A comprehensive hardware/software infrastructure for IP cores design protection.	FPT	2017	DBLP DOI BibTeX RDF
1	Zhiqiang Liu, Yong Dou, Jingfei Jiang, Qiang Wang 0006, Paul Chow	An FPGA-based processor for training convolutional neural networks.	FPT	2017	DBLP DOI BibTeX RDF
1	Amit Kulkarni 0002, Poona Bahrebar, Dirk Stroobandt, Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu	A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration.	FPT	2017	DBLP DOI BibTeX RDF
1	Dan Cristian Turicu, Octavian Cret, Lucia Vacariu	High performance serial ATA Gen3 controllers on FPGA devices.	FPT	2017	DBLP DOI BibTeX RDF
1	Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara	All binarized convolutional neural network and its implementation on an FPGA.	FPT	2017	DBLP DOI BibTeX RDF
1	Kentaro Katayama, Hidetoshi Matsumura, Hiroaki Kameyama, Shinichi Sazawa, Yasuhiro Watanabe	An FPGA-accelerated high-throughput data optimization system for high-speed transfer via wide area network.	FPT	2017	DBLP DOI BibTeX RDF
1	Ke Cui, Zongkai Liu, Rihong Zhu, Xiangyu Li 0005	FPGA-based high-performance time-to-digital converters by utilizing multi-channels looped carry chains.	FPT	2017	DBLP DOI BibTeX RDF
1	Brian Jarvis, Kris Gaj	Selection of an error-correcting code for FPGA-based physical unclonable functions.	FPT	2017	DBLP DOI BibTeX RDF
1	Weijia Li, Conghui He, Haohuan Fu, Wayne Luk	An FPGA-based tree crown detection approach for remote sensing images.	FPT	2017	DBLP DOI BibTeX RDF
1	Yiren Zhao, John Wickerson, George A. Constantinides	An efficient implementation of online arithmetic.	FPT	2016	DBLP DOI BibTeX RDF
1	Lana Josipovic, Nithin George, Paolo Ienne	Enriching C-based High-Level Synthesis with parallel pattern templates.	FPT	2016	DBLP DOI BibTeX RDF
1	Zhehao Li, Jifang Jin, Lingli Wang, Ji Yang, Jiahua Lu	A moving object extraction and classification system based on Zynq and IBM SuperVessel.	FPT	2016	DBLP DOI BibTeX RDF
1	Eriko Nurvitadhi, David Sheffield, Jaewoong Sim, Asit K. Mishra, Ganesh Venkatesh, Debbie Marr	Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC.	FPT	2016	DBLP DOI BibTeX RDF
1	Li Ding, Ping Kang, Wenbo Yin, Linli Wang	Hardware TCP Offload Engine based on 10-Gbps Ethernet for low-latency network communication.	FPT	2016	DBLP DOI BibTeX RDF
1	Yonghua Lin	FPGA as service in public Cloud: Why and how.	FPT	2016	DBLP DOI BibTeX RDF
1	Yuzhi Zhou, Xi Jin 0002, Tian Xiang	Fixed-ratio DXT format Frame Buffer Compressor for mobile graphics systems.	FPT	2016	DBLP DOI BibTeX RDF
1	Ali Asghar, Muhammad Mazher Iqbal, Waqar Ahmed, Mujahid Ali, Husain Parvez, Muhammad Rashid	Exploring shared SRAM tables among NPN equivalent large LUTs in SRAM-based FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
1	Quentin Gautier, Alric Althoff, Pingfan Meng, Ryan Kastner	Spector: An OpenCL FPGA benchmark suite.	FPT	2016	DBLP DOI BibTeX RDF
1	Lingkan Gong, Tong Wu 0007, Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Zhuoran Zhao, Ediz Cetin, Oliver Diessel	A Programmable Configuration Controller for fault-tolerant applications.	FPT	2016	DBLP DOI BibTeX RDF
1	Martin Krcma, Zdenek Kotásek, Jakub Lojda	Implementation of fault tolerant techniques into FPNNs.	FPT	2016	DBLP DOI BibTeX RDF
1	Lin Li, Quansheng Yang	SMCFA: A Zynq-based stacked multi CPU-FPGA architecture.	FPT	2016	DBLP DOI BibTeX RDF
1	Otávio Alcântara de Lima Jr., Weslley N. Costa, Virginie Fresse, Frédéric Rousseau 0001	A survey of NoC evaluation platforms on FPGAs.	FPT	2016	DBLP DOI BibTeX RDF

Publications at "FPT"( http://dblp.L3S.de/Venues/FPT )