Search results for "HLDVT"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante	High-level test generation for hardware testing and software validation.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Alessandro Fin, Franco Fummi	Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?	HLDVT	2003	DBLP DOI BibTeX RDF
1	Moshe Levinger, Avi Ziv, Brian Bailey, Jacob Abraham, Bob Bentley, William H. Joyner, Yaron Kas	Panel: What's the next 'big thing' in simulation-based verification?	HLDVT	2003	DBLP DOI BibTeX RDF
1	Flávio Miana de Paula, Claudionor José Nunes Coelho Jr., Harry Foster, José Augusto Miranda Nacif, Joseph Tompkins, Antônio Otávio Fernandes, Diógenes Cecilio da Silva Jr.	Refactoring digital hardware designs with assertion libraries.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang	A comparison of BDDs, BMC, and sequential SAT for model checking.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Roy Emek, Yehuda Naveh	Scheduling of transactions for system-level test-case generation.	HLDVT	2003	DBLP DOI BibTeX RDF
1	K. C. Shashidhar, Maurice Bruynooghe, Francky Catthoor, Gerda Janssens	Automatic functional verification of memory oriented global source code transformations.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Kameshwar Chandrasekar, Michael S. Hsiao	ATPG-based preimage computation: efficient search space pruning with ZBDD.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Franco Fummi, Cristina Marconcini, Graziano Pravadelli	Redundant functional faults reduction by saboteurs synthesis [logic verification].	HLDVT	2003	DBLP DOI BibTeX RDF
1	Patrick Schaumont, Kazuo Sakiyama, Yi Fan, David D. Hwang, Shenglin Yang, Alireza Hodjat, Bo-Cheng Lai, Ingrid Verbauwhede	Testing ThumbPod: Softcore bugs are hard to find.	HLDVT	2003	DBLP DOI BibTeX RDF
1		Eighth IEEE International High-Level Design Validation and Test Workshop 2003, San Francisco, CA, USA, November 12-14, 2003	HLDVT	2003	DBLP BibTeX RDF
1	Markus Braun, Wolfgang Rosenstiel, Klaus-Dieter Schubert	Comparison of Bayesian networks and data mining for coverage directed verification category simulation-based verification.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Íñigo Ugarte, Pablo Sanchez	Functional vector generation for assertion-based verification at behavioral level using interval analysis.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Sandeep K. Shukla, Ramesh Karri, Seth Copen Goldstein, Forrest Brewer, Kaustav Banerjee, Sankar Basu	Nano, quantum, and molecular computing: are we ready for the validation and test challenges?	HLDVT	2003	DBLP DOI BibTeX RDF
1	Dhiraj K. Pradhan	Logic transformation and coding theory-based frameworks for Boolean satisfiability.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Xiaoliang Bai, Li Chen, Sujit Dey	Software-based self-test methodology for crosstalk faults in processors.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Dhiraj K. Pradhan, Serkan Askar, Maciej J. Ciesielski	Mathematical framework for representing discrete functions as word-level polynomials.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Shai Fine, Avi Ziv	Enhancing the control and efficiency of the covering process [logic verification].	HLDVT	2003	DBLP DOI BibTeX RDF
1	Rajat Arora, Michael S. Hsiao	Enhancing SAT-based equivalence checking with static logic implications.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Sivaram Gopalakrishnan, Vijay Durairaj, Priyank Kalla	Integrating CNF and BDD based SAT solvers.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Allon Adir, Eyal Bin, Ofer Peled, Avi Ziv	Piparazzi: a test program generator for micro-architecture flow verification.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Fulvio Corno, Paolo Gabrielli, Simonluca Tosato	Relating vehicle-level and network-level reliability through high-level fault injection.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Daniel Große, Rolf Drechsler	BDD-based verification of scalable designs.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Merav Aharoni, Sigal Asaf, Laurent Fournier, Anatoly Koyfman, Raviv Nagel	FPgen - a test generation framework for datapath floating-point verification.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Solaiman Rahim, Bruno Rouzeyre, Lionel Torres, Jérôme Rampon	Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Jennifer Campbell, Nancy A. Day	High-level optimization of pipeline design.	HLDVT	2003	DBLP DOI BibTeX RDF
1	Mohammad Reza Mousavi 0001, Giovanni Russello, Michel R. V. Chaudron, Michel A. Reniers, Twan Basten, Angelo Corsaro, Sandeep K. Shukla, Rajesh K. Gupta 0001, Douglas C. Schmidt	Using Aspect-GAMMA in the design of embedded systems.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Markus Wannemacher, Mihai Munteanu, Sacha Perret, Rolf Singer	Taking the best out of two worlds: prototyping and hardware emulation.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre	A simple and effective compression scheme for test pins reduction.	HLDVT	2002	DBLP DOI BibTeX RDF
1	H. N. Nguyen, P. Koumou, Bernard Candaele, Michel Sarlotte, Christian Antoine, S. Emeriau	Verification of a DSP IP cores by model checking.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Amnon Rosenmann, Ziyad Hanna	Alignability equivalence of synchronous sequential circuits.	HLDVT	2002	DBLP DOI BibTeX RDF
1	A. Castelnuovo, Andrea Fedeli, Alessandro Fin, Franco Fummi, Graziano Pravadelli, Umberto Rossi, F. Sforza, Franco Toto	A 1000X speed up for properties completeness evaluation.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Matteo Sonza Reorda, Massimo Violante, Nicola Mazzocca, Salvatore Venticinque, Andrea Bobbio, Giuliana Franceschinis	A hierarchical approach for designing dependable systems.	HLDVT	2002	DBLP DOI BibTeX RDF
1	César A. M. Marcon, Fabiano Hessel, Alexandre M. Amory, Luis H. L. Ries, Fernando Gehm Moraes, Ney Laert Vilar Calazans	Prototyping of embedded digital systems from SDL language: a case study.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Idriz Smaili, Astrit Ademaj	Setting break-points in distributed time-triggered architecture.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Gert Jervan, Zebo Peng, Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante	High-level and hierarchical test sequence generation.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Allon Adir, Roy Emek, Eitan Marcus	Adaptive test program generation: planning for the unplanned.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Axel G. Braun, Joachim Gerlach, Wolfgang Rosenstiel	Checking temporal properties in SystemC specifications.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Astrit Ademaj	Slightly-off-specification failures in the time-triggered architecture.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Ranan Fraer, Shahid Ikram, Gila Kamhi, Tim Leonard, Abdel Mokkedem	Accelerated verification of RTL assertions based on satisfiability solvers.	HLDVT	2002	DBLP DOI BibTeX RDF
1	David A. Sigüenza-Tortosa, Jari Nurmi	VHDL-based simulation environment for Proteo NoC.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Priyank Kalla, Maciej J. Ciesielski, Emmanuel Boutillon, Eric Martin 0001	High-level design verification using Taylor Expansion Diagrams: first results.	HLDVT	2002	DBLP DOI BibTeX RDF
1	John Dielissen, Benito Otero Mathijssen, Jos Huisken	Breaking an application specific instruction-set processor: the first step towards embedded software testing.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Iuliana Bacivarov, Sungjoo Yoo, Ahmed Amine Jerraya	Timed HW-SW cosimulation using native execution of OS and application SW.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Zurab Khasidashvili, John Moondanos, Ziyad Hanna	TRANS: efficient sequential verification of loop-free circuits.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Bob Bentley	High level validation of next-generation microprocessors.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Hiroshi Saito, Takaya Ogawa, Thanyapat Sakunkonchak, Masahiro Fujita, Takashi Nanya	An equivalence checking methodology for hardware oriented C-based specifications.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Allon Adir, Gil Shurek	Generating concurrent test-programs with collisions for multi-processor verification.	HLDVT	2002	DBLP DOI BibTeX RDF
1	David Malandain, Pim Palmen, Matthew Taylor, Merav Aharoni, Yaron Arbetman	An effective and flexible approach to functional verification of processor families.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Xi Chen 0024, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe	Formal verification of embedded system designs at multiple levels of abstraction.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Fei Xin, Ian G. Harris	Test generation for hardware-software covalidation using non-linear programming.	HLDVT	2002	DBLP DOI BibTeX RDF
1		Seventh IEEE International High-Level Design Validation and Test Workshop 2002, Cannes, France, October 27-29, 2002	HLDVT	2002	DBLP BibTeX RDF
1	Gethin Norman, David Parker 0001, Marta Z. Kwiatkowska, Sandeep K. Shukla, Rajesh K. Gupta 0001	Formal analysis and validation of continuous-time Markov chain based system level power management strategies.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Klaus-Dieter Schubert	Practical experiences in functional simulation. An integrated method from unit to co-simulation.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Gérard Berry, Lionel Blanc, Amar Bouali, Jerome Dormoy	Top-level validation of system-on-chip in Esterel Studio.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Roy Emek, Itai Jaeger, Yehuda Naveh, Gadi Bergman, Guy Aloni, Yoav Katz, Monica Farkash, Igor Dozoretz, Alex Goldin	X-Gen: a random test-case generator for systems and SoCs.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Prabhat Mishra 0001, Nikil D. Dutt	Automatic functional test program generation for pipelined processors using model checking.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Piotr Gawkowski, Janusz Sosnowski	Experimental validation of fault detection and fault tolerance mechanisms.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Alex Wakefield, Bassam Jamil Mohd	Constructing reusable testbenches.	HLDVT	2002	DBLP DOI BibTeX RDF
1	Nabarun Bhattacharyya, A. Wang	Automatic test generation for micro-architectural verification of configurable microprocessor cores with user extensions.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Peer Johannsen	Reducing bitvector satisfiability problems to scale down design sizes for RTL property checking.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Marek Jersak, Kai Richter 0001, Rolf Ernst	Combining complex event models and timing constraints.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Zurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna	An enhanced cut-points algorithm in formal equivalence verification.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Michael S. Hsiao, Jawahar Jain	Practical use of sequential ATPG for model checking: going the extra mile does pay off.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Ganapathy Parthasarathy, Chung-Yang Huang, Kwang-Ting Cheng	An analysis of ATPG and SAT algorithms for formal verification.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Prabhat Mishra 0001, Nikil D. Dutt, Alex Nicolau	Automatic validation of pipeline specifications.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Ian G. Harris	Hardware-software covalidation: fault models and test generation.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Roope Kaivola, Naren Narasimhan	Formal verification of the Pentium(R) 4 multiplier.	HLDVT	2001	DBLP DOI BibTeX RDF
1		Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, Monterey, California, USA, November 7-9, 2001	HLDVT	2001	DBLP BibTeX RDF
1	Sandeep K. Shukla, Rajesh K. Gupta 0001	A model checking approach to evaluating system level dynamic power management policies for embedded systems.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Dong Wang, Edmund M. Clarke, Yunshan Zhu, James H. Kukula	Using cutwidth to improve symbolic simulation and Boolean satisfiability.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Byeong Min, Gwan Choi	RTL functional verification using excitation and observation coverage.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Farzan Fallah, Indradeep Ghosh	Observability enhanced coverage analysis of C programs for functional validation.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris	Test pattern generation for timing-induced functional errors in hardware-software systems.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Shuvendu K. Lahiri, Carl Pixley, Ken Albin	Experience with term level modeling and verification of the M*CORE TM microprocessor core.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre	Taylor expansion diagrams: a new representation for RTL verification.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Annette Bunker, Ganesh Gopalakrishnan	Using live sequence charts for hardware protocol specification and compliance verification.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Claudia Blank, Hans Eveking, Jens Levihn, Gerd Ritter	Symbolic simulation techniques-state-of-the-art and applications.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Noppanunt Utamaphethai, Ronald D. Blanton, John Paul Shen	Relating buffer-oriented microarchitecture validation to high-level pipeline functionality.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Tim Braun, Anne Condon, Alan J. Hu, Kai S. Juse, Marius Laza, Michael Leslie, Rita Sharma	Proving sequential consistency by model checking.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Felice Balarin, Jerry R. Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli	Constraints specification at higher levels of abstraction.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou	On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, Ahmed Amine Jerraya	Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Michael D. McKinney	Integrating Perl, Tcl and C++ into simulation-based ASIC verification environments.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir	A language formalism for verification of PowerPCTM custom memories using compositions of abstract specifications.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Allon Adir, Eitan Marcus, Michal Rimon, Amir Voskoboynik	Improving test quality through resource reallocation.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Kiyoharu Hamaguchi	Symbolic simulation heuristics for high-level design descriptions with uninterpreted functions.	HLDVT	2001	DBLP DOI BibTeX RDF
1	Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero	An RT-level fault model with high gate level correlation.	HLDVT	2000	DBLP DOI BibTeX RDF
1	Robert Pasko, Radim Cmar, Patrick Schaumont, Serge Vernalde	Functional verification of an embedded network component by co-simulation with a real network.	HLDVT	2000	DBLP DOI BibTeX RDF
1	Harry Hsieh, Felice Balarin	Refining abstract equivalence analysis for embedded system design.	HLDVT	2000	DBLP DOI BibTeX RDF
1	Cordula Hansen, Wolfgang Rosenstiel	Transformation of algorithmic simulation vector sets considering mapping problems of I/O operations.	HLDVT	2000	DBLP DOI BibTeX RDF
1	Hajime Yamashita, Hiroto Yasuura, Eko Fajar, Yun Cao	Variable size analysis and validation of computation quality.	HLDVT	2000	DBLP DOI BibTeX RDF
1	Matthias Pflanz, Christian Galke, Heinrich Theodor Vierhaus	A new method for on-line state machine observation for embedded microprocessors.	HLDVT	2000	DBLP DOI BibTeX RDF
1	Debashis Panigrahi, Clark N. Taylor, Sujit Dey	Interface based hardware/software validation of a system-on-chip.	HLDVT	2000	DBLP DOI BibTeX RDF
1	Jürgen Ruf, Dirk W. Hoffmann, Thomas Kropf, Wolfgang Rosenstiel	Checking temporal properties under simulation of executable system descriptions.	HLDVT	2000	DBLP DOI BibTeX RDF
1	Sandhya Seshadri, Michael S. Hsiao	Formal operator testability methods for behavioral-level DFT using value ranges.	HLDVT	2000	DBLP DOI BibTeX RDF
1	Amjad Hajjar, Tom Chen 0001, Anneliese von Mayrhauser	On statistical behavior of branch coverage in testing behavioral VHDL models.	HLDVT	2000	DBLP DOI BibTeX RDF
1	Mihai T. Lazarescu, Jwahar R. Bammi, Edwin A. Harcourt, Luciano Lavagno, Marcello Lajolo	Compilation-based software performance estimation for system level design.	HLDVT	2000	DBLP DOI BibTeX RDF
1	Tianjing Jiang, Robert H. Klenke, James H. Aylor, Gang Han	System level testability analysis using Petri nets.	HLDVT	2000	DBLP DOI BibTeX RDF

Publications at "HLDVT"( http://dblp.L3S.de/Venues/HLDVT )