| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo O. Johann, Ricardo Augusto da Luz Reis |
Drive Strength Aware Cell Movement Techniques for Timing Driven Placement.  |
ISPD  |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Xu, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, David Z. Pan |
A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ralph Otten |
Complexity and Diversity in IC Layout Design. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Wen-Hsiang Chang, Li-De Chen, Chien-Hsueh Lin, Szu-Pang Mu, Mango Chia-Tso Chao, Cheng-Hong Tsai, Yen-Chih Chiu |
Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Johann Knechtel, Jens Lienig |
Physical Design Automation for 3D Chip Stacks: Challenges and Solutions. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ang Lu, Hao He, Jiang Hu |
Proximity Optimization for Adaptive Circuit Design. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sabya Das, Rajat Aggarwal, Zhiyong Wang |
An Interactive Physical Synthesis Methodology for High-Frequency FPGA Designs. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Filipp Akopyan |
Design and Tool Flow of IBM's TrueNorth: an Ultra-Low Power Programmable Neurosynaptic Chip with 1 Million Neurons. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Julien Ryckaert |
Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephen Yang, Aman Gayasen, Chandra Mulpuri, Sainath Reddy, Rajat Aggarwal |
Routability-Driven FPGA Placement Contest. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Hantao Huang, Hao Yu 0001, Cheng Zhuo, Fengbo Ren |
A Compressive-sensing based Testing Vehicle for 3D TSV Pre-bond and Post-bond Testing Data. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Patrick R. Groeneveld |
Optimizing for Power, Speed, Cost and Emissions in Automotive Drivetrains. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Antun Domic |
Some Observations on the Physical Design of the Next Decade. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Patrick R. Groeneveld |
Trailblazing Physical Design Flows: Ralph Otten's Impact on Design Automation. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Lukas P. P. P. van Ginneken |
The Annealing Algorithm revisted. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhi-Wen Lin, Yao-Wen Chang |
Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Tiago J. Reimann, Cliff C. N. Sze, Ricardo Reis 0001 |
Cell Selection for High-Performance Designs in an Industrial Design Flow. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kevin Zhang 0001 |
Circuit Design in Nano-Scale CMOS Technologies. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jingwei Lu, Hao Zhuang 0001, Ilgweon Kang, Pengwen Chen, Chung-Kuan Cheng |
ePlace-3D: Electrostatics based Placement for 3D-ICs. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Guojie Luo, Wentai Zhang 0001, Jiaxi Zhang 0001, Jason Cong |
Scaling Up Physical Design: Challenges and Opportunities. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Raymond X. Nijssen |
Challenges and Opportunities with Place and Route of Modern FPGA Designs. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Rickard Ewetz, Chuan Yean Tan, Cheng-Kok Koh |
Construction of Latency-Bounded Clock Trees. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Greg Ford |
A Designer's Perspective on Timing Closure. |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young, Mustafa Ozdal (eds.) |
Proceedings of the 2016 on International Symposium on Physical Design, ISPD 2016, Santa Rosa, CA, USA, April 3-6, 2016 |
ISPD |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Qin Wang 0005, Weiran He, Hailong Yao, Tsung-Yi Ho, Yici Cai |
SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Jürgen Scheible, Jens Lienig |
Automation of Analog IC Layout: Challenges and Solutions. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Han, Jianghao Guo, Qiang Xu 0001, Wen-Ben Jone |
On Resilient System Performance Binning. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Mayler G. A. Martins, Jody Maick Matos, Renato P. Ribas, André Inácio Reis, Guilherme Schlinker, Lucio Rech, Jens Michelsen |
Open Cell Library in 15nm FreePDK Technology. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Li-C. Wang, Malgorzata Marek-Sadowska |
Machine Learning in Simulation-Based Analysis. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Dean Drako |
Concept & Research to Revenue: An Entrepreneurial Story. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Karim Arabi, Kambiz Samadi, Yang Du 0001 |
3D VLSI: A Scalable Integration Beyond 2D. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Wei Huang, Martin D. F. Wong |
Accelerated Path-Based Timing Analysis with MapReduce. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Rob A. Rutenbar |
Analog Circuit and Layout Synthesis Revisited. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Rickard Ewetz, Cheng-Kok Koh |
A Useful Skew Tree Framework for Inserting Large Safety Margins. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Lin 0007, Chris C. N. Chu |
TPL-Aware Displacement-driven Detailed Placement Refinement with Coloring Constraints. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Chrystian Guth, Vinicius S. Livramento, Renan Netto, Renan Fonseca, José Luís Güntzel, Luiz C. V. dos Santos |
Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Olivier Billoint, Hossam Sarhan, Iyad Rayane, Maud Vinet, Perrine Batude, Claire Fenouillet-Béranger, Olivier Rozeau, Gerald Cibrario, Fabien Deprat, Ogun Turkyilmaz, Sébastien Thuries, Fabien Clermidy |
From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Ulrich Brenner, Anna Hermann, Nils Hoppmann, Philipp Ochsendorf |
BonnPlace: A Self-Stabilizing Placement Framework. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Hans Eisenmann |
Force-Directed Placement of VLSI Circuits. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Po-Hsun Wu, Mark Po-Hung Lin, Xin Li 0001, Tsung-Yi Ho |
Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Michiel Oostindie, Coby Zelnik, Maarten Berkens |
Design Rule Management and its Applications in 15nm FreePDK Technology. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsi-An Chien, Szu-Yuan Han, Ye-Hong Chen, Ting-Chi Wang |
A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Ulf Schlichtmann |
Beyond GORDIAN and Kraftwerk: EDA Research at TUM. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | H.-S. Philip Wong, He Yi, Maryann C. Tung, Kye Okabe |
Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Farid N. Najm |
Physical Design Challenges in the Chip Power Distribution Network. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Ismail S. Bustany, David G. Chinnery, Joseph R. Shinnerl, Vladimir Yutsis |
ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Abbasinasab, Malgorzata Marek-Sadowska |
Blech Effect in Interconnects: Applications and Design Guidelines. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Kai Wang, Chuan-Chia Huang, Shih-Ying Sean Liu, Ching-Yu Chin, Sheng-Te Hu, Wei-Chen Wu, Hung-Ming Chen |
Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Kirti Bhanushali, W. Rhett Davis |
FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Chang Xu 0005, Peixin Li, Guojie Luo, Yiyu Shi 0001, Iris Hui-Ru Jiang |
Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Sungmin Bae, Hyung-Ock Kim, Jung Yun Choi, Jaehong Park |
Coarse-grained Structural Placement for a Synthesized Parallel Multiplier. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin D. F. Wong |
Early Days of Circuit Placement. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Guang Chen, Wan-Yu Wen, Tao Wang, Yiyu Shi 0001, Shih-Chieh Chang |
Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Jody Maick Matos, Augusto Neutzling, Renato P. Ribas, André Inácio Reis |
A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design. |
ISPD |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Vladimir Yutsis, Ismail Bustany, David G. Chinnery, Joseph R. Shinnerl, Wen-Hao Liu |
ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Shang-Tsung Yu, Sheng-Han Yeh, Tsung-Yi Ho |
Reliability-driven chip-level design for high-frequency digital microfluidic biochips. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Qi Zhu 0002, Peng Deng |
Design synthesis and optimization for automotive embedded systems. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert C. Aitken, Greg Yeric, Brian Cline, Saurabh Sinha, Lucian Shifren, Imran Iqbal, Vikas Chandra |
Physical design and FinFETs. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong |
From design to design automation. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Tung Ho, Yu-Min Lee, Shu-Han Wei, Liang-Chia Cheng |
Incremental transient simulation of power grid. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Massoud Pedram |
Interconnect length estimation in VLSI designs: a retrospective. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhasish Mitra |
Carbon nanotube computer: transforming scientific discoveries into working systems. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajat Aggarwal |
FPGA place & route challenges. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael J. Lorenzetti |
Making a difference in EDA: a thank you to Bryan Preas for his contributions to the profession. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Caleb Serafy, Ankur Srivastava 0001 |
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Shreepad Panth, Kambiz Samadi, Yang Du 0001, Sung Kyu Lim |
Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Anand Arunachalam 0001 |
Integrated structured placement design methodology in place and route flow. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Scott Elrod |
Bryan Preas: broad contributions to system engineering in the 2000's. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan |
Clock tree resynthesis for multi-corner multi-mode timing closure. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Bryan Preas |
Smart matter systems, an introduction through examples. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu 0001, David Z. Pan |
Self-aligned double patterning aware pin access and standard cell layout co-optimization. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang |
A study on unroutable placement recognition. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuai Li, Cheng-Kok Koh |
MIP-based detailed placer for mixed-size circuits. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Serge Leef |
Hardware cyber security. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Cliff C. N. Sze, Azadeh Davoodi (eds.) |
International Symposium on Physical Design, ISPD'14, Petaluma, CA, USA, March 30 - April 02, 2014 |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Wing-Kai Chow, Jian Kuang 0001, Xu He, Wenzan Cai, Evangeline F. Y. Young |
Cell density-driven detailed placement with displacement constraint. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Jai-Ming Lin, Che-Chun Lin, Zong-Wei Syu, Chih-Chung Tsai, Kevin Huang |
Current density aware power switch placement algorithm for power gating designs. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian Kuang 0001, Evangeline F. Y. Young |
A highly-efficient row-structure stencil planning approach for e-beam lithography with overlapped characters. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Held, Sophie Theresa Spirkl |
A fast algorithm for rectilinear steiner trees with length restrictions on obstacles. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chuan Lo, Chih-Cheng Hsu, Mark Po-Hung Lin |
Power optimization for clock network with clock gate cloning and flip-flop merging. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | William Wu Shen |
3DIC system design impact, challenge and solutions. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Gi-Joon Nam, Sani R. Nassif |
Opportunities in power distribution network system optimization: from EDA perspective. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Yilin Zhang, David Z. Pan |
Timing-driven, over-the-block rectilinear steiner tree construction with pre-buffering and slew constraints. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin Hu, Debjit Sinha, Igor Keller |
TAU 2014 contest on removing common path pessimism during timing analysis. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Fan Ye |
Indoor localization technology and algorithm issues. |
ISPD |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Shigetoshi Nakatake |
Practicality on placement given by optimality of packing. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Rickard Ewetz, Cheng-Kok Koh |
Local merges for effective redundancy in clock networks. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Han Tseng, Sheng-Chi You, Jhe-Yu Liou, Tsung-Yi Ho |
A top-down synthesis methodology for flow-based microfluidic biochips considering valve-switching minimization. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Shigeki Nojima |
Optical lithography extension with double patterning. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | James D. Warnock |
Circuit and PD challenges at the 14nm technology node. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | David G. Chinnery |
High performance and low power design techniques for ASIC and custom in nanometer technologies. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo |
An improved benchmark suite for the ISPD-2013 discrete cell sizing contest. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Debjit Sinha, Luís Guerra e Silva, Jia Wang, Shesha Raghunathan, Dileep Netrabile, Ahmed Shebaita |
TAU 2013 variation aware timing analysis contest. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Hua Xiang 0001, Minsik Cho, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri |
Network flow based datapath bit slicing. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | John Giacobbe |
Physical design for debug: insurance policy for IC's. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Atsushi Takahashi 0001 |
Dawn of computer-aided design: from graph-theory to place and route. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Jens Lienig |
Electromigration and its impact on physical design in future technologies. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Pei-Wen Luo, Chun Zhang, Yung-Tai Chang, Liang-Chia Cheng, Hung-Hsie Lee, Bih-Lan Sheu, Yu-Shih Su, Ding-Ming Kwai, Yiyu Shi 0001 |
Benchmarking for research in power delivery networks of three-dimensional integrated circuits. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Kenneth S. Stevens |
Relative timing driven multi-synchronous design: enabling order-of-magnitude energy reduction. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Xu He, Wing-Kai Chow, Evangeline F. Y. Young |
SRP: simultaneous routing and placement for congestion refinement. |
ISPD |
2013 |
DBLP DOI BibTeX RDF |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")
data released under the ODC-BY 1.0 license