Search results for "ReConFig"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Tassadaq Hussain, Nehir Sönmez, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Shakaib A. Gursal	PAMS: Pattern Aware Memory System for embedded systems.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Sam Skalicky, Tyler Kwolek, Sonia López, Marcin Lukowiak	Enabling FPGA support in Matlab based heterogeneous systems.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Zhuo Qian, Martin Margala	Low power RAM-based hierarchical CAM on FPGA.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Yu Bai 0004, Mingjie Lin	Stochastically computing discrete Fourier transform with reconfigurable digital fabric.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Ekawat Homsirikamol, Kris Gaj	Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri	Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Quang Hoa Le, Emmanuel Casseau, Antoine Courtay	Place Reservation technique for online task placement on a multi-context heterogeneous reconfigurable architecture.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Misael Lopez-Ramirez, Luis Manuel Ledesma-Carrillo, Ana L. Martinez-Herrera, Eduardo Cabal-Yepez, Homero Miranda-Vidales	FPGA-based reconfigurable unit for real-time power quality index estimation.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Tomas Drahonovsky, Martin Rozkovec, Ondrej Novák	A highly flexible reconfigurable system on a Xilinx FPGA.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Friedrich Wiemer, Ralf Zimmermann	High-speed implementation of bcrypt password search using special-purpose hardware.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Rajesh G. Kavasseri, Mohammad A. Zare	Net reordering and multicommodity flow based global routing for FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Shijie Zhou 0001, Sihan Zhao, Viktor K. Prasanna	400 Gbps energy-efficient multi-field packet classification on FPGA.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Mohammed M. Farag, Mohammad A. Ewais	Smart employment of circuit redundancy to effectively counter trojans (SECRET) in third-party IP cores.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Daniel Kirschberger, Holger Flatt, Jürgen Jasperneite	An architectural approach for reconfigurable industrial I/O devices.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Alexandra Kourfali, Elias Vansteenkiste, Dirk Stroobandt	Parameterised FPGA reconfigurations for efficient test set generation.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Mohammad A. Zare, Rajesh G. Kavasseri, Cristinel Ababei	FPGA-based design and implementation of direct torque control for induction machines.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Daniel Tortei Tertei, Jonathan Piat, Michel Devy	FPGA design and implementation of a matrix multiplier based accelerator for 3D EKF SLAM.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Fynn Schwiegelshohn, Michael Hübner 0001	Design of an attention detection system on the Zynq-7000 SoC.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Rico Backasch, Gerald Hempel, Stefan Werner 0002, Sven Groppe, Thilo Pionteck	Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Khaled E. Ahmed, Mohammed M. Farag	Overloaded CDMA bus topology for MPSoC interconnect.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Vignesh Adhinarayanan, Thaddeus Koehn, Krzysztof Kepa, Wu-chun Feng, Peter Athanas	On the performance and energy efficiency of FPGAs and GPUs for polyphase channelization.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek	PoC-align: An open-source alignment accelerator using FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Alfredo Espinoza-Rhoton, Luis F. Gonzalez-Perez, J. L. Ponce, Borrayo-S. Hector, Lennin C. Yllescas-Calderon, Ramón Parra-Michel, Hassan Aboushady	An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio paradigm.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Byron Navas, Johnny Öberg, Ingo Sander	On providing scalable self-healing adaptive fault-tolerance to RTR SoCs.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Peter Reichel, Jens Döge	Hardware/software infrastructure for ASIC commissioning and rapid system prototyping.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Gang Chen 0023, Biao Hu 0001, Kai Huang 0001, Alois C. Knoll, Kai Huang 0002, Di Liu 0002, Todor P. Stefanov	Automatic cache partitioning and time-triggered scheduling for real-time MPSoCs.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Shinya Takamaeda-Yamazaki, Kenji Kise	A framework for efficient rapid prototyping by virtually enlarging FPGA resources.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Shanyuan Gao, Jeremy Chritz	Characterization of OpenCL on a scalable FPGA architecture.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Andreas Emeretlis, George Theodoridis, George-Othon Glentis	High-performance FPGA implementations of volterra DFEs for optical fiber systems.	ReConFig	2014	DBLP DOI BibTeX RDF
1	James Demma, Peter Athanas	A hardware generator for factor graph applications.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Felipe A. P. de Figueiredo, Fabiano S. Mathilde, Fabbryccio A. C. M. Cardoso, Rafael M. Vilela, Joao Paulo Miranda	Efficient FPGA-based implementation of a CAZAC sequence generator for 3GPP LTE.	ReConFig	2014	DBLP DOI BibTeX RDF
1		2014 International Conference on ReConFigurable Computing and FPGAs, ReConFig14, Cancun, Mexico, December 8-10, 2014	ReConFig	2014	DBLP BibTeX RDF
1	Jose Fernando Zazo, Marco Forconesi, Sergio López-Buedo, Gustavo Sutter, Javier Aracil 0001	TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Konrad Häublein, Marc Reichenbach, Dietmar Fey	Fast and generic hardware architecture for stereo block matching applications on embedded systems.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Poona Bahrebar, Dirk Stroobandt	Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Carlos Andres Lara-Nino, César Torres-Huitzil, Jose Hugo Barron-Zambrano	Versatile educational and research robotic platform based on reconfigurable hardware.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Tobias Wiersema, Arne Bockhorn, Marco Platzner	Embedding FPGA overlays into configurable Systems-on-Chip: ReconOS meets ZUMA.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Tom Davidson, Dirk Stroobandt	Data path analysis for dynamic circuit specialisation.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Saki Hatta, Nobuyuki Tanaka, Satoshi Shigematsu	Area-efficient dynamically reconfigurable protocol-processing-hardware for access network communications SoC.	ReConFig	2014	DBLP DOI BibTeX RDF
1	An Hung Nguyen, Mark R. Pickering, Andrew J. Lambert	The FPGA implementation of an image registration algorithm using binary images.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Jorge Echavarria, Alicia Morales-Reyes, René Cumplido, Miguel A. Salido	FSM merging and reduction for IP cores watermarking using Genetic Algorithms.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Jens Rettkowski, Diana Göhringer	RAR-NoC: A reconfigurable and adaptive routable Network-on-Chip for FPGA-based multiprocessor systems.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Osvaldo Navarro, Michael Hübner 0001	An adaptive victim cache scheme.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Fouad Sahraoui, Fakhreddine Ghaffari, Mohamed El Amine Benkhelifa, Bertrand Granado	Context-aware resources placement for SRAM-based FPGA to minimize checkpoint/recovery overhead.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Tobias Kenter, Henning Schmitz, Christian Plessl	Kernel-centric acceleration of high accuracy stereo-matching.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Pavel G. Zaykov, Georgi Kuzmanov, Anca Mariana Molnos, Kees Goossens	Hardware Task-Status Manager for an RTOS with FIFO communication.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Lei Xu 0012, Pham Dang Khoa, Seung-Hun Kim, Won Woo Ro, Weidong Shi	LUT based secure cloud computing - An implementation using FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
1	C. Wilson, Paolo Zicari, Stefan Craciun, P. Gauvin, E. Carlisle, Alan D. George, Herman Lam	A power-efficient real-time architecture for SURF feature extraction.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Hongyuan Ding, Miaoqing Huang	A unified OpenCL-flavor programming model with scalable hybrid hardware platform on FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Bernhard Jungk, Leandro Rodrigues Lima, Matthias Hiller	A systematic study of lightweight hash functions on FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Naoyuki Fujita, Toshifumi Yanagisawa, Hirohisa Kurosaki, Hiroshi Oda	The speed-up of detection of space debris using "InterP" and "FLOPS2D".	ReConFig	2014	DBLP DOI BibTeX RDF
1	Ali Asgar Sohanghpurwala, Peter M. Athanas, Andrew Love	A device-agnostic tool for precomputing legal placements in modular design flows.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Edward A. Lee	Keynote - It's about time.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Di Wu, Andreas Moshovos	Advanced branch predictors for soft processors.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Gavin Vaz, Heinrich Riebler, Tobias Kenter, Christian Plessl	Deferring accelerator offloading decisions to application runtime.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Timm Bostelmann, Sergei Sawitzki	A conceptual toolchain for an application domain specific reconfigurable logic architecture.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Maik Ender, Gerd Duppmann, Alexander Wild, Thomas Pöppelmann, Tim Güneysu	A hardware-assisted proof-of-concept for secure VoIP clients on untrusted operating systems.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Chuan Cheng, Christos-Savvas Bouganis	Memory optimisation for hardware induction of axis-parallel decision tree.	ReConFig	2014	DBLP DOI BibTeX RDF
1	Yu Wang 0136, Hyunchul Shin	An effective window based legalization algorithm for FPGA placement.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez	Lightweight and compact solutions for secure reconfiguration of FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Matthias Hinkfoth, Ralf Joost, Ralf Salomon	Improving calibration precision of signal-delay-based time measurement systems in FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Michael Rückauer, Daniel M. Muñoz, Timo Stripf, Oliver Oey, Carlos H. Llanos, Jürgen Becker 0001	A flexible implementation of the PSO algorithm for fine- and coarse-grained reconfigurable embedded systems.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Kiran Kumar Matam, Viktor K. Prasanna	Energy-efficient large-scale matrix multiplication on FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Mingjie Lin, Shaoyi Cheng, John Wawrzynek	Extracting memory-level parallelism through reconfigurable hardware traces.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Tim Gallagher	Keynote 2 - Past, current, and future of faster, cheaper, better.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Luis F. Gonzalez-Perez, Lennin C. Yllescas-Calderon, Ramón Parra-Michel	Parallel and configurable turbo decoder implementation for 3GPP-LTE.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Durga Prasad Sahoo, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty	Design of low area-overhead ring oscillator PUF with large challenge space.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Yann Thoma, Alberto Dassatti, Daniel Molla	FPGA2: An open source framework for FPGA-GPU PCIe communication.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Jonas Gomes Filho, Jiang Chau Wang	Exploring the problems of placement and mapping in NoC-based reconfizurable systems.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Thomas Schweizer, Wolfgang Rosenstiel, Luigi Vaz Ferreira, Marcus Ritt	Timing error handling on CGRAs.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Ali Ebrahim, Khaled Benkrid, Jalal Khalifat, Chuan Hong	A platform for secure IP integration in Xilinx Virtex FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Raymond J. Weber, Justin A. Hogan, Brock J. LaMeres	Power efficiency benchmarking of a partially reconfigurable, many-tile system implemented on a Xilinx Virtex-6 FPGA.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Da Tong, Viktor K. Prasanna	Online heavy hitter detector on FPGA.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García	A VLSI architecture for the QR decomposition based on the MCGR algorithm.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Milica Orlandic, Kjetil Svarstad	A low complexity H.264/AVC 4×4 intra prediction architecture with macroblock/block reordering.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini	Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Milovan Duric, Oscar Palomar, Aaron Smith	ReCompAc: Reconfigurable compute accelerator.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Horácio C. Neto, Mário P. Véstias	Very low resource table-based FPGA evaluation of elementary functions.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Umer I. Cheema, Ashfaq A. Khokhar	A high performance architecture for computing burrows-wheeler transform on FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Luis Manuel Ledesma-Carrillo, Misael Lopez-Ramirez, Ana L. Martinez-Herrera	FPGA-based reconfigurable unit for image filtering in frequency domain.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Edgar Mora-Sanchez, Jason Helge Anderson	Leakage power reduction in FPGA DSP circuits through algorithmic noise tolerance.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Swamy D. Ponpandi, Zhang Zhang, Akhilesh Tyagi	PolyNOC - A polymorphic thread simulator for NoC communication based embedded systems.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Aydin Aysu, Patrick Schaumont	PASC: Physically authenticated stable-clocked soc platform on low-cost FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Krishna K. Nagar, Jason D. Bakos	Accuracy, cost, and performance tradeoffs for floating-point accumulation.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Markus Weinhardt, Alexander Krieger, Thomas Kinder	A framework for PC applications with portable and scalable FPGA accelerators.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye	Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Byron Navas, Johnny Öberg, Ingo Sander	Towards the generic reconfigurable accelerator: Algorithm development, core design, and performance analysis.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Oguzhan Erdem, Aydin Carus	Range tree-linked list hierarchical search structure for packet classification on FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Moritz Schmid, Markus Blocherer, Frank Hannig, Jürgen Teich	Real-timerange image preprocessing on FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Mohamed Ben Jrad, Régis Leveugle	Automated design flow for no-cost configuration error detection in sram-based FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Ren Chen, Viktor K. Prasanna	Energy-efficient architecture for stride permutation on streaming data.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Jean-Pierre David	Max-hashing fragments for large data sets detection.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Sam Skalicky, Christopher A. Wood, Marcin Lukowiak, Matthew Ryan	High level synthesis: Where are we? A case study on matrix multiplication.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Juan Carlos Moctezuma, Joseph McGeehan, José Luis Núñez-Yáñez	Numerically efficient and biophysically accurate neuroprocessing platform.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Bryant C. Lam, Carlo Pascoe, Scott Schaecher, Herman Lam, Alan D. George	BSW: FPGA-accelerated BLAST-Wrapped Smith-Waterman aligner.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Duarte Lopes de Oliveira, Diego Bompean, Lester de Abreu Faria, Joao Luis V. Oliveira	Design of asynchronous systems on FPGA using direct mapping and synchronous specification.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Kevin Zeng, Peter Athanas	Enhancing productivity with back-end similarity matching of digital circuits for IP reuse.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Cristina I. Muresan, George Dan Mois, Silviu Folea, Clara M. Ionescu	Alternative implementations of a fractional order control algorithm on FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Elif Bilge Kavun, Gregor Leander, Tolga Yalçin	A reconfigurable architecture for searching optimal software code to implement block cipher permutation matrices.	ReConFig	2013	DBLP DOI BibTeX RDF
1	Emna Amouri, Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Zied Marrakchi	Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture.	ReConFig	2013	DBLP DOI BibTeX RDF

Publications at "ReConFig"( http://dblp.L3S.de/Venues/ReConFig )